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authorGravatar Fernando Sahmkow2020-06-19 19:40:07 -0400
committerGravatar Fernando Sahmkow2020-06-27 11:36:27 -0400
commit4105f38022a525aab2e7d4288f121b4f0a0dd7b2 (patch)
tree3cf68e47fcc17442111b8af16a3fff19b3f3434f /src/core/arm
parentSVC: Add GetCurrentProcessorNumber32, CreateTransferMemory32, SetMemoryAttrib... (diff)
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SVC: Implement 32-bits wrappers and update Dynarmic.
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h5
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp8
2 files changed, 9 insertions, 4 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index fbdce4134..0c1d6ac39 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -33,16 +33,15 @@ public:
33 33
34 struct ThreadContext32 { 34 struct ThreadContext32 {
35 std::array<u32, 16> cpu_registers{}; 35 std::array<u32, 16> cpu_registers{};
36 std::array<u32, 64> extension_registers{};
36 u32 cpsr{}; 37 u32 cpsr{};
37 std::array<u8, 4> padding{};
38 std::array<u64, 32> fprs{};
39 u32 fpscr{}; 38 u32 fpscr{};
40 u32 fpexc{}; 39 u32 fpexc{};
41 u32 tpidr{}; 40 u32 tpidr{};
42 }; 41 };
43 // Internally within the kernel, it expects the AArch32 version of the 42 // Internally within the kernel, it expects the AArch32 version of the
44 // thread context to be 344 bytes in size. 43 // thread context to be 344 bytes in size.
45 static_assert(sizeof(ThreadContext32) == 0x158); 44 static_assert(sizeof(ThreadContext32) == 0x150);
46 45
47 struct ThreadContext64 { 46 struct ThreadContext64 {
48 std::array<u64, 31> cpu_registers{}; 47 std::array<u64, 31> cpu_registers{};
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 5df4fc079..cfda12098 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -222,13 +222,17 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
222 Dynarmic::A32::Context context; 222 Dynarmic::A32::Context context;
223 jit->SaveContext(context); 223 jit->SaveContext(context);
224 ctx.cpu_registers = context.Regs(); 224 ctx.cpu_registers = context.Regs();
225 ctx.extension_registers = context.ExtRegs();
225 ctx.cpsr = context.Cpsr(); 226 ctx.cpsr = context.Cpsr();
227 ctx.fpscr = context.Fpscr();
226} 228}
227 229
228void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { 230void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
229 Dynarmic::A32::Context context; 231 Dynarmic::A32::Context context;
230 context.Regs() = ctx.cpu_registers; 232 context.Regs() = ctx.cpu_registers;
233 context.ExtRegs() = ctx.extension_registers;
231 context.SetCpsr(ctx.cpsr); 234 context.SetCpsr(ctx.cpsr);
235 context.SetFpscr(ctx.fpscr);
232 jit->LoadContext(context); 236 jit->LoadContext(context);
233} 237}
234 238
@@ -243,7 +247,9 @@ void ARM_Dynarmic_32::ClearInstructionCache() {
243 jit->ClearCache(); 247 jit->ClearCache();
244} 248}
245 249
246void ARM_Dynarmic_32::ClearExclusiveState() {} 250void ARM_Dynarmic_32::ClearExclusiveState() {
251 jit->ClearExclusiveState();
252}
247 253
248void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table, 254void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
249 std::size_t new_address_space_size_in_bits) { 255 std::size_t new_address_space_size_in_bits) {