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authorGravatar bunnei2014-12-22 00:12:43 -0500
committerGravatar bunnei2014-12-22 00:12:43 -0500
commit2188af4a653d56fcaf59e90399beb2c355762140 (patch)
treeb9c5bf92b6cebe6ecb7de4685049afdbc54d839d /src/core/arm
parentMerge pull request #325 from yuriks/cmake-opts (diff)
parentMore warning cleanups (diff)
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Merge pull request #322 from chinhodado/master
More warning cleanups
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp12
-rw-r--r--src/core/arm/dyncom/arm_dyncom_run.cpp1
3 files changed, 6 insertions, 9 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index 19d94f369..70eb96e93 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -56,8 +56,6 @@
56#define RN ((instr >> 16) & 0xF) 56#define RN ((instr >> 16) & 0xF)
57/*xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 */ 57/*xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 */
58#define RM (instr & 0xF) 58#define RM (instr & 0xF)
59#define BIT(n) ((instr >> (n)) & 1)
60#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
61 59
62/* CP15 registers */ 60/* CP15 registers */
63#define OPCODE_1 BITS(21, 23) 61#define OPCODE_1 BITS(21, 23)
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index df698e8f1..ae407585e 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3798,9 +3798,9 @@ unsigned InterpreterMainLoop(ARMul_State* state)
3798 #define INC_ICOUNTER cpu->icounter++; \ 3798 #define INC_ICOUNTER cpu->icounter++; \
3799 if(cpu->Reg[15] > 0xc0000000) \ 3799 if(cpu->Reg[15] > 0xc0000000) \
3800 cpu->kernel_icounter++; 3800 cpu->kernel_icounter++;
3801 //if (debug_function(core)) \ 3801 /*if (debug_function(core)) \
3802 if (core->check_int_flag) \ 3802 if (core->check_int_flag) \
3803 goto END 3803 goto END*/
3804 //LOG_TRACE(Core_ARM11, "icounter is %llx pc is %x\n", cpu->icounter, cpu->Reg[15]) 3804 //LOG_TRACE(Core_ARM11, "icounter is %llx pc is %x\n", cpu->icounter, cpu->Reg[15])
3805 #else 3805 #else
3806 #define INC_ICOUNTER ; 3806 #define INC_ICOUNTER ;
@@ -4021,18 +4021,18 @@ unsigned InterpreterMainLoop(ARMul_State* state)
4021 4021
4022 #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) 4022 #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0)
4023 #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) 4023 #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1)
4024// #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((ISNEG(lop) && ISPOS(rop)) || \ 4024/* #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((ISNEG(lop) && ISPOS(rop)) || \
4025 (ISNEG(lop) && ISPOS(dst)) || \ 4025 (ISNEG(lop) && ISPOS(dst)) || \
4026 (ISPOS(rop) && ISPOS(dst)))) 4026 (ISPOS(rop) && ISPOS(dst)))) */
4027 #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((dst < lop) || (dst < rop))) 4027 #define UPDATE_CFLAG(dst, lop, rop) (cpu->CFlag = ((dst < lop) || (dst < rop)))
4028 #define UPDATE_CFLAG_CARRY_FROM_ADD(lop, rop, flag) (cpu->CFlag = (((uint64_t) lop + (uint64_t) rop + (uint64_t) flag) > 0xffffffff) ) 4028 #define UPDATE_CFLAG_CARRY_FROM_ADD(lop, rop, flag) (cpu->CFlag = (((uint64_t) lop + (uint64_t) rop + (uint64_t) flag) > 0xffffffff) )
4029 #define UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(lop, rop, flag) (cpu->CFlag = ((uint64_t) lop >= ((uint64_t) rop + (uint64_t) flag))) 4029 #define UPDATE_CFLAG_NOT_BORROW_FROM_FLAG(lop, rop, flag) (cpu->CFlag = ((uint64_t) lop >= ((uint64_t) rop + (uint64_t) flag)))
4030 #define UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop) (cpu->CFlag = (lop >= rop)) 4030 #define UPDATE_CFLAG_NOT_BORROW_FROM(lop, rop) (cpu->CFlag = (lop >= rop))
4031 #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) (cpu->CFlag = !(dst < lop)) 4031 #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) (cpu->CFlag = !(dst < lop))
4032 #define UPDATE_CFLAG_WITH_SC cpu->CFlag = cpu->shifter_carry_out 4032 #define UPDATE_CFLAG_WITH_SC cpu->CFlag = cpu->shifter_carry_out
4033// #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) cpu->CFlag = !((ISNEG(lop) && ISPOS(rop)) || \ 4033/* #define UPDATE_CFLAG_WITH_NOT(dst, lop, rop) cpu->CFlag = !((ISNEG(lop) && ISPOS(rop)) || \
4034 (ISNEG(lop) && ISPOS(dst)) || \ 4034 (ISNEG(lop) && ISPOS(dst)) || \
4035 (ISPOS(rop) && ISPOS(dst))) 4035 (ISPOS(rop) && ISPOS(dst))) */
4036 #define UPDATE_VFLAG(dst, lop, rop) (cpu->VFlag = (((lop < 0) && (rop < 0) && (dst >= 0)) || \ 4036 #define UPDATE_VFLAG(dst, lop, rop) (cpu->VFlag = (((lop < 0) && (rop < 0) && (dst >= 0)) || \
4037 ((lop >= 0) && (rop) >= 0 && (dst < 0)))) 4037 ((lop >= 0) && (rop) >= 0 && (dst < 0))))
4038 #define UPDATE_VFLAG_WITH_NOT(dst, lop, rop) (cpu->VFlag = !(((lop < 0) && (rop < 0) && (dst >= 0)) || \ 4038 #define UPDATE_VFLAG_WITH_NOT(dst, lop, rop) (cpu->VFlag = !(((lop < 0) && (rop < 0) && (dst >= 0)) || \
diff --git a/src/core/arm/dyncom/arm_dyncom_run.cpp b/src/core/arm/dyncom/arm_dyncom_run.cpp
index a2026cbf3..b66b92cf5 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_run.cpp
@@ -29,7 +29,6 @@
29 29
30void switch_mode(arm_core_t *core, uint32_t mode) 30void switch_mode(arm_core_t *core, uint32_t mode)
31{ 31{
32 uint32_t tmp1, tmp2;
33 if (core->Mode == mode) { 32 if (core->Mode == mode) {
34 //Mode not changed. 33 //Mode not changed.
35 //printf("mode not changed\n"); 34 //printf("mode not changed\n");