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authorGravatar Subv2015-05-10 18:43:59 -0500
committerGravatar Subv2015-05-10 18:43:59 -0500
commit115ad8e16a69c8823118f210654fc9ea70a03213 (patch)
tree945fc0617a3329e14f0b4ec3cf2679a0054cbb7b /src/core/arm
parentCore/Memory: Give every emulated thread it's own TLS area. (diff)
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fixup! Set the TLS address in the scheduler
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h3
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp5
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h2
3 files changed, 3 insertions, 7 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 976c339e8..85ed2c698 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -99,9 +99,8 @@ public:
99 * @param stack_top Pointer to the top of the stack 99 * @param stack_top Pointer to the top of the stack
100 * @param entry_point Entry point for execution 100 * @param entry_point Entry point for execution
101 * @param arg User argument for thread 101 * @param arg User argument for thread
102 * @param tls_address Address of the Thread Local Storage for the thread
103 */ 102 */
104 virtual void ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg, u32 tls_address) = 0; 103 virtual void ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) = 0;
105 104
106 /** 105 /**
107 * Saves the current CPU context 106 * Saves the current CPU context
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 1de1d2612..0072ae533 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -90,14 +90,13 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
90 AddTicks(ticks_executed); 90 AddTicks(ticks_executed);
91} 91}
92 92
93void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg, u32 tls_address) { 93void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) {
94 memset(&context, 0, sizeof(Core::ThreadContext)); 94 memset(&context, 0, sizeof(Core::ThreadContext));
95 95
96 context.cpu_registers[0] = arg; 96 context.cpu_registers[0] = arg;
97 context.pc = entry_point; 97 context.pc = entry_point;
98 context.sp = stack_top; 98 context.sp = stack_top;
99 context.cpsr = 0x1F; // Usermode 99 context.cpsr = 0x1F; // Usermode
100 context.tls = tls_address;
101} 100}
102 101
103void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { 102void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
@@ -124,8 +123,6 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
124 123
125 state->VFP[1] = ctx.fpscr; 124 state->VFP[1] = ctx.fpscr;
126 state->VFP[2] = ctx.fpexc; 125 state->VFP[2] = ctx.fpexc;
127
128 SetCP15Register(CP15_THREAD_URO, ctx.tls);
129} 126}
130 127
131void ARM_DynCom::PrepareReschedule() { 128void ARM_DynCom::PrepareReschedule() {
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index b3fd708f1..2488c879c 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -27,7 +27,7 @@ public:
27 27
28 void AddTicks(u64 ticks) override; 28 void AddTicks(u64 ticks) override;
29 29
30 void ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg, u32 tls_address) override; 30 void ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) override;
31 void SaveContext(Core::ThreadContext& ctx) override; 31 void SaveContext(Core::ThreadContext& ctx) override;
32 void LoadContext(const Core::ThreadContext& ctx) override; 32 void LoadContext(const Core::ThreadContext& ctx) override;
33 33