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authorGravatar Lioncash2015-07-21 05:49:05 -0400
committerGravatar Lioncash2015-07-21 05:49:05 -0400
commit043b2f882aa48488ba632621cd62c5784e1c8fab (patch)
treebd812292360525f0172a469e11f81ac57339852d /src/core/arm
parentResolve issue accidentally left unaddressed in PR #930 (diff)
parentdyncom: Pass SVC immediates directly. (diff)
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Merge pull request #964 from lioncash/svc
dyncom: Pass SVC immediates directly.
Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index e40f3fa93..785f39566 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -6248,7 +6248,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6248 SWI_INST: 6248 SWI_INST:
6249 { 6249 {
6250 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 6250 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
6251 SVC::CallSVC(Memory::Read32(cpu->Reg[15])); 6251 swi_inst* const inst_cream = (swi_inst*)inst_base->component;
6252 SVC::CallSVC(inst_cream->num & 0xFFFF);
6252 } 6253 }
6253 6254
6254 cpu->Reg[15] += GET_INST_SIZE(cpu); 6255 cpu->Reg[15] += GET_INST_SIZE(cpu);