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authorGravatar bunnei2014-12-30 18:50:47 -0500
committerGravatar bunnei2014-12-30 23:56:45 -0500
commit631f13e462239bbbec929bc00d042191c9ebb06f (patch)
treeda601e8a202deaad9aec76ebcfd8d38fee534afd /src/core/arm/skyeye_common
parentMerge pull request #369 from darkf/mingw_ (diff)
downloadyuzu-631f13e462239bbbec929bc00d042191c9ebb06f.tar.gz
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dyncom: Massive refactor
Diffstat (limited to 'src/core/arm/skyeye_common')
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp170
1 files changed, 30 insertions, 140 deletions
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index cc70fc33c..b5fcbac86 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -2891,32 +2891,15 @@ VSTR_INST:
2891 2891
2892 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); 2892 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]);
2893 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); 2893 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32);
2894 DBG("VSTR :\n"); 2894
2895
2896
2897 if (inst_cream->single) 2895 if (inst_cream->single)
2898 { 2896 {
2899 fault = check_address_validity(cpu, addr, &phys_addr, 0); 2897 Memory::Write32(addr, cpu->ExtReg[inst_cream->d]);
2900 if (fault) goto MMU_EXCEPTION;
2901 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
2902 if (fault) goto MMU_EXCEPTION;
2903 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d, cpu->ExtReg[inst_cream->d]);
2904 } 2898 }
2905 else 2899 else
2906 { 2900 {
2907 fault = check_address_validity(cpu, addr, &phys_addr, 0); 2901 Memory::Write32(addr, cpu->ExtReg[inst_cream->d*2]);
2908 if (fault) goto MMU_EXCEPTION; 2902 Memory::Write32(addr + 4, cpu->ExtReg[inst_cream->d*2+1]);
2909
2910 /* Check endianness */
2911 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d*2], 32);
2912 if (fault) goto MMU_EXCEPTION;
2913
2914 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
2915 if (fault) goto MMU_EXCEPTION;
2916
2917 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[inst_cream->d*2+1], 32);
2918 if (fault) goto MMU_EXCEPTION;
2919 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, inst_cream->d*2+1, inst_cream->d*2, cpu->ExtReg[inst_cream->d*2+1], cpu->ExtReg[inst_cream->d*2]);
2920 } 2903 }
2921 } 2904 }
2922 cpu->Reg[15] += GET_INST_SIZE(cpu); 2905 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -3027,47 +3010,27 @@ VPUSH_INST:
3027{ 3010{
3028 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 3011 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
3029 CHECK_VFP_ENABLED; 3012 CHECK_VFP_ENABLED;
3030
3031 int i; 3013 int i;
3032 3014
3033 vpush_inst *inst_cream = (vpush_inst *)inst_base->component; 3015 vpush_inst *inst_cream = (vpush_inst *)inst_base->component;
3034 3016
3035 DBG("VPUSH :\n");
3036
3037 addr = cpu->Reg[R13] - inst_cream->imm32; 3017 addr = cpu->Reg[R13] - inst_cream->imm32;
3038 3018
3039
3040 for (i = 0; i < inst_cream->regs; i++) 3019 for (i = 0; i < inst_cream->regs; i++)
3041 { 3020 {
3042 if (inst_cream->single) 3021 if (inst_cream->single)
3043 { 3022 {
3044 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3023 Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3045 if (fault) goto MMU_EXCEPTION;
3046 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3047 if (fault) goto MMU_EXCEPTION;
3048 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3049 addr += 4; 3024 addr += 4;
3050 } 3025 }
3051 else 3026 else
3052 { 3027 {
3053 /* Careful of endianness, little by default */ 3028 Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3054 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3029 Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3055 if (fault) goto MMU_EXCEPTION;
3056 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3057 if (fault) goto MMU_EXCEPTION;
3058
3059 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
3060 if (fault) goto MMU_EXCEPTION;
3061 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3062 if (fault) goto MMU_EXCEPTION;
3063 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3064 addr += 8; 3030 addr += 8;
3065 } 3031 }
3066 } 3032 }
3067 DBG("\tsp[%x]", cpu->Reg[R13]);
3068 cpu->Reg[R13] = cpu->Reg[R13] - inst_cream->imm32; 3033 cpu->Reg[R13] = cpu->Reg[R13] - inst_cream->imm32;
3069 DBG("=>[%x]\n", cpu->Reg[R13]);
3070
3071 } 3034 }
3072 cpu->Reg[15] += GET_INST_SIZE(cpu); 3035 cpu->Reg[15] += GET_INST_SIZE(cpu);
3073 INC_PC(sizeof(vpush_inst)); 3036 INC_PC(sizeof(vpush_inst));
@@ -3110,7 +3073,7 @@ int DYNCOM_TRANS(vpush)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3110 { 3073 {
3111 if (single) 3074 if (single)
3112 { 3075 {
3113 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3076 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3114 #if 0 3077 #if 0
3115 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3078 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
3116 bb = cpu->dyncom_engine->bb; 3079 bb = cpu->dyncom_engine->bb;
@@ -3199,43 +3162,24 @@ VSTM_INST: /* encoding 1 */
3199 vstm_inst *inst_cream = (vstm_inst *)inst_base->component; 3162 vstm_inst *inst_cream = (vstm_inst *)inst_base->component;
3200 3163
3201 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32); 3164 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32);
3202 DBG("VSTM : addr[%x]\n", addr); 3165
3203
3204
3205 for (i = 0; i < inst_cream->regs; i++) 3166 for (i = 0; i < inst_cream->regs; i++)
3206 { 3167 {
3207 if (inst_cream->single) 3168 if (inst_cream->single)
3208 { 3169 {
3209 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3170 Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3210 if (fault) goto MMU_EXCEPTION;
3211
3212 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3213 if (fault) goto MMU_EXCEPTION;
3214 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3215 addr += 4; 3171 addr += 4;
3216 } 3172 }
3217 else 3173 else
3218 { 3174 {
3219 /* Careful of endianness, little by default */ 3175 Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3220 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3176 Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3221 if (fault) goto MMU_EXCEPTION;
3222
3223 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3224 if (fault) goto MMU_EXCEPTION;
3225
3226 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
3227 if (fault) goto MMU_EXCEPTION;
3228
3229 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3230 if (fault) goto MMU_EXCEPTION;
3231 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3232 addr += 8; 3177 addr += 8;
3233 } 3178 }
3234 } 3179 }
3235 if (inst_cream->wback){ 3180 if (inst_cream->wback){
3236 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : 3181 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
3237 cpu->Reg[inst_cream->n] - inst_cream->imm32); 3182 cpu->Reg[inst_cream->n] - inst_cream->imm32);
3238 DBG("\twback r%d[%x]\n", inst_cream->n, cpu->Reg[inst_cream->n]);
3239 } 3183 }
3240 3184
3241 } 3185 }
@@ -3290,7 +3234,7 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3290 if (single) 3234 if (single)
3291 { 3235 {
3292 3236
3293 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3237 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3294 /* if R(i) is R15? */ 3238 /* if R(i) is R15? */
3295 #if 0 3239 #if 0
3296 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3240 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
@@ -3300,14 +3244,13 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3300 //memory_write(cpu, bb, Addr, RSPR(d + i), 32); 3244 //memory_write(cpu, bb, Addr, RSPR(d + i), 32);
3301 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32); 3245 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32);
3302 bb = cpu->dyncom_engine->bb; 3246 bb = cpu->dyncom_engine->bb;
3303 //if (fault) goto MMU_EXCEPTION;
3304 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]); 3247 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3305 Addr = ADD(Addr, CONST(4)); 3248 Addr = ADD(Addr, CONST(4));
3306 } 3249 }
3307 else 3250 else
3308 { 3251 {
3309 3252
3310 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32); 3253 //Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3311 #if 0 3254 #if 0
3312 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3255 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
3313 bb = cpu->dyncom_engine->bb; 3256 bb = cpu->dyncom_engine->bb;
@@ -3316,9 +3259,8 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3316 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32); 3259 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
3317 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32); 3260 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32);
3318 bb = cpu->dyncom_engine->bb; 3261 bb = cpu->dyncom_engine->bb;
3319 //if (fault) goto MMU_EXCEPTION;
3320 3262
3321 //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32); 3263 //Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3322 #if 0 3264 #if 0
3323 phys_addr = get_phys_addr(cpu, bb, ADD(Addr, CONST(4)), 0); 3265 phys_addr = get_phys_addr(cpu, bb, ADD(Addr, CONST(4)), 0);
3324 bb = cpu->dyncom_engine->bb; 3266 bb = cpu->dyncom_engine->bb;
@@ -3327,7 +3269,6 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3327 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32); 3269 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
3328 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32); 3270 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
3329 bb = cpu->dyncom_engine->bb; 3271 bb = cpu->dyncom_engine->bb;
3330 //if (fault) goto MMU_EXCEPTION;
3331 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]); 3272 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3332 //addr += 8; 3273 //addr += 8;
3333 Addr = ADD(Addr, CONST(8)); 3274 Addr = ADD(Addr, CONST(8));
@@ -3385,49 +3326,27 @@ VPOP_INST:
3385 unsigned int value1, value2; 3326 unsigned int value1, value2;
3386 3327
3387 vpop_inst *inst_cream = (vpop_inst *)inst_base->component; 3328 vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
3388 3329
3389 DBG("VPOP :\n");
3390
3391 addr = cpu->Reg[R13]; 3330 addr = cpu->Reg[R13];
3392
3393 3331
3394 for (i = 0; i < inst_cream->regs; i++) 3332 for (i = 0; i < inst_cream->regs; i++)
3395 { 3333 {
3396 if (inst_cream->single) 3334 if (inst_cream->single)
3397 { 3335 {
3398 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3336 value1 = Memory::Read32(addr);
3399 if (fault) goto MMU_EXCEPTION;
3400
3401 fault = interpreter_read_memory(addr, phys_addr, value1, 32);
3402 if (fault) goto MMU_EXCEPTION;
3403 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, value1, addr);
3404 cpu->ExtReg[inst_cream->d+i] = value1; 3337 cpu->ExtReg[inst_cream->d+i] = value1;
3405 addr += 4; 3338 addr += 4;
3406 } 3339 }
3407 else 3340 else
3408 { 3341 {
3409 /* Careful of endianness, little by default */ 3342 value1 = Memory::Read32(addr);
3410 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3343 value2 = Memory::Read32(addr + 4);
3411 if (fault) goto MMU_EXCEPTION;
3412
3413 fault = interpreter_read_memory(addr, phys_addr, value1, 32);
3414 if (fault) goto MMU_EXCEPTION;
3415
3416 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3417 if (fault) goto MMU_EXCEPTION;
3418
3419 fault = interpreter_read_memory(addr + 4, phys_addr, value2, 32);
3420 if (fault) goto MMU_EXCEPTION;
3421 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, value2, value1, addr+4, addr);
3422 cpu->ExtReg[(inst_cream->d+i)*2] = value1; 3344 cpu->ExtReg[(inst_cream->d+i)*2] = value1;
3423 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = value2; 3345 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = value2;
3424 addr += 8; 3346 addr += 8;
3425 } 3347 }
3426 } 3348 }
3427 DBG("\tsp[%x]", cpu->Reg[R13]);
3428 cpu->Reg[R13] = cpu->Reg[R13] + inst_cream->imm32; 3349 cpu->Reg[R13] = cpu->Reg[R13] + inst_cream->imm32;
3429 DBG("=>[%x]\n", cpu->Reg[R13]);
3430
3431 } 3350 }
3432 cpu->Reg[15] += GET_INST_SIZE(cpu); 3351 cpu->Reg[15] += GET_INST_SIZE(cpu);
3433 INC_PC(sizeof(vpop_inst)); 3352 INC_PC(sizeof(vpop_inst));
@@ -3565,33 +3484,19 @@ VLDR_INST:
3565 3484
3566 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); 3485 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]);
3567 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); 3486 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32);
3568 DBG("VLDR :\n", addr); 3487
3569
3570
3571 if (inst_cream->single) 3488 if (inst_cream->single)
3572 { 3489 {
3573 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3490 cpu->ExtReg[inst_cream->d] = Memory::Read32(addr);
3574 if (fault) goto MMU_EXCEPTION;
3575 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
3576 if (fault) goto MMU_EXCEPTION;
3577 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d, cpu->ExtReg[inst_cream->d], addr);
3578 } 3491 }
3579 else 3492 else
3580 { 3493 {
3581 unsigned int word1, word2; 3494 unsigned int word1, word2;
3582 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3495 word1 = Memory::Read32(addr);
3583 if (fault) goto MMU_EXCEPTION; 3496 word2 = Memory::Read32(addr + 4);
3584 fault = interpreter_read_memory(addr, phys_addr, word1, 32); 3497
3585 if (fault) goto MMU_EXCEPTION;
3586
3587 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3588 if (fault) goto MMU_EXCEPTION;
3589 fault = interpreter_read_memory(addr + 4, phys_addr, word2, 32);
3590 if (fault) goto MMU_EXCEPTION;
3591 /* Check endianness */
3592 cpu->ExtReg[inst_cream->d*2] = word1; 3498 cpu->ExtReg[inst_cream->d*2] = word1;
3593 cpu->ExtReg[inst_cream->d*2+1] = word2; 3499 cpu->ExtReg[inst_cream->d*2+1] = word2;
3594 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", inst_cream->d*2+1, inst_cream->d*2, word2, word1, addr+4, addr);
3595 } 3500 }
3596 } 3501 }
3597 cpu->Reg[15] += GET_INST_SIZE(cpu); 3502 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -3729,32 +3634,18 @@ VLDM_INST:
3729 vldm_inst *inst_cream = (vldm_inst *)inst_base->component; 3634 vldm_inst *inst_cream = (vldm_inst *)inst_base->component;
3730 3635
3731 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32); 3636 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32);
3732 DBG("VLDM : addr[%x]\n", addr); 3637
3733
3734 for (i = 0; i < inst_cream->regs; i++) 3638 for (i = 0; i < inst_cream->regs; i++)
3735 { 3639 {
3736 if (inst_cream->single) 3640 if (inst_cream->single)
3737 { 3641 {
3738 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3642 cpu->ExtReg[inst_cream->d+i] = Memory::Read32(addr);
3739 if (fault) goto MMU_EXCEPTION;
3740 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3741 if (fault) goto MMU_EXCEPTION;
3742 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, cpu->ExtReg[inst_cream->d+i], addr);
3743 addr += 4; 3643 addr += 4;
3744 } 3644 }
3745 else 3645 else
3746 { 3646 {
3747 /* Careful of endianness, little by default */ 3647 cpu->ExtReg[(inst_cream->d+i)*2] = Memory::Read32(addr);
3748 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3648 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = Memory::Read32(addr + 4);
3749 if (fault) goto MMU_EXCEPTION;
3750 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3751 if (fault) goto MMU_EXCEPTION;
3752
3753 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3754 if (fault) goto MMU_EXCEPTION;
3755 fault = interpreter_read_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3756 if (fault) goto MMU_EXCEPTION;
3757 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2], addr+4, addr);
3758 addr += 8; 3649 addr += 8;
3759 } 3650 }
3760 } 3651 }
@@ -3815,7 +3706,7 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3815 if (single) 3706 if (single)
3816 { 3707 {
3817 3708
3818 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3709 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3819 /* if R(i) is R15? */ 3710 /* if R(i) is R15? */
3820 #if 0 3711 #if 0
3821 phys_addr = get_phys_addr(cpu, bb, Addr, 1); 3712 phys_addr = get_phys_addr(cpu, bb, Addr, 1);
@@ -3827,7 +3718,6 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3827 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb); 3718 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3828 //LETS(d + i, val); 3719 //LETS(d + i, val);
3829 LETFPS(d + i, FPBITCAST32(val)); 3720 LETFPS(d + i, FPBITCAST32(val));
3830 //if (fault) goto MMU_EXCEPTION;
3831 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]); 3721 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3832 Addr = ADD(Addr, CONST(4)); 3722 Addr = ADD(Addr, CONST(4));
3833 } 3723 }
@@ -3852,7 +3742,7 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3852 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb); 3742 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3853 LETFPS((d + i) * 2 + 1, FPBITCAST32(val)); 3743 LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
3854 3744
3855 //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32); 3745 //Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3856 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]); 3746 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3857 //addr += 8; 3747 //addr += 8;
3858 Addr = ADD(Addr, CONST(8)); 3748 Addr = ADD(Addr, CONST(8));
HIC SVNT DRACONES