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| author | 2015-03-26 15:25:04 -0400 | |
|---|---|---|
| committer | 2015-04-02 00:20:52 -0400 | |
| commit | 490df716f327b1cff6097f607c13f08f948dbf3b (patch) | |
| tree | 0ba1f8b3b58ac4c31722b5fac1dad33f0adef2ca /src/core/arm/skyeye_common | |
| parent | dyncom: Move CP15 register reading into its own function. (diff) | |
| download | yuzu-490df716f327b1cff6097f607c13f08f948dbf3b.tar.gz yuzu-490df716f327b1cff6097f607c13f08f948dbf3b.tar.xz yuzu-490df716f327b1cff6097f607c13f08f948dbf3b.zip | |
dyncom: Move CP15 register writing into its own function.
Also implements writing to the rest of the ARM11 MPCore CP15 register set.
Diffstat (limited to 'src/core/arm/skyeye_common')
| -rw-r--r-- | src/core/arm/skyeye_common/arm_regformat.h | 33 | ||||
| -rw-r--r-- | src/core/arm/skyeye_common/armdefs.h | 1 |
2 files changed, 34 insertions, 0 deletions
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h index fb5b70f1e..c232376e0 100644 --- a/src/core/arm/skyeye_common/arm_regformat.h +++ b/src/core/arm/skyeye_common/arm_regformat.h | |||
| @@ -105,7 +105,40 @@ enum { | |||
| 105 | CP15_IFAR, | 105 | CP15_IFAR, |
| 106 | 106 | ||
| 107 | // c7 - Cache operation registers | 107 | // c7 - Cache operation registers |
| 108 | CP15_WAIT_FOR_INTERRUPT, | ||
| 108 | CP15_PHYS_ADDRESS, | 109 | CP15_PHYS_ADDRESS, |
| 110 | CP15_INVALIDATE_INSTR_CACHE, | ||
| 111 | CP15_INVALIDATE_INSTR_CACHE_USING_MVA, | ||
| 112 | CP15_INVALIDATE_INSTR_CACHE_USING_INDEX, | ||
| 113 | CP15_FLUSH_PREFETCH_BUFFER, | ||
| 114 | CP15_FLUSH_BRANCH_TARGET_CACHE, | ||
| 115 | CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY, | ||
| 116 | CP15_INVALIDATE_DATA_CACHE, | ||
| 117 | CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA, | ||
| 118 | CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, | ||
| 119 | CP15_INVALIDATE_DATA_AND_INSTR_CACHE, | ||
| 120 | CP15_CLEAN_DATA_CACHE, | ||
| 121 | CP15_CLEAN_DATA_CACHE_LINE_USING_MVA, | ||
| 122 | CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX, | ||
| 123 | CP15_DATA_SYNC_BARRIER, | ||
| 124 | CP15_DATA_MEMORY_BARRIER, | ||
| 125 | CP15_CLEAN_AND_INVALIDATE_DATA_CACHE, | ||
| 126 | CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA, | ||
| 127 | CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX, | ||
| 128 | |||
| 129 | // c8 - TLB operations | ||
| 130 | CP15_INVALIDATE_ITLB, | ||
| 131 | CP15_INVALIDATE_ITLB_SINGLE_ENTRY, | ||
| 132 | CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH, | ||
| 133 | CP15_INVALIDATE_ITLB_ENTRY_ON_MVA, | ||
| 134 | CP15_INVALIDATE_DTLB, | ||
| 135 | CP15_INVALIDATE_DTLB_SINGLE_ENTRY, | ||
| 136 | CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH, | ||
| 137 | CP15_INVALIDATE_DTLB_ENTRY_ON_MVA, | ||
| 138 | CP15_INVALIDATE_UTLB, | ||
| 139 | CP15_INVALIDATE_UTLB_SINGLE_ENTRY, | ||
| 140 | CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH, | ||
| 141 | CP15_INVALIDATE_UTLB_ENTRY_ON_MVA, | ||
| 109 | 142 | ||
| 110 | // c9 - Data cache lockdown register | 143 | // c9 - Data cache lockdown register |
| 111 | CP15_DATA_CACHE_LOCKDOWN, | 144 | CP15_DATA_CACHE_LOCKDOWN, |
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h index 14f2a39d1..d5b0242c3 100644 --- a/src/core/arm/skyeye_common/armdefs.h +++ b/src/core/arm/skyeye_common/armdefs.h | |||
| @@ -360,3 +360,4 @@ extern bool InBigEndianMode(ARMul_State*); | |||
| 360 | extern bool InAPrivilegedMode(ARMul_State*); | 360 | extern bool InAPrivilegedMode(ARMul_State*); |
| 361 | 361 | ||
| 362 | extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); | 362 | extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); |
| 363 | extern void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); | ||