summaryrefslogtreecommitdiff
path: root/src/core/arm/skyeye_common
diff options
context:
space:
mode:
authorGravatar Lioncash2015-02-10 09:34:39 -0500
committerGravatar Lioncash2015-02-10 09:34:42 -0500
commit3eccc66abf5f4a47e3d821cfaaacbe76b4bc3406 (patch)
treed3d70fbf67548ac2790b603f145746fbd3a0cfcc /src/core/arm/skyeye_common
parentMerge pull request #543 from Alegend45/master (diff)
downloadyuzu-3eccc66abf5f4a47e3d821cfaaacbe76b4bc3406.tar.gz
yuzu-3eccc66abf5f4a47e3d821cfaaacbe76b4bc3406.tar.xz
yuzu-3eccc66abf5f4a47e3d821cfaaacbe76b4bc3406.zip
dyncom: Add more regs to MCR/MRC
Adds the registers that were left out of some coprocessor ranges.
Diffstat (limited to 'src/core/arm/skyeye_common')
-rw-r--r--src/core/arm/skyeye_common/arm_regformat.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
index 997874764..5be3a561f 100644
--- a/src/core/arm/skyeye_common/arm_regformat.h
+++ b/src/core/arm/skyeye_common/arm_regformat.h
@@ -86,7 +86,9 @@ enum {
86 CP15_IFAR, 86 CP15_IFAR,
87 CP15_PID, 87 CP15_PID,
88 CP15_CONTEXT_ID, 88 CP15_CONTEXT_ID,
89 CP15_THREAD_URO, 89 CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
90 CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
91 CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
90 CP15_TLB_FAULT_ADDR, /* defined by SkyEye */ 92 CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
91 CP15_TLB_FAULT_STATUS, /* defined by SkyEye */ 93 CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
92 /* VFP registers */ 94 /* VFP registers */