summaryrefslogtreecommitdiff
path: root/src/core/arm/skyeye_common
diff options
context:
space:
mode:
authorGravatar Lioncash2015-01-30 13:24:19 -0500
committerGravatar Lioncash2015-01-30 13:32:03 -0500
commit09a66860e235242f4bcdf52f0cf71284fb35bfa8 (patch)
tree564c496932549bf8de83b9e199f0380cd5d6f2e1 /src/core/arm/skyeye_common
parentarmdefs: Move some defines over to enums (diff)
downloadyuzu-09a66860e235242f4bcdf52f0cf71284fb35bfa8.tar.gz
yuzu-09a66860e235242f4bcdf52f0cf71284fb35bfa8.tar.xz
yuzu-09a66860e235242f4bcdf52f0cf71284fb35bfa8.zip
arm: Throw out a lot of unnecessary code
Diffstat (limited to 'src/core/arm/skyeye_common')
-rw-r--r--src/core/arm/skyeye_common/armdefs.h212
-rw-r--r--src/core/arm/skyeye_common/armemu.h5
-rw-r--r--src/core/arm/skyeye_common/skyeye_defs.h82
3 files changed, 20 insertions, 279 deletions
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index d5939313b..a9c41ce5a 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -15,8 +15,7 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#ifndef _ARMDEFS_H_ 18#pragma once
19#define _ARMDEFS_H_
20 19
21#include <cerrno> 20#include <cerrno>
22#include <csignal> 21#include <csignal>
@@ -33,21 +32,6 @@
33#include "core/arm/skyeye_common/armmmu.h" 32#include "core/arm/skyeye_common/armmmu.h"
34#include "core/arm/skyeye_common/skyeye_defs.h" 33#include "core/arm/skyeye_common/skyeye_defs.h"
35 34
36#if EMU_PLATFORM == PLATFORM_LINUX
37#include <sys/time.h>
38#include <unistd.h>
39#endif
40
41#if 0
42#if 0
43#define DIFF_STATE 1
44#define __FOLLOW_MODE__ 0
45#else
46#define DIFF_STATE 0
47#define __FOLLOW_MODE__ 1
48#endif
49#endif
50
51#ifndef FALSE 35#ifndef FALSE
52#define FALSE 0 36#define FALSE 0
53#define TRUE 1 37#define TRUE 1
@@ -58,13 +42,6 @@
58#define LOWHIGH 1 42#define LOWHIGH 1
59#define HIGHLOW 2 43#define HIGHLOW 2
60 44
61//#define DBCT_TEST_SPEED
62#define DBCT_TEST_SPEED_SEC 10
63
64#define ARM_BYTE_TYPE 0
65#define ARM_HALFWORD_TYPE 1
66#define ARM_WORD_TYPE 2
67
68//the define of cachetype 45//the define of cachetype
69#define NONCACHE 0 46#define NONCACHE 0
70#define DATACACHE 1 47#define DATACACHE 1
@@ -73,18 +50,11 @@
73#define POS(i) ( (~(i)) >> 31 ) 50#define POS(i) ( (~(i)) >> 31 )
74#define NEG(i) ( (i) >> 31 ) 51#define NEG(i) ( (i) >> 31 )
75 52
76#ifndef __STDC__
77typedef char *VoidStar;
78#endif
79
80typedef u64 ARMdword; // must be 64 bits wide 53typedef u64 ARMdword; // must be 64 bits wide
81typedef u32 ARMword; // must be 32 bits wide 54typedef u32 ARMword; // must be 32 bits wide
82typedef u16 ARMhword; // must be 16 bits wide 55typedef u16 ARMhword; // must be 16 bits wide
83typedef u8 ARMbyte; // must be 8 bits wide 56typedef u8 ARMbyte; // must be 8 bits wide
84typedef struct ARMul_State ARMul_State; 57typedef struct ARMul_State ARMul_State;
85typedef struct ARMul_io ARMul_io;
86typedef struct ARMul_Energy ARMul_Energy;
87
88 58
89typedef unsigned ARMul_CPInits(ARMul_State* state); 59typedef unsigned ARMul_CPInits(ARMul_State* state);
90typedef unsigned ARMul_CPExits(ARMul_State* state); 60typedef unsigned ARMul_CPExits(ARMul_State* state);
@@ -98,65 +68,6 @@ typedef unsigned ARMul_CDPs(ARMul_State* state, unsigned type, ARMword instr);
98typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value); 68typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value);
99typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value); 69typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value);
100 70
101
102//added by ksh,2004-3-5
103struct ARMul_io
104{
105 ARMword *instr; // to display the current interrupt state
106 ARMword *net_flag; // to judge if network is enabled
107 ARMword *net_int; // netcard interrupt
108
109 //ywc,2004-04-01
110 ARMword *ts_int;
111 ARMword *ts_is_enable;
112 ARMword *ts_addr_begin;
113 ARMword *ts_addr_end;
114 ARMword *ts_buffer;
115};
116
117/* added by ksh,2004-11-26,some energy profiling */
118struct ARMul_Energy
119{
120 int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
121 int enable_func_energy; /* <tktan> BUG200105181702 */
122 char *func_energy;
123 int func_display; /* <tktan> BUG200103311509 : for function call display */
124 int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
125 char *start_func; /* <tktan> BUG200104191428 */
126
127 FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
128 long long tcycle, pcycle;
129 float t_energy;
130 void *cur_task; /* <tktan> BUG200103291737 */
131 long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
132 long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
133 long long p_io_update_tcycle;
134 /*record CCCR,to get current core frequency */
135 ARMword cccr;
136};
137#if 0
138#define MAX_BANK 8
139#define MAX_STR 1024
140
141typedef struct mem_bank
142{
143 ARMword (*read_byte) (ARMul_State* state, ARMword addr);
144 void (*write_byte) (ARMul_State* state, ARMword addr, ARMword data);
145 ARMword (*read_halfword) (ARMul_State* state, ARMword addr);
146 void (*write_halfword) (ARMul_State* state, ARMword addr, ARMword data);
147 ARMword (*read_word) (ARMul_State* state, ARMword addr);
148 void (*write_word) (ARMul_State* state, ARMword addr, ARMword data);
149 unsigned int addr, len;
150 char filename[MAX_STR];
151 unsigned type; //chy 2003-09-21: maybe io,ram,rom
152} mem_bank_t;
153typedef struct
154{
155 int bank_num;
156 int current_num; /*current num of bank */
157 mem_bank_t mem_banks[MAX_BANK];
158} mem_config_t;
159#endif
160#define VFP_REG_NUM 64 71#define VFP_REG_NUM 64
161struct ARMul_State 72struct ARMul_State
162{ 73{
@@ -196,9 +107,8 @@ struct ARMul_State
196 ARMdword Accumulator; 107 ARMdword Accumulator;
197 108
198 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ 109 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
199 unsigned long long int icounter, debug_icounter, kernel_icounter; 110 unsigned long long int icounter, debug_icounter, kernel_icounter;
200 unsigned int shifter_carry_out; 111 unsigned int shifter_carry_out;
201 //ARMword translate_pc;
202 112
203 /* add armv6 flags dyf:2010-08-09 */ 113 /* add armv6 flags dyf:2010-08-09 */
204 ARMword GEFlag, EFlag, AFlag, QFlag; 114 ARMword GEFlag, EFlag, AFlag, QFlag;
@@ -226,9 +136,6 @@ struct ARMul_State
226 unsigned CanWatch; /* set by memory interface if its willing to suffer the 136 unsigned CanWatch; /* set by memory interface if its willing to suffer the
227 overhead of checking for watchpoints on each memory 137 overhead of checking for watchpoints on each memory
228 access */ 138 access */
229 unsigned int StopHandle;
230
231 char *CommandLine; /* Command Line from ARMsd */
232 139
233 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ 140 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
234 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ 141 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
@@ -244,10 +151,6 @@ struct ARMul_State
244 unsigned char *CPData[16]; /* Coprocessor data */ 151 unsigned char *CPData[16]; /* Coprocessor data */
245 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ 152 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
246 153
247 unsigned EventSet; /* the number of events in the queue */
248 unsigned int Now; /* time to the nearest cycle */
249 struct EventNode **EventPtr; /* the event list */
250
251 unsigned Debug; /* show instructions as they are executed */ 154 unsigned Debug; /* show instructions as they are executed */
252 unsigned NresetSig; /* reset the processor */ 155 unsigned NresetSig; /* reset the processor */
253 unsigned NfiqSig; 156 unsigned NfiqSig;
@@ -300,17 +203,9 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
300 ARMword Base; /* extra hand for base writeback */ 203 ARMword Base; /* extra hand for base writeback */
301 ARMword AbortAddr; /* to keep track of Prefetch aborts */ 204 ARMword AbortAddr; /* to keep track of Prefetch aborts */
302 205
303 const struct Dbg_HostosInterface *hostif;
304
305 int verbose; /* non-zero means print various messages like the banner */ 206 int verbose; /* non-zero means print various messages like the banner */
306 207
307 int mmu_inited; 208 int mmu_inited;
308 //mem_state_t mem;
309 /*remove io_state to skyeye_mach_*.c files */
310 //io_state_t io;
311 /* point to a interrupt pending register. now for skyeye-ne2k.c
312 * later should move somewhere. e.g machine_config_t*/
313
314 209
315 //chy: 2003-08-11, for different arm core type 210 //chy: 2003-08-11, for different arm core type
316 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ 211 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
@@ -321,44 +216,17 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
321 unsigned is_XScale; /* Are we emulating an XScale architecture ? */ 216 unsigned is_XScale; /* Are we emulating an XScale architecture ? */
322 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ 217 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
323 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ 218 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
324 //chy 2005-09-19
325 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */ 219 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
220
326 //chy: seems only used in xscale's CP14 221 //chy: seems only used in xscale's CP14
327 unsigned int LastTime; /* Value of last call to ARMul_Time() */
328 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */ 222 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
329 223
330
331 //added by ksh:for handle different machs io 2004-3-5
332 ARMul_io mach_io;
333
334 /*added by ksh,2004-11-26,some energy profiling*/
335 ARMul_Energy energy;
336
337 //teawater add for next_dis 2004.10.27-----------------------
338 int disassemble;
339
340
341 //teawater add for arm2x86 2005.02.15-------------------------------------------
342 u32 trap;
343 u32 tea_break_addr;
344 u32 tea_break_ok;
345 int tea_pc;
346
347 //teawater add for arm2x86 2005.07.05------------------------------------------- 224 //teawater add for arm2x86 2005.07.05-------------------------------------------
348 //arm_arm A2-18 225 //arm_arm A2-18
349 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model 226 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
350
351 //teawater change for return if running tb dirty 2005.07.09---------------------
352 void *tb_now;
353
354
355 //teawater add for record reg value to ./reg.txt 2005.07.10---------------------
356 FILE *tea_reg_fd;
357
358 227
359 /*added by ksh in 2005-10-1*/ 228 /*added by ksh in 2005-10-1*/
360 cpu_config_t *cpu; 229 cpu_config_t *cpu;
361 //mem_config_t *mem_bank;
362 230
363 /* added LPC remap function */ 231 /* added LPC remap function */
364 int vector_remap_flag; 232 int vector_remap_flag;
@@ -367,23 +235,12 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
367 235
368 u32 step; 236 u32 step;
369 u32 cycle; 237 u32 cycle;
370 int stop_simulator; 238
371 conf_object_t *dyncom_cpu;
372//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
373#ifdef DBCT_TEST_SPEED
374 uint64_t instr_count;
375#endif //DBCT_TEST_SPEED
376// FILE * state_log;
377//diff log
378//#if DIFF_STATE
379 FILE * state_log;
380//#endif
381 /* monitored memory for exclusice access */ 239 /* monitored memory for exclusice access */
382 ARMword exclusive_tag_array[128]; 240 ARMword exclusive_tag_array[128];
383 /* 1 means exclusive access and 0 means open access */ 241 /* 1 means exclusive access and 0 means open access */
384 ARMword exclusive_access_state; 242 ARMword exclusive_access_state;
385 243
386 memory_space_intf space;
387 u32 CurrInstr; 244 u32 CurrInstr;
388 u32 last_pc; /* the last pc executed */ 245 u32 last_pc; /* the last pc executed */
389 u32 last_instr; /* the last inst executed */ 246 u32 last_instr; /* the last inst executed */
@@ -392,7 +249,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
392 u32 WritePc[17]; 249 u32 WritePc[17];
393 u32 CurrWrite; 250 u32 CurrWrite;
394}; 251};
395#define DIFF_WRITE 0
396 252
397typedef ARMul_State arm_core_t; 253typedef ARMul_State arm_core_t;
398 254
@@ -519,13 +375,6 @@ extern void ARMul_Reset(ARMul_State* state);
519extern ARMul_State *ARMul_NewState(ARMul_State* state); 375extern ARMul_State *ARMul_NewState(ARMul_State* state);
520extern ARMword ARMul_DoProg(ARMul_State* state); 376extern ARMword ARMul_DoProg(ARMul_State* state);
521extern ARMword ARMul_DoInstr(ARMul_State* state); 377extern ARMword ARMul_DoInstr(ARMul_State* state);
522/***************************************************************************\
523* Definitons of things for event handling *
524\***************************************************************************/
525
526extern void ARMul_ScheduleEvent(ARMul_State* state, unsigned int delay, unsigned(*func) ());
527extern void ARMul_EnvokeEvent(ARMul_State* state);
528extern unsigned int ARMul_Time(ARMul_State* state);
529 378
530/***************************************************************************\ 379/***************************************************************************\
531* Useful support routines * 380* Useful support routines *
@@ -724,56 +573,12 @@ enum ConditionCode {
724#define IFFLAGS state->IFFlags 573#define IFFLAGS state->IFFlags
725#endif //VFLAG 574#endif //VFLAG
726 575
727#define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\
728 state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \
729 state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
730 state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
731 state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
732 state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
733 state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
734 state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
735 state->temp,state->loaded,state->decoded);}
736
737#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
738RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
739RF %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
740RI %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
741RS %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
742RA %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
743RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
744 state->RegBank[0][0],state->RegBank[0][1],state->RegBank[0][2],state->RegBank[0][3], \
745 state->RegBank[0][4],state->RegBank[0][5],state->RegBank[0][6],state->RegBank[0][7], \
746 state->RegBank[0][8],state->RegBank[0][9],state->RegBank[0][10],state->RegBank[0][11], \
747 state->RegBank[0][12],state->RegBank[0][13],state->RegBank[0][14],state->RegBank[0][15], \
748 state->RegBank[1][0],state->RegBank[1][1],state->RegBank[1][2],state->RegBank[1][3], \
749 state->RegBank[1][4],state->RegBank[1][5],state->RegBank[1][6],state->RegBank[1][7], \
750 state->RegBank[1][8],state->RegBank[1][9],state->RegBank[1][10],state->RegBank[1][11], \
751 state->RegBank[1][12],state->RegBank[1][13],state->RegBank[1][14],state->RegBank[1][15], \
752 state->RegBank[2][0],state->RegBank[2][1],state->RegBank[2][2],state->RegBank[2][3], \
753 state->RegBank[2][4],state->RegBank[2][5],state->RegBank[2][6],state->RegBank[2][7], \
754 state->RegBank[2][8],state->RegBank[2][9],state->RegBank[2][10],state->RegBank[2][11], \
755 state->RegBank[2][12],state->RegBank[2][13],state->RegBank[2][14],state->RegBank[2][15], \
756 state->RegBank[3][0],state->RegBank[3][1],state->RegBank[3][2],state->RegBank[3][3], \
757 state->RegBank[3][4],state->RegBank[3][5],state->RegBank[3][6],state->RegBank[3][7], \
758 state->RegBank[3][8],state->RegBank[3][9],state->RegBank[3][10],state->RegBank[3][11], \
759 state->RegBank[3][12],state->RegBank[3][13],state->RegBank[3][14],state->RegBank[3][15], \
760 state->RegBank[4][0],state->RegBank[4][1],state->RegBank[4][2],state->RegBank[4][3], \
761 state->RegBank[4][4],state->RegBank[4][5],state->RegBank[4][6],state->RegBank[4][7], \
762 state->RegBank[4][8],state->RegBank[4][9],state->RegBank[4][10],state->RegBank[4][11], \
763 state->RegBank[4][12],state->RegBank[4][13],state->RegBank[4][14],state->RegBank[4][15], \
764 state->RegBank[5][0],state->RegBank[5][1],state->RegBank[5][2],state->RegBank[5][3], \
765 state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
766 state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
767 state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
768 );}
769
770extern bool AddOverflow(ARMword, ARMword, ARMword); 576extern bool AddOverflow(ARMword, ARMword, ARMword);
771extern bool SubOverflow(ARMword, ARMword, ARMword); 577extern bool SubOverflow(ARMword, ARMword, ARMword);
772 578
773extern void ARMul_UndefInstr(ARMul_State*, ARMword); 579extern void ARMul_UndefInstr(ARMul_State*, ARMword);
774extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword); 580extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword);
775extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword); 581extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword);
776extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
777extern void ARMul_SelectProcessor(ARMul_State*, unsigned); 582extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
778 583
779extern u32 AddWithCarry(u32, u32, u32, bool*, bool*); 584extern u32 AddWithCarry(u32, u32, u32, bool*, bool*);
@@ -791,8 +596,3 @@ extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
791extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8); 596extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
792extern u32 ARMul_SignedSatQ(s32, u8, bool*); 597extern u32 ARMul_SignedSatQ(s32, u8, bool*);
793extern u32 ARMul_UnsignedSatQ(s32, u8, bool*); 598extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
794
795#define DIFF_LOG 0
796#define SAVE_LOG 0
797
798#endif /* _ARMDEFS_H_ */
diff --git a/src/core/arm/skyeye_common/armemu.h b/src/core/arm/skyeye_common/armemu.h
index 1dfcc635a..686b2a3f6 100644
--- a/src/core/arm/skyeye_common/armemu.h
+++ b/src/core/arm/skyeye_common/armemu.h
@@ -575,8 +575,6 @@ extern ARMword ARMul_GetPC (ARMul_State *);
575extern ARMword ARMul_GetNextPC (ARMul_State *); 575extern ARMword ARMul_GetNextPC (ARMul_State *);
576extern ARMword ARMul_GetR15 (ARMul_State *); 576extern ARMword ARMul_GetR15 (ARMul_State *);
577extern ARMword ARMul_GetCPSR (ARMul_State *); 577extern ARMword ARMul_GetCPSR (ARMul_State *);
578extern void ARMul_EnvokeEvent (ARMul_State *);
579extern unsigned int ARMul_Time (ARMul_State *);
580extern void ARMul_NegZero (ARMul_State *, ARMword); 578extern void ARMul_NegZero (ARMul_State *, ARMword);
581extern void ARMul_SetPC (ARMul_State *, ARMword); 579extern void ARMul_SetPC (ARMul_State *, ARMword);
582extern void ARMul_SetR15 (ARMul_State *, ARMword); 580extern void ARMul_SetR15 (ARMul_State *, ARMword);
@@ -603,8 +601,7 @@ extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
603extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); 601extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
604extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); 602extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
605extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); 603extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
606extern void ARMul_ScheduleEvent (ARMul_State *, unsigned int, 604
607 unsigned (*)(ARMul_State *));
608/* Coprocessor support functions. */ 605/* Coprocessor support functions. */
609extern unsigned ARMul_CoProInit (ARMul_State *); 606extern unsigned ARMul_CoProInit (ARMul_State *);
610extern void ARMul_CoProExit (ARMul_State *); 607extern void ARMul_CoProExit (ARMul_State *);
diff --git a/src/core/arm/skyeye_common/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
index d4088383f..6648e9d66 100644
--- a/src/core/arm/skyeye_common/skyeye_defs.h
+++ b/src/core/arm/skyeye_common/skyeye_defs.h
@@ -1,5 +1,4 @@
1#ifndef CORE_ARM_SKYEYE_DEFS_H_ 1#pragma once
2#define CORE_ARM_SKYEYE_DEFS_H_
3 2
4#include "common/common.h" 3#include "common/common.h"
5 4
@@ -8,21 +7,15 @@
8 7
9typedef struct 8typedef struct
10{ 9{
11 const char *cpu_arch_name; /*cpu architecture version name.e.g. armv4t */ 10 const char *cpu_arch_name; /* CPU architecture version name.e.g. armv4t */
12 const char *cpu_name; /*cpu name. e.g. arm7tdmi or arm720t */ 11 const char *cpu_name; /* CPU name. e.g. arm7tdmi or arm720t */
13 u32 cpu_val; /*CPU value; also call MMU ID or processor id;see 12 u32 cpu_val; /*CPU value; also call MMU ID or processor id;see
14 ARM Architecture Reference Manual B2-6 */ 13 ARM Architecture Reference Manual B2-6 */
15 u32 cpu_mask; /*cpu_val's mask. */ 14 u32 cpu_mask; /* cpu_val's mask. */
16 u32 cachetype; /*this cpu has what kind of cache */ 15 u32 cachetype; /* this CPU has what kind of cache */
17} cpu_config_t; 16} cpu_config_t;
18 17
19typedef struct conf_object_s{ 18typedef enum {
20 char* objname;
21 void* obj;
22 char* class_name;
23}conf_object_t;
24
25typedef enum{
26 /* No exception */ 19 /* No exception */
27 No_exp = 0, 20 No_exp = 0,
28 /* Memory allocation exception */ 21 /* Memory allocation exception */
@@ -44,70 +37,21 @@ typedef enum{
44 37
45 /* Unknown exception */ 38 /* Unknown exception */
46 Unknown_exp 39 Unknown_exp
47}exception_t; 40} exception_t;
48 41
49typedef enum { 42typedef enum {
50 Align = 0, 43 Align = 0,
51 UnAlign 44 UnAlign
52}align_t; 45} align_t;
53 46
54typedef enum { 47typedef enum {
55 Little_endian = 0, 48 Little_endian = 0,
56 Big_endian 49 Big_endian
57}endian_t; 50} endian_t;
58//typedef int exception_t;
59 51
60typedef enum{ 52typedef enum {
61 Phys_addr = 0, 53 Phys_addr = 0,
62 Virt_addr 54 Virt_addr
63}addr_type_t; 55} addr_type_t;
64
65typedef exception_t(*read_byte_t)(conf_object_t* target, u32 addr, void *buf, size_t count);
66typedef exception_t(*write_byte_t)(conf_object_t* target, u32 addr, const void *buf, size_t count);
67
68typedef struct memory_space{
69 conf_object_t* conf_obj;
70 read_byte_t read;
71 write_byte_t write;
72}memory_space_intf;
73
74
75/*
76 * a running instance for a specific archteciture.
77 */
78typedef struct generic_arch_s
79{
80 char* arch_name;
81 void (*init) (void);
82 void (*reset) (void);
83 void (*step_once) (void);
84 void (*set_pc)(u32 addr);
85 u32 (*get_pc)(void);
86 u32 (*get_step)(void);
87 //chy 2004-04-15
88 //int (*ICE_write_byte) (u32 addr, uint8_t v);
89 //int (*ICE_read_byte)(u32 addr, uint8_t *pv);
90 u32 (*get_regval_by_id)(int id);
91 u32 (*get_regnum)(void);
92 char* (*get_regname_by_id)(int id);
93 exception_t (*set_regval_by_id)(int id, u32 value);
94 /*
95 * read a data by virtual address.
96 */
97 exception_t (*mmu_read)(short size, u32 addr, u32 * value);
98 /*
99 * write a data by a virtual address.
100 */
101 exception_t (*mmu_write)(short size, u32 addr, u32 value);
102 /**
103 * get a signal from external
104 */
105 //exception_t (*signal)(interrupt_signal_t* signal);
106
107 endian_t endianess;
108 align_t alignment;
109} generic_arch_t;
110 56
111typedef u32 addr_t; 57typedef u32 addr_t;
112
113#endif