summaryrefslogtreecommitdiff
path: root/src/core/arm/interpreter
diff options
context:
space:
mode:
authorGravatar bunnei2014-12-23 09:44:04 -0500
committerGravatar bunnei2014-12-23 09:44:04 -0500
commitd31a94f06b5d595e6dceafdd6a76a76455dd5ed6 (patch)
tree5cfa9b22a9577c166b54e95a32046dff6dc5bbeb /src/core/arm/interpreter
parentMerge pull request #335 from lioncash/cpsrcreate (diff)
parentarmemu: Fix retrieval of the CPSR in MRS instructions. (diff)
downloadyuzu-d31a94f06b5d595e6dceafdd6a76a76455dd5ed6.tar.gz
yuzu-d31a94f06b5d595e6dceafdd6a76a76455dd5ed6.tar.xz
yuzu-d31a94f06b5d595e6dceafdd6a76a76455dd5ed6.zip
Merge pull request #334 from lioncash/cpsr
armemu: Fix retrieval of the CPSR in MRS instructions.
Diffstat (limited to 'src/core/arm/interpreter')
-rw-r--r--src/core/arm/interpreter/armemu.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index e69789142..578d71380 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -1724,7 +1724,7 @@ mainswitch:
1724 TAKEABORT; 1724 TAKEABORT;
1725 } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */ 1725 } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */
1726 UNDEF_MRSPC; 1726 UNDEF_MRSPC;
1727 DEST = ECC | EINT | EMODE; 1727 DEST = ARMul_GetCPSR(state);
1728 } else { 1728 } else {
1729 UNDEF_Test; 1729 UNDEF_Test;
1730 } 1730 }