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authorGravatar bunnei2014-05-26 20:52:00 -0400
committerGravatar bunnei2014-05-26 20:52:00 -0400
commit6448c2f30062c085330ff26a4812c9a91c7b492c (patch)
tree386e32cf3ec053491fb8dfd8459a1c92553241d9 /src/core/arm/interpreter
parentMerge pull request #4 from archshift/patch-1 (diff)
parentservice: fixed typo that MSVC did not catch as an error (diff)
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Merge pull request #9 from bunnei/master
Add initial kernel HLE, includes thread creation and context switching
Diffstat (limited to 'src/core/arm/interpreter')
-rw-r--r--src/core/arm/interpreter/arm_interpreter.cpp91
-rw-r--r--src/core/arm/interpreter/arm_interpreter.h20
-rw-r--r--src/core/arm/interpreter/armdefs.h4
-rw-r--r--src/core/arm/interpreter/armemu.cpp5
-rw-r--r--src/core/arm/interpreter/arminit.cpp3
-rw-r--r--src/core/arm/interpreter/vfp/vfp.h2
6 files changed, 94 insertions, 31 deletions
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 23d96d292..17f787b86 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -9,30 +9,30 @@ const static cpu_config_t s_arm11_cpu_info = {
9}; 9};
10 10
11ARM_Interpreter::ARM_Interpreter() { 11ARM_Interpreter::ARM_Interpreter() {
12 m_state = new ARMul_State; 12 state = new ARMul_State;
13 13
14 ARMul_EmulateInit(); 14 ARMul_EmulateInit();
15 ARMul_NewState(m_state); 15 ARMul_NewState(state);
16 16
17 m_state->abort_model = 0; 17 state->abort_model = 0;
18 m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info; 18 state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
19 m_state->bigendSig = LOW; 19 state->bigendSig = LOW;
20 20
21 ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); 21 ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
22 m_state->lateabtSig = LOW; 22 state->lateabtSig = LOW;
23 mmu_init(m_state); 23 mmu_init(state);
24 24
25 // Reset the core to initial state 25 // Reset the core to initial state
26 ARMul_Reset(m_state); 26 ARMul_Reset(state);
27 m_state->NextInstr = 0; 27 state->NextInstr = 0;
28 m_state->Emulate = 3; 28 state->Emulate = 3;
29 29
30 m_state->pc = m_state->Reg[15] = 0x00000000; 30 state->pc = state->Reg[15] = 0x00000000;
31 m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack 31 state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
32} 32}
33 33
34ARM_Interpreter::~ARM_Interpreter() { 34ARM_Interpreter::~ARM_Interpreter() {
35 delete m_state; 35 delete state;
36} 36}
37 37
38/** 38/**
@@ -40,7 +40,7 @@ ARM_Interpreter::~ARM_Interpreter() {
40 * @param addr Address to set PC to 40 * @param addr Address to set PC to
41 */ 41 */
42void ARM_Interpreter::SetPC(u32 pc) { 42void ARM_Interpreter::SetPC(u32 pc) {
43 m_state->pc = m_state->Reg[15] = pc; 43 state->pc = state->Reg[15] = pc;
44} 44}
45 45
46/* 46/*
@@ -48,7 +48,7 @@ void ARM_Interpreter::SetPC(u32 pc) {
48 * @return Returns current PC 48 * @return Returns current PC
49 */ 49 */
50u32 ARM_Interpreter::GetPC() const { 50u32 ARM_Interpreter::GetPC() const {
51 return m_state->pc; 51 return state->pc;
52} 52}
53 53
54/** 54/**
@@ -57,7 +57,7 @@ u32 ARM_Interpreter::GetPC() const {
57 * @return Returns the value in the register 57 * @return Returns the value in the register
58 */ 58 */
59u32 ARM_Interpreter::GetReg(int index) const { 59u32 ARM_Interpreter::GetReg(int index) const {
60 return m_state->Reg[index]; 60 return state->Reg[index];
61} 61}
62 62
63/** 63/**
@@ -66,7 +66,7 @@ u32 ARM_Interpreter::GetReg(int index) const {
66 * @param value Value to set register to 66 * @param value Value to set register to
67 */ 67 */
68void ARM_Interpreter::SetReg(int index, u32 value) { 68void ARM_Interpreter::SetReg(int index, u32 value) {
69 m_state->Reg[index] = value; 69 state->Reg[index] = value;
70} 70}
71 71
72/** 72/**
@@ -74,7 +74,15 @@ void ARM_Interpreter::SetReg(int index, u32 value) {
74 * @return Returns the value of the CPSR register 74 * @return Returns the value of the CPSR register
75 */ 75 */
76u32 ARM_Interpreter::GetCPSR() const { 76u32 ARM_Interpreter::GetCPSR() const {
77 return m_state->Cpsr; 77 return state->Cpsr;
78}
79
80/**
81 * Set the current CPSR register
82 * @param cpsr Value to set CPSR to
83 */
84void ARM_Interpreter::SetCPSR(u32 cpsr) {
85 state->Cpsr = cpsr;
78} 86}
79 87
80/** 88/**
@@ -82,7 +90,7 @@ u32 ARM_Interpreter::GetCPSR() const {
82 * @return Returns number of clock ticks 90 * @return Returns number of clock ticks
83 */ 91 */
84u64 ARM_Interpreter::GetTicks() const { 92u64 ARM_Interpreter::GetTicks() const {
85 return ARMul_Time(m_state); 93 return ARMul_Time(state);
86} 94}
87 95
88/** 96/**
@@ -90,6 +98,45 @@ u64 ARM_Interpreter::GetTicks() const {
90 * @param num_instructions Number of instructions to executes 98 * @param num_instructions Number of instructions to executes
91 */ 99 */
92void ARM_Interpreter::ExecuteInstructions(int num_instructions) { 100void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
93 m_state->NumInstrsToExecute = num_instructions; 101 state->NumInstrsToExecute = num_instructions;
94 ARMul_Emulate32(m_state); 102 ARMul_Emulate32(state);
103}
104
105/**
106 * Saves the current CPU context
107 * @param ctx Thread context to save
108 * @todo Do we need to save Reg[15] and NextInstr?
109 */
110void ARM_Interpreter::SaveContext(ThreadContext& ctx) {
111 memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
112 memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
113
114 ctx.sp = state->Reg[13];
115 ctx.lr = state->Reg[14];
116 ctx.pc = state->pc;
117 ctx.cpsr = state->Cpsr;
118
119 ctx.fpscr = state->VFP[1];
120 ctx.fpexc = state->VFP[2];
121}
122
123/**
124 * Loads a CPU context
125 * @param ctx Thread context to load
126 * @param Do we need to load Reg[15] and NextInstr?
127 */
128void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
129 memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
130 memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
131
132 state->Reg[13] = ctx.sp;
133 state->Reg[14] = ctx.lr;
134 state->pc = ctx.pc;
135 state->Cpsr = ctx.cpsr;
136
137 state->VFP[1] = ctx.fpscr;
138 state->VFP[2] = ctx.fpexc;
139
140 state->Reg[15] = ctx.pc;
141 state->NextInstr = RESUME;
95} 142}
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 509025080..6a531e497 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -49,11 +49,29 @@ public:
49 u32 GetCPSR() const; 49 u32 GetCPSR() const;
50 50
51 /** 51 /**
52 * Set the current CPSR register
53 * @param cpsr Value to set CPSR to
54 */
55 void SetCPSR(u32 cpsr);
56
57 /**
52 * Returns the number of clock ticks since the last reset 58 * Returns the number of clock ticks since the last reset
53 * @return Returns number of clock ticks 59 * @return Returns number of clock ticks
54 */ 60 */
55 u64 GetTicks() const; 61 u64 GetTicks() const;
56 62
63 /**
64 * Saves the current CPU context
65 * @param ctx Thread context to save
66 */
67 void SaveContext(ThreadContext& ctx);
68
69 /**
70 * Loads a CPU context
71 * @param ctx Thread context to load
72 */
73 void LoadContext(const ThreadContext& ctx);
74
57protected: 75protected:
58 76
59 /** 77 /**
@@ -64,6 +82,6 @@ protected:
64 82
65private: 83private:
66 84
67 ARMul_State* m_state; 85 ARMul_State* state;
68 86
69}; 87};
diff --git a/src/core/arm/interpreter/armdefs.h b/src/core/arm/interpreter/armdefs.h
index 5b2abc7f7..d8eae4d3f 100644
--- a/src/core/arm/interpreter/armdefs.h
+++ b/src/core/arm/interpreter/armdefs.h
@@ -24,10 +24,6 @@
24 24
25#include "common/platform.h" 25#include "common/platform.h"
26 26
27#if EMU_PLATFORM == PLATFORM_WINDOWS
28#include <windows.h>
29#endif
30
31//teawater add for arm2x86 2005.02.14------------------------------------------- 27//teawater add for arm2x86 2005.02.14-------------------------------------------
32// koodailar remove it for mingw 2005.12.18---------------- 28// koodailar remove it for mingw 2005.12.18----------------
33//anthonylee modify it for portable 2007.01.30 29//anthonylee modify it for portable 2007.01.30
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 32e315f4b..e5dc7bd44 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -4478,8 +4478,7 @@ ARMul_Emulate26 (ARMul_State * state)
4478 isize) & 4478 isize) &
4479 R15PCBITS)); 4479 R15PCBITS));
4480#endif 4480#endif
4481 } 4481 } else if (instr != 0xDEADC0DE) // thumbemu uses 0xDEADCODE for debugging to catch non updates
4482 else
4483 ARMul_MCR (state, instr, 4482 ARMul_MCR (state, instr,
4484 DEST); 4483 DEST);
4485 } 4484 }
@@ -4549,7 +4548,7 @@ ARMul_Emulate26 (ARMul_State * state)
4549 // ARMul_OSHandleSWI (state, BITS (0, 23)); 4548 // ARMul_OSHandleSWI (state, BITS (0, 23));
4550 // break; 4549 // break;
4551 //} 4550 //}
4552 HLE::CallSyscall(instr); 4551 HLE::CallSVC(instr);
4553 ARMul_Abort (state, ARMul_SWIV); 4552 ARMul_Abort (state, ARMul_SWIV);
4554 break; 4553 break;
4555 } 4554 }
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 2c771cdda..e05667bea 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -17,8 +17,11 @@
17 17
18 18
19#include "common/platform.h" 19#include "common/platform.h"
20
20#if EMU_PLATFORM == PLATFORM_LINUX 21#if EMU_PLATFORM == PLATFORM_LINUX
21#include <unistd.h> 22#include <unistd.h>
23#elif EMU_PLATFORM == PLATFORM_WINDOWS
24#include <windows.h>
22#endif 25#endif
23 26
24#include <math.h> 27#include <math.h>
diff --git a/src/core/arm/interpreter/vfp/vfp.h b/src/core/arm/interpreter/vfp/vfp.h
index f738a615b..bbf4caeb0 100644
--- a/src/core/arm/interpreter/vfp/vfp.h
+++ b/src/core/arm/interpreter/vfp/vfp.h
@@ -21,7 +21,7 @@
21#ifndef __VFP_H__ 21#ifndef __VFP_H__
22#define __VFP_H__ 22#define __VFP_H__
23 23
24#define DBG(...) DEBUG_LOG(ARM11, __VA_ARGS__) 24#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__)
25 25
26#define vfpdebug //printf 26#define vfpdebug //printf
27 27