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authorGravatar bunnei2015-04-02 20:21:11 -0400
committerGravatar bunnei2015-04-02 20:21:11 -0400
commite25ffaba86c5b5a79256faf80c39f7e37343701d (patch)
treee65dfe42e08d9cb1fab735c8a62ec414fabee31e /src/core/arm/interpreter/armsupp.cpp
parentMerge pull request #678 from lioncash/disasm (diff)
parentdyncom: Move CP15 register writing into its own function. (diff)
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Merge pull request #677 from lioncash/cp15
dyncom: Isolate CP15 register reading and writing
Diffstat (limited to 'src/core/arm/interpreter/armsupp.cpp')
-rw-r--r--src/core/arm/interpreter/armsupp.cpp431
1 files changed, 431 insertions, 0 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index aca2bfbbd..6a11a5804 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -15,7 +15,9 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#include "core/mem_map.h"
18#include "core/arm/skyeye_common/armdefs.h" 19#include "core/arm/skyeye_common/armdefs.h"
20#include "core/arm/skyeye_common/arm_regformat.h"
19 21
20// Unsigned sum of absolute difference 22// Unsigned sum of absolute difference
21u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) 23u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
@@ -207,3 +209,432 @@ bool InBigEndianMode(ARMul_State* cpu)
207{ 209{
208 return (cpu->Cpsr & (1 << 9)) != 0; 210 return (cpu->Cpsr & (1 << 9)) != 0;
209} 211}
212
213// Whether or not the given CPU is in a mode other than user mode.
214bool InAPrivilegedMode(ARMul_State* cpu)
215{
216 return (cpu->Mode != USER32MODE);
217}
218
219// Reads from the CP15 registers. Used with implementation of the MRC instruction.
220// Note that since the 3DS does not have the hypervisor extensions, these registers
221// are not implemented.
222u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
223{
224 // Unprivileged registers
225 if (crn == 13 && opcode_1 == 0 && crm == 0)
226 {
227 if (opcode_2 == 2)
228 return cpu->CP15[CP15(CP15_THREAD_UPRW)];
229
230 // TODO: Whenever TLS is implemented, this should return
231 // "cpu->CP15[CP15(CP15_THREAD_URO)];"
232 // which contains the address of the 0x200-byte TLS
233 if (opcode_2 == 3)
234 return Memory::KERNEL_MEMORY_VADDR;
235 }
236
237 if (InAPrivilegedMode(cpu))
238 {
239 if (crn == 0 && opcode_1 == 0)
240 {
241 if (crm == 0)
242 {
243 if (opcode_2 == 0)
244 return cpu->CP15[CP15(CP15_MAIN_ID)];
245
246 if (opcode_2 == 1)
247 return cpu->CP15[CP15(CP15_CACHE_TYPE)];
248
249 if (opcode_2 == 3)
250 return cpu->CP15[CP15(CP15_TLB_TYPE)];
251
252 if (opcode_2 == 5)
253 return cpu->CP15[CP15(CP15_CPU_ID)];
254 }
255 else if (crm == 1)
256 {
257 if (opcode_2 == 0)
258 return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)];
259
260 if (opcode_2 == 1)
261 return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)];
262
263 if (opcode_2 == 2)
264 return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)];
265
266 if (opcode_2 == 4)
267 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)];
268
269 if (opcode_2 == 5)
270 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)];
271
272 if (opcode_2 == 6)
273 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)];
274
275 if (opcode_2 == 7)
276 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)];
277 }
278 else if (crm == 2)
279 {
280 if (opcode_2 == 0)
281 return cpu->CP15[CP15(CP15_ISA_FEATURE_0)];
282
283 if (opcode_2 == 1)
284 return cpu->CP15[CP15(CP15_ISA_FEATURE_1)];
285
286 if (opcode_2 == 2)
287 return cpu->CP15[CP15(CP15_ISA_FEATURE_2)];
288
289 if (opcode_2 == 3)
290 return cpu->CP15[CP15(CP15_ISA_FEATURE_3)];
291
292 if (opcode_2 == 4)
293 return cpu->CP15[CP15(CP15_ISA_FEATURE_4)];
294 }
295 }
296
297 if (crn == 1 && opcode_1 == 0 && crm == 0)
298 {
299 if (opcode_2 == 0)
300 return cpu->CP15[CP15(CP15_CONTROL)];
301
302 if (opcode_2 == 1)
303 return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
304
305 if (opcode_2 == 2)
306 return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
307 }
308
309 if (crn == 2 && opcode_1 == 0 && crm == 0)
310 {
311 if (opcode_2 == 0)
312 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
313
314 if (opcode_2 == 1)
315 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
316
317 if (opcode_2 == 2)
318 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
319 }
320
321 if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
322 return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
323
324 if (crn == 5 && opcode_1 == 0 && crm == 0)
325 {
326 if (opcode_2 == 0)
327 return cpu->CP15[CP15(CP15_FAULT_STATUS)];
328
329 if (opcode_2 == 1)
330 return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
331 }
332
333 if (crn == 6 && opcode_1 == 0 && crm == 0)
334 {
335 if (opcode_2 == 0)
336 return cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
337
338 if (opcode_2 == 1)
339 return cpu->CP15[CP15(CP15_WFAR)];
340 }
341
342 if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
343 return cpu->CP15[CP15(CP15_PHYS_ADDRESS)];
344
345 if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
346 return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)];
347
348 if (crn == 10 && opcode_1 == 0)
349 {
350 if (crm == 0 && opcode_2 == 0)
351 return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)];
352
353 if (crm == 2)
354 {
355 if (opcode_2 == 0)
356 return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)];
357
358 if (opcode_2 == 1)
359 return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)];
360 }
361 }
362
363 if (crn == 13 && crm == 0)
364 {
365 if (opcode_2 == 0)
366 return cpu->CP15[CP15(CP15_PID)];
367
368 if (opcode_2 == 1)
369 return cpu->CP15[CP15(CP15_CONTEXT_ID)];
370
371 if (opcode_2 == 4)
372 return cpu->CP15[CP15(CP15_THREAD_PRW)];
373 }
374
375 if (crn == 15)
376 {
377 if (opcode_1 == 0 && crm == 12)
378 {
379 if (opcode_2 == 0)
380 return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)];
381
382 if (opcode_2 == 1)
383 return cpu->CP15[CP15(CP15_CYCLE_COUNTER)];
384
385 if (opcode_2 == 2)
386 return cpu->CP15[CP15(CP15_COUNT_0)];
387
388 if (opcode_2 == 3)
389 return cpu->CP15[CP15(CP15_COUNT_1)];
390 }
391
392 if (opcode_1 == 5 && opcode_2 == 2)
393 {
394 if (crm == 5)
395 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)];
396
397 if (crm == 6)
398 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)];
399
400 if (crm == 7)
401 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)];
402 }
403
404 if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
405 return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)];
406 }
407 }
408
409 LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
410 return 0;
411}
412
413// Write to the CP15 registers. Used with implementation of the MCR instruction.
414// Note that since the 3DS does not have the hypervisor extensions, these registers
415// are not implemented.
416void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
417{
418 if (InAPrivilegedMode(cpu))
419 {
420 if (crn == 1 && opcode_1 == 0 && crm == 0)
421 {
422 if (opcode_2 == 0)
423 cpu->CP15[CP15(CP15_CONTROL)] = value;
424 else if (opcode_2 == 1)
425 cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = value;
426 else if (opcode_2 == 2)
427 cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = value;
428 }
429 else if (crn == 2 && opcode_1 == 0 && crm == 0)
430 {
431 if (opcode_2 == 0)
432 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = value;
433 else if (opcode_2 == 1)
434 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = value;
435 else if (opcode_2 == 2)
436 cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = value;
437 }
438 else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
439 {
440 cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = value;
441 }
442 else if (crn == 5 && opcode_1 == 0 && crm == 0)
443 {
444 if (opcode_2 == 0)
445 cpu->CP15[CP15(CP15_FAULT_STATUS)] = value;
446 else if (opcode_2 == 1)
447 cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = value;
448 }
449 else if (crn == 6 && opcode_1 == 0 && crm == 0)
450 {
451 if (opcode_2 == 0)
452 cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = value;
453 else if (opcode_2 == 1)
454 cpu->CP15[CP15(CP15_WFAR)] = value;
455 }
456 else if (crn == 7 && opcode_1 == 0)
457 {
458 LOG_WARNING(Core_ARM11, "Cache operations are not fully implemented.");
459
460 if (crm == 0 && opcode_2 == 4)
461 {
462 cpu->CP15[CP15(CP15_WAIT_FOR_INTERRUPT)] = value;
463 }
464 else if (crm == 4 && opcode_2 == 0)
465 {
466 // NOTE: Not entirely accurate. This should do permission checks.
467 cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = Memory::VirtualToPhysicalAddress(value);
468 }
469 else if (crm == 5)
470 {
471 if (opcode_2 == 0)
472 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE)] = value;
473 else if (opcode_2 == 1)
474 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_MVA)] = value;
475 else if (opcode_2 == 2)
476 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_INDEX)] = value;
477 else if (opcode_2 == 6)
478 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE)] = value;
479 else if (opcode_2 == 7)
480 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY)] = value;
481 }
482 else if (crm == 6)
483 {
484 if (opcode_2 == 0)
485 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE)] = value;
486 else if (opcode_2 == 1)
487 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
488 else if (opcode_2 == 2)
489 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
490 }
491 else if (crm == 7 && opcode_2 == 0)
492 {
493 cpu->CP15[CP15(CP15_INVALIDATE_DATA_AND_INSTR_CACHE)] = value;
494 }
495 else if (crm == 10)
496 {
497 if (opcode_2 == 0)
498 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE)] = value;
499 else if (opcode_2 == 1)
500 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_MVA)] = value;
501 else if (opcode_2 == 2)
502 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX)] = value;
503 }
504 else if (crm == 14)
505 {
506 if (opcode_2 == 0)
507 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE)] = value;
508 else if (opcode_2 == 1)
509 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
510 else if (opcode_2 == 2)
511 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
512 }
513 }
514 else if (crn == 8 && opcode_1 == 0)
515 {
516 LOG_WARNING(Core_ARM11, "TLB operations not fully implemented.");
517
518 if (crm == 5)
519 {
520 if (opcode_2 == 0)
521 cpu->CP15[CP15(CP15_INVALIDATE_ITLB)] = value;
522 else if (opcode_2 == 1)
523 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_SINGLE_ENTRY)] = value;
524 else if (opcode_2 == 2)
525 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH)] = value;
526 else if (opcode_2 == 3)
527 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_MVA)] = value;
528 }
529 else if (crm == 6)
530 {
531 if (opcode_2 == 0)
532 cpu->CP15[CP15(CP15_INVALIDATE_DTLB)] = value;
533 else if (opcode_2 == 1)
534 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_SINGLE_ENTRY)] = value;
535 else if (opcode_2 == 2)
536 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH)] = value;
537 else if (opcode_2 == 3)
538 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_MVA)] = value;
539 }
540 else if (crm == 7)
541 {
542 if (opcode_2 == 0)
543 cpu->CP15[CP15(CP15_INVALIDATE_UTLB)] = value;
544 else if (opcode_2 == 1)
545 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_SINGLE_ENTRY)] = value;
546 else if (opcode_2 == 2)
547 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH)] = value;
548 else if (opcode_2 == 3)
549 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_MVA)] = value;
550 }
551 }
552 else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
553 {
554 cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = value;
555 }
556 else if (crn == 10 && opcode_1 == 0)
557 {
558 if (crm == 0 && opcode_2 == 0)
559 {
560 cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = value;
561 }
562 else if (crm == 2)
563 {
564 if (opcode_2 == 0)
565 cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = value;
566 else if (opcode_2 == 1)
567 cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = value;
568 }
569 }
570 else if (crn == 13 && opcode_1 == 0 && crm == 0)
571 {
572 if (opcode_2 == 0)
573 cpu->CP15[CP15(CP15_PID)] = value;
574 else if (opcode_2 == 1)
575 cpu->CP15[CP15(CP15_CONTEXT_ID)] = value;
576 else if (opcode_2 == 3)
577 cpu->CP15[CP15(CP15_THREAD_URO)] = value;
578 else if (opcode_2 == 4)
579 cpu->CP15[CP15(CP15_THREAD_PRW)] = value;
580 }
581 else if (crn == 15)
582 {
583 if (opcode_1 == 0 && crm == 12)
584 {
585 if (opcode_2 == 0)
586 cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = value;
587 else if (opcode_2 == 1)
588 cpu->CP15[CP15(CP15_CYCLE_COUNTER)] = value;
589 else if (opcode_2 == 2)
590 cpu->CP15[CP15(CP15_COUNT_0)] = value;
591 else if (opcode_2 == 3)
592 cpu->CP15[CP15(CP15_COUNT_1)] = value;
593 }
594 else if (opcode_1 == 5)
595 {
596 if (crm == 4)
597 {
598 if (opcode_2 == 2)
599 cpu->CP15[CP15(CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
600 else if (opcode_2 == 4)
601 cpu->CP15[CP15(CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
602 }
603 else if (crm == 5 && opcode_2 == 2)
604 {
605 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = value;
606 }
607 else if (crm == 6 && opcode_2 == 2)
608 {
609 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = value;
610 }
611 else if (crm == 7 && opcode_2 == 2)
612 {
613 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = value;
614 }
615 }
616 else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
617 {
618 cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = value;
619 }
620 }
621 }
622
623 // Unprivileged registers
624 if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
625 {
626 cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value;
627 }
628 else if (crn == 7 && opcode_1 == 0 && crm == 10)
629 {
630 if (opcode_2 == 4)
631 cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value;
632 else if (opcode_2 == 5)
633 cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value;
634
635 }
636 else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
637 {
638 cpu->CP15[CP15(CP15_THREAD_UPRW)] = value;
639 }
640}
HIC SVNT DRACONES