diff options
| author |  Lioncash | 2014-12-22 22:10:47 -0500 |
|---|---|---|
| committer | Lioncash | 2014-12-22 23:51:59 -0500 |
| commit | 8e2accd9746d33116c6398e6f30db5b8b4e1f188 (patch) | |
| tree | c39bd43bf51a9eead458b8743e0cc925947edbd4 /src/core/arm/interpreter/armsupp.cpp | |
| parent | Merge pull request #322 from chinhodado/master (diff) | |
| download | yuzu-8e2accd9746d33116c6398e6f30db5b8b4e1f188.tar.gz yuzu-8e2accd9746d33116c6398e6f30db5b8b4e1f188.tar.xz yuzu-8e2accd9746d33116c6398e6f30db5b8b4e1f188.zip | |
armemu: Fix construction of the CPSR
Diffstat (limited to 'src/core/arm/interpreter/armsupp.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 30519f216..b31c0ea24 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp | |||
| @@ -227,8 +227,9 @@ ARMul_CPSRAltered (ARMul_State * state) | |||
| 227 | //state->Cpsr &= ~CBIT; | 227 | //state->Cpsr &= ~CBIT; |
| 228 | ASSIGNV ((state->Cpsr & VBIT) != 0); | 228 | ASSIGNV ((state->Cpsr & VBIT) != 0); |
| 229 | //state->Cpsr &= ~VBIT; | 229 | //state->Cpsr &= ~VBIT; |
| 230 | ASSIGNS ((state->Cpsr & SBIT) != 0); | 230 | ASSIGNQ ((state->Cpsr & QBIT) != 0); |
| 231 | //state->Cpsr &= ~SBIT; | 231 | //state->Cpsr &= ~QBIT; |
| 232 | state->GEFlag = (state->Cpsr & 0x000F0000); | ||
| 232 | #ifdef MODET | 233 | #ifdef MODET |
| 233 | ASSIGNT ((state->Cpsr & TBIT) != 0); | 234 | ASSIGNT ((state->Cpsr & TBIT) != 0); |
| 234 | //state->Cpsr &= ~TBIT; | 235 | //state->Cpsr &= ~TBIT; |