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| author | 2014-04-25 15:57:32 -0400 | |
|---|---|---|
| committer | 2014-04-25 15:57:32 -0400 | |
| commit | 6151e26958fa243b6322a9a544446dda5020204b (patch) | |
| tree | 65065ba89fb911837148202811c6df9956a8a060 /src/core/arm/interpreter/armsupp.cpp | |
| parent | removed some cruft (diff) | |
| download | yuzu-6151e26958fa243b6322a9a544446dda5020204b.tar.gz yuzu-6151e26958fa243b6322a9a544446dda5020204b.tar.xz yuzu-6151e26958fa243b6322a9a544446dda5020204b.zip | |
added disassembly to unimplemented instruction
Diffstat (limited to 'src/core/arm/interpreter/armsupp.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index 101b9807a..48e55c63a 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp | |||
| @@ -17,9 +17,11 @@ | |||
| 17 | 17 | ||
| 18 | #include "armdefs.h" | 18 | #include "armdefs.h" |
| 19 | #include "armemu.h" | 19 | #include "armemu.h" |
| 20 | |||
| 20 | //#include "ansidecl.h" | 21 | //#include "ansidecl.h" |
| 21 | #include "skyeye_defs.h" | 22 | #include "skyeye_defs.h" |
| 22 | #include "core/hle/hle.h" | 23 | #include "core/hle/hle.h" |
| 24 | #include "core/arm/disassembler/arm_disasm.h" | ||
| 23 | 25 | ||
| 24 | unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, | 26 | unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, |
| 25 | unsigned cpnum); | 27 | unsigned cpnum); |
| @@ -846,7 +848,10 @@ ARMul_CDP (ARMul_State * state, ARMword instr) | |||
| 846 | void | 848 | void |
| 847 | ARMul_UndefInstr (ARMul_State * state, ARMword instr) | 849 | ARMul_UndefInstr (ARMul_State * state, ARMword instr) |
| 848 | { | 850 | { |
| 849 | ERROR_LOG(ARM11, "Undefined instruction!! Instr: 0x%x", instr); | 851 | char buff[512]; |
| 852 | ARM_Disasm disasm = ARM_Disasm(); | ||
| 853 | disasm.disasm(state->pc, instr, buff); | ||
| 854 | ERROR_LOG(ARM11, "Undefined instruction!! Disasm: %s Opcode: 0x%x", buff, instr); | ||
| 850 | ARMul_Abort (state, ARMul_UndefinedInstrV); | 855 | ARMul_Abort (state, ARMul_UndefinedInstrV); |
| 851 | } | 856 | } |
| 852 | 857 | ||