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authorGravatar Lioncash2015-01-31 20:34:26 -0500
committerGravatar Lioncash2015-01-31 20:43:03 -0500
commitf44781fd7b0c5f99573e917ccdd92716a99a9b0d (patch)
treead31575f5653316488371cd654d961ce803e2c01 /src/core/arm/interpreter/arminit.cpp
parentMerge pull request #512 from lioncash/assignment (diff)
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arm: Adios armemu
Diffstat (limited to 'src/core/arm/interpreter/arminit.cpp')
-rw-r--r--src/core/arm/interpreter/arminit.cpp136
1 files changed, 8 insertions, 128 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 8ab5ef160..a0e041fa0 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -25,24 +25,13 @@
25void ARMul_EmulateInit(); 25void ARMul_EmulateInit();
26ARMul_State* ARMul_NewState(ARMul_State* state); 26ARMul_State* ARMul_NewState(ARMul_State* state);
27void ARMul_Reset (ARMul_State* state); 27void ARMul_Reset (ARMul_State* state);
28ARMword ARMul_DoCycle(ARMul_State* state);
29unsigned ARMul_DoCoPro(ARMul_State* state);
30ARMword ARMul_DoProg(ARMul_State* state);
31ARMword ARMul_DoInstr(ARMul_State* state);
32void ARMul_Abort(ARMul_State* state, ARMword address);
33 28
34unsigned ARMul_MultTable[32] = { 29unsigned ARMul_MultTable[32] = {
35 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 30 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
36 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 31 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
37}; 32};
38ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 33ARMword ARMul_ImmedTable[4096]; // immediate DP LHS values
39char ARMul_BitList[256]; /* number of bits in a byte table */ 34char ARMul_BitList[256]; // number of bits in a byte table
40
41void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
42{
43 ARMul_Abort(state, vector);
44}
45
46 35
47/***************************************************************************\ 36/***************************************************************************\
48* Call this routine once to set up the emulator's tables. * 37* Call this routine once to set up the emulator's tables. *
@@ -51,18 +40,21 @@ void ARMul_EmulateInit()
51{ 40{
52 unsigned int i, j; 41 unsigned int i, j;
53 42
54 for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */ 43 // the values of 12 bit dp rhs's
44 for (i = 0; i < 4096; i++) {
55 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); 45 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
56 } 46 }
57 47
58 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ 48 // how many bits in LSM
49 for (i = 0; i < 256; ARMul_BitList[i++] = 0);
59 for (j = 1; j < 256; j <<= 1) 50 for (j = 1; j < 256; j <<= 1)
60 for (i = 0; i < 256; i++) 51 for (i = 0; i < 256; i++)
61 if ((i & j) > 0) 52 if ((i & j) > 0)
62 ARMul_BitList[i]++; 53 ARMul_BitList[i]++;
63 54
55 // you always need 4 times these values
64 for (i = 0; i < 256; i++) 56 for (i = 0; i < 256; i++)
65 ARMul_BitList[i] *= 4; /* you always need 4 times these values */ 57 ARMul_BitList[i] *= 4;
66 58
67} 59}
68 60
@@ -178,115 +170,3 @@ void ARMul_Reset(ARMul_State* state)
178 state->NumCcycles = 0; 170 state->NumCcycles = 0;
179 state->NumFcycles = 0; 171 state->NumFcycles = 0;
180} 172}
181
182
183/***************************************************************************\
184* Emulate the execution of an entire program. Start the correct emulator *
185* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
186* address of the last instruction that is executed. *
187\***************************************************************************/
188ARMword ARMul_DoProg(ARMul_State* state)
189{
190 ARMword pc = 0;
191
192 state->Emulate = RUN;
193 while (state->Emulate != STOP) {
194 state->Emulate = RUN;
195
196 if (state->prog32Sig && ARMul_MODE32BIT) {
197 pc = ARMul_Emulate32 (state);
198 }
199 else {
200 //pc = ARMul_Emulate26 (state);
201 }
202 }
203
204 return pc;
205}
206
207/***************************************************************************\
208* Emulate the execution of one instruction. Start the correct emulator *
209* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
210* address of the instruction that is executed. *
211\***************************************************************************/
212ARMword ARMul_DoInstr(ARMul_State* state)
213{
214 ARMword pc = 0;
215
216 state->Emulate = ONCE;
217
218 if (state->prog32Sig && ARMul_MODE32BIT) {
219 pc = ARMul_Emulate32 (state);
220 }
221
222 return pc;
223}
224
225/***************************************************************************\
226* This routine causes an Abort to occur, including selecting the correct *
227* mode, register bank, and the saving of registers. Call with the *
228* appropriate vector's memory address (0,4,8 ....) *
229\***************************************************************************/
230void ARMul_Abort(ARMul_State* state, ARMword vector)
231{
232 ARMword temp;
233 int isize = INSN_SIZE;
234 int esize = (TFLAG ? 0 : 4);
235 int e2size = (TFLAG ? -4 : 0);
236
237 state->Aborted = FALSE;
238
239 if (state->prog32Sig)
240 if (ARMul_MODE26BIT)
241 temp = R15PC;
242 else
243 temp = state->Reg[15];
244 else
245 temp = R15PC | ECC | ER15INT | EMODE;
246
247 switch (vector) {
248 case ARMul_ResetV: /* RESET */
249 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE,
250 0);
251 break;
252 case ARMul_UndefinedInstrV: /* Undefined Instruction */
253 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE,
254 isize);
255 break;
256 case ARMul_SWIV: /* Software Interrupt */
257 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
258 isize);
259 break;
260 case ARMul_PrefetchAbortV: /* Prefetch Abort */
261 state->AbortAddr = 1;
262 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
263 esize);
264 break;
265 case ARMul_DataAbortV: /* Data Abort */
266 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
267 e2size);
268 break;
269 case ARMul_AddrExceptnV: /* Address Exception */
270 SETABORT (IBIT, SVC26MODE, isize);
271 break;
272 case ARMul_IRQV: /* IRQ */
273 SETABORT (IBIT,
274 state->prog32Sig ? IRQ32MODE : IRQ26MODE,
275 esize);
276 break;
277 case ARMul_FIQV: /* FIQ */
278 SETABORT (INTBITS,
279 state->prog32Sig ? FIQ32MODE : FIQ26MODE,
280 esize);
281 break;
282 }
283
284 if (ARMul_MODE32BIT) {
285 /*if (state->mmu.control & CONTROL_VECTOR)
286 vector += 0xffff0000; //for v4 high exception address*/
287 if (state->vector_remap_flag)
288 vector += state->vector_remap_addr; /* support some remap function in LPC processor */
289 ARMul_SetR15 (state, vector);
290 } else
291 ARMul_SetR15 (state, R15CCINTMODE | vector);
292}