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authorGravatar bunnei2014-07-23 19:16:40 -0400
committerGravatar bunnei2014-07-23 19:16:40 -0400
commit77fc029a00c45ffe48cf4eacf4721e312b2248c0 (patch)
treec29766d5b8374fa7bbc38c1bbb67c3787e4b034a /src/core/arm/interpreter/arminit.cpp
parentMerge pull request #27 from neobrain/disassembly_view_rewrite (diff)
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ARM: Synchronize Citra's SkyEye core with 3dmoo's.
Diffstat (limited to 'src/core/arm/interpreter/arminit.cpp')
-rw-r--r--src/core/arm/interpreter/arminit.cpp744
1 files changed, 342 insertions, 402 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index e05667bea..6fbab3bfb 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -1,30 +1,21 @@
1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. 1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd. 2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3 3
4 This program is free software; you can redistribute it and/or modify 4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by 5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or 6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version. 7 (at your option) any later version.
8 8
9 This program is distributed in the hope that it will be useful, 9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of 10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details. 12 GNU General Public License for more details.
13 13
14 You should have received a copy of the GNU General Public License 14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18 18//#include <unistd.h>
19#include "common/platform.h"
20
21#if EMU_PLATFORM == PLATFORM_LINUX
22#include <unistd.h>
23#elif EMU_PLATFORM == PLATFORM_WINDOWS
24#include <windows.h>
25#endif
26
27#include <math.h>
28 19
29#include "core/arm/interpreter/armdefs.h" 20#include "core/arm/interpreter/armdefs.h"
30#include "core/arm/interpreter/armemu.h" 21#include "core/arm/interpreter/armemu.h"
@@ -42,9 +33,9 @@ ARMword ARMul_DoProg (ARMul_State * state);
42ARMword ARMul_DoInstr (ARMul_State * state); 33ARMword ARMul_DoInstr (ARMul_State * state);
43void ARMul_Abort (ARMul_State * state, ARMword address); 34void ARMul_Abort (ARMul_State * state, ARMword address);
44 35
45unsigned ARMul_MultTable[32] = 36unsigned ARMul_MultTable[32] = {
46 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 37 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
47 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 38 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
48}; 39};
49ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 40ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
50char ARMul_BitList[256]; /* number of bits in a byte table */ 41char ARMul_BitList[256]; /* number of bits in a byte table */
@@ -56,78 +47,34 @@ extern int remote_interrupt( void );
56 47
57void arm_dyncom_Abort(ARMul_State * state, ARMword vector) 48void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
58{ 49{
59 ARMul_Abort(state, vector); 50 ARMul_Abort(state, vector);
60} 51}
61 52
62 53
63/* ahe-ykl : the following code to initialize user mode 54/* ahe-ykl : the following code to initialize user mode
64 code is architecture dependent and probably model dependant. */ 55 code is architecture dependent and probably model dependant. */
65 56
66//#include "skyeye_arch.h" 57/*#include "skyeye_arch.h"
67//#include "skyeye_pref.h" 58#include "skyeye_pref.h"
68//#include "skyeye_exec_info.h" 59#include "skyeye_exec_info.h"
69//#include "bank_defs.h" 60#include "bank_defs.h"*/
70#include "armcpu.h" 61//#include "armcpu.h"
71//#include "skyeye_callback.h" 62//#include "skyeye_callback.h"
72 63
73//void arm_user_mode_init(generic_arch_t * arch_instance) 64/*
74//{ 65 ARM_CPU_State* cpu = get_current_cpu();
75// sky_pref_t *pref = get_skyeye_pref(); 66 arm_core_t* core = &cpu->core[0];
76//
77// if (pref->user_mode_sim)
78// {
79// sky_exec_info_t *info = get_skyeye_exec_info();
80// info->arch_page_size = 0x1000;
81// info->arch_stack_top = 0x1ffffff0;// + 0x401fe7 - 0xff0; /* arbitrary value */
82// /* stack initial address specific to architecture may be placed here */
83//
84// /* we need to mmap the stack space, if we are using skyeye space */
85// if (info->mmap_access)
86// {
87// /* get system stack size */
88// size_t stacksize = 0;
89// pthread_attr_t attr;
90// pthread_attr_init(&attr);
91// pthread_attr_getstacksize(&attr, &stacksize);
92// if (stacksize > info->arch_stack_top)
93// {
94// printf("arch_stack_top is too low\n");
95// stacksize = info->arch_stack_top;
96// }
97//
98// /* Note: Skyeye is occupating 0x400000 to 0x600000 */
99// /* We do a mmap */
100// void* ret = mmap( (info->arch_stack_top) - stacksize,
101// stacksize + 0x1000 , PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
102// if (ret == MAP_FAILED){
103// /* ideally, we should find an empty space until it works */
104// printf("mmap error, stack couldn't be mapped: errno %d\n", errno);
105// exit(-1);
106// } else {
107// memset(ret, '\0', stacksize);
108// //printf("stack top has been defined at %x size %x\n", (uint32_t) ret + stacksize, stacksize);
109// //info->arch_stack_top = (uint32_t) ret + stacksize;
110// }
111// }
112//
113// exec_stack_init();
114//
115// ARM_CPU_State* cpu = get_current_cpu();
116// arm_core_t* core = &cpu->core[0];
117//
118// uint32_t sp = info->initial_sp;
119//
120// core->Cpsr = 0x10; /* User mode */
121// /* FIXME: may need to add thumb */
122// core->Reg[13] = sp;
123// core->Reg[10] = info->start_data;
124// core->Reg[0] = 0;
125// bus_read(32, sp + 4, &(core->Reg[1]));
126// bus_read(32, sp + 8, &(core->Reg[2]));
127// }
128//
129//}
130 67
68 uint32_t sp = info->initial_sp;
69
70 core->Cpsr = 0x10; // User mode
71// FIXME: may need to add thumb
72core->Reg[13] = sp;
73core->Reg[10] = info->start_data;
74core->Reg[0] = 0;
75bus_read(32, sp + 4, &(core->Reg[1]));
76bus_read(32, sp + 8, &(core->Reg[2]));
77*/
131/***************************************************************************\ 78/***************************************************************************\
132* Call this routine once to set up the emulator's tables. * 79* Call this routine once to set up the emulator's tables. *
133\***************************************************************************/ 80\***************************************************************************/
@@ -135,20 +82,20 @@ void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
135void 82void
136ARMul_EmulateInit (void) 83ARMul_EmulateInit (void)
137{ 84{
138 unsigned int i, j; 85 unsigned int i, j;
139 86
140 for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */ 87 for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */
141 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); 88 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
142 } 89 }
143 90
144 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ 91 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
145 for (j = 1; j < 256; j <<= 1) 92 for (j = 1; j < 256; j <<= 1)
146 for (i = 0; i < 256; i++) 93 for (i = 0; i < 256; i++)
147 if ((i & j) > 0) 94 if ((i & j) > 0)
148 ARMul_BitList[i]++; 95 ARMul_BitList[i]++;
149 96
150 for (i = 0; i < 256; i++) 97 for (i = 0; i < 256; i++)
151 ARMul_BitList[i] *= 4; /* you always need 4 times these values */ 98 ARMul_BitList[i] *= 4; /* you always need 4 times these values */
152 99
153} 100}
154 101
@@ -159,80 +106,82 @@ ARMul_EmulateInit (void)
159ARMul_State * 106ARMul_State *
160ARMul_NewState (ARMul_State *state) 107ARMul_NewState (ARMul_State *state)
161{ 108{
162 unsigned i, j; 109 unsigned i, j;
163 110
164 memset (state, 0, sizeof (ARMul_State)); 111 memset (state, 0, sizeof (ARMul_State));
165 112
166 state->Emulate = RUN; 113 state->Emulate = RUN;
167 for (i = 0; i < 16; i++) { 114 for (i = 0; i < 16; i++) {
168 state->Reg[i] = 0; 115 state->Reg[i] = 0;
169 for (j = 0; j < 7; j++) 116 for (j = 0; j < 7; j++)
170 state->RegBank[j][i] = 0; 117 state->RegBank[j][i] = 0;
171 } 118 }
172 for (i = 0; i < 7; i++) 119 for (i = 0; i < 7; i++)
173 state->Spsr[i] = 0; 120 state->Spsr[i] = 0;
174 state->Mode = 0; 121 state->Mode = 0;
175 122
176 state->CallDebug = FALSE; 123 state->CallDebug = FALSE;
177 state->Debug = FALSE; 124 state->Debug = FALSE;
178 state->VectorCatch = 0; 125 state->VectorCatch = 0;
179 state->Aborted = FALSE; 126 state->Aborted = FALSE;
180 state->Reseted = FALSE; 127 state->Reseted = FALSE;
181 state->Inted = 3; 128 state->Inted = 3;
182 state->LastInted = 3; 129 state->LastInted = 3;
183 130
184 state->CommandLine = NULL; 131 state->CommandLine = NULL;
185 132
186 state->EventSet = 0; 133 state->EventSet = 0;
187 state->Now = 0; 134 state->Now = 0;
188 state->EventPtr = 135 state->EventPtr =
189 (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * 136 (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
190 sizeof (struct EventNode *)); 137 sizeof (struct EventNode *));
191#if DIFF_STATE 138#if DIFF_STATE
192 state->state_log = fopen("/data/state.log", "w"); 139 state->state_log = fopen("/data/state.log", "w");
193 printf("create pc log file.\n"); 140 printf("create pc log file.\n");
194#endif 141#endif
195 if (state->EventPtr == NULL) { 142 if (state->EventPtr == NULL) {
196 printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n"); 143 printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n");
197 exit(-1); 144 exit(-1);
198 } 145 //skyeye_exit (-1);
199 for (i = 0; i < EVENTLISTSIZE; i++) 146 }
200 *(state->EventPtr + i) = NULL; 147 for (i = 0; i < EVENTLISTSIZE; i++)
148 *(state->EventPtr + i) = NULL;
201#if SAVE_LOG 149#if SAVE_LOG
202 state->state_log = fopen("/tmp/state.log", "w"); 150 state->state_log = fopen("/tmp/state.log", "w");
203 printf("create pc log file.\n"); 151 printf("create pc log file.\n");
204#else 152#else
205#if DIFF_LOG 153#if DIFF_LOG
206 state->state_log = fopen("/tmp/state.log", "r"); 154 state->state_log = fopen("/tmp/state.log", "r");
207 printf("loaded pc log file.\n"); 155 printf("loaded pc log file.\n");
208#endif 156#endif
209#endif 157#endif
210 158
211#ifdef ARM61 159#ifdef ARM61
212 state->prog32Sig = LOW; 160 state->prog32Sig = LOW;
213 state->data32Sig = LOW; 161 state->data32Sig = LOW;
214#else 162#else
215 state->prog32Sig = HIGH; 163 state->prog32Sig = HIGH;
216 state->data32Sig = HIGH; 164 state->data32Sig = HIGH;
217#endif 165#endif
218 166
219 state->lateabtSig = HIGH; 167 state->lateabtSig = HIGH;
220 state->bigendSig = LOW; 168 state->bigendSig = LOW;
221 169
222 //chy:2003-08-19 170 //chy:2003-08-19
223 state->LastTime = 0; 171 state->LastTime = 0;
224 state->CP14R0_CCD = -1; 172 state->CP14R0_CCD = -1;
225 173
226 /* ahe-ykl: common function for interpret and dyncom */ 174 /* ahe-ykl: common function for interpret and dyncom */
227 //sky_pref_t *pref = get_skyeye_pref(); 175 /*sky_pref_t *pref = get_skyeye_pref();
228 //if (pref->user_mode_sim) 176 if (pref->user_mode_sim)
229 // register_callback(arm_user_mode_init, Bootmach_callback); 177 register_callback(arm_user_mode_init, Bootmach_callback);
230 178 */
231 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128); 179
232 state->exclusive_access_state = 0; 180 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128);
233 //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t)); 181 state->exclusive_access_state = 0;
234 //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t)); 182 //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t));
235 return (state); 183 //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t));
184 return (state);
236} 185}
237 186
238/***************************************************************************\ 187/***************************************************************************\
@@ -242,39 +191,38 @@ ARMul_NewState (ARMul_State *state)
242void 191void
243ARMul_SelectProcessor (ARMul_State * state, unsigned properties) 192ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
244{ 193{
245 if (properties & ARM_Fix26_Prop) { 194 if (properties & ARM_Fix26_Prop) {
246 state->prog32Sig = LOW; 195 state->prog32Sig = LOW;
247 state->data32Sig = LOW; 196 state->data32Sig = LOW;
248 } 197 } else {
249 else { 198 state->prog32Sig = HIGH;
250 state->prog32Sig = HIGH; 199 state->data32Sig = HIGH;
251 state->data32Sig = HIGH; 200 }
252 } 201 /* 2004-05-09 chy
253/* 2004-05-09 chy 202 below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function
254below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function 203 */
255*/ 204 // state->lateabtSig = HIGH;
256 // state->lateabtSig = HIGH; 205
257 206
258 207 state->is_v4 =
259 state->is_v4 = 208 (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
260 (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; 209 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
261 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; 210 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
262 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; 211 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
263 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; 212 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
264 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; 213 /* state->is_v6 = LOW */;
265 /* state->is_v6 = LOW */; 214 /* jeff.du 2010-08-05 */
266 /* jeff.du 2010-08-05 */ 215 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
267 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; 216 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
268 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; 217 //chy 2005-09-19
269 //chy 2005-09-19 218 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW;
270 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW; 219
271 220 /* shenoubang 2012-3-11 */
272 /* shenoubang 2012-3-11 */ 221 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW;
273 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW; 222
274 223 /* Only initialse the coprocessor support once we
275 /* Only initialse the coprocessor support once we 224 know what kind of chip we are dealing with. */
276 know what kind of chip we are dealing with. */ 225 //ARMul_CoProInit (state);
277 ARMul_CoProInit (state);
278 226
279} 227}
280 228
@@ -285,66 +233,65 @@ below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function
285void 233void
286ARMul_Reset (ARMul_State * state) 234ARMul_Reset (ARMul_State * state)
287{ 235{
288 //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 236 //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
289 state->NextInstr = 0; 237 state->NextInstr = 0;
290 if (state->prog32Sig) { 238 if (state->prog32Sig) {
291 state->Reg[15] = 0; 239 state->Reg[15] = 0;
292 state->Cpsr = INTBITS | SVC32MODE; 240 state->Cpsr = INTBITS | SVC32MODE;
293 state->Mode = SVC32MODE; 241 state->Mode = SVC32MODE;
294 } 242 } else {
295 else { 243 state->Reg[15] = R15INTBITS | SVC26MODE;
296 state->Reg[15] = R15INTBITS | SVC26MODE; 244 state->Cpsr = INTBITS | SVC26MODE;
297 state->Cpsr = INTBITS | SVC26MODE; 245 state->Mode = SVC26MODE;
298 state->Mode = SVC26MODE; 246 }
299 } 247 //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
300 //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 248 //ARMul_CPSRAltered (state);
301 ARMul_CPSRAltered (state); 249 state->Bank = SVCBANK;
302 state->Bank = SVCBANK; 250 FLUSHPIPE;
303 FLUSHPIPE; 251
304 252 state->EndCondition = 0;
305 state->EndCondition = 0; 253 state->ErrorCode = 0;
306 state->ErrorCode = 0; 254
307 255 //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
308 //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 256 state->NresetSig = HIGH;
309 state->NresetSig = HIGH; 257 state->NfiqSig = HIGH;
310 state->NfiqSig = HIGH; 258 state->NirqSig = HIGH;
311 state->NirqSig = HIGH; 259 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
312 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 260 state->abortSig = LOW;
313 state->abortSig = LOW; 261 state->AbortAddr = 1;
314 state->AbortAddr = 1; 262
315 263 state->NumInstrs = 0;
316 state->NumInstrs = 0; 264 state->NumNcycles = 0;
317 state->NumNcycles = 0; 265 state->NumScycles = 0;
318 state->NumScycles = 0; 266 state->NumIcycles = 0;
319 state->NumIcycles = 0; 267 state->NumCcycles = 0;
320 state->NumCcycles = 0; 268 state->NumFcycles = 0;
321 state->NumFcycles = 0; 269
322 270 //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
323 //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 271 //mmu_reset (state);
324 mmu_reset (state); 272 //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
325 //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 273
326 274 //mem_reset (state); /* move to memory/ram.c */
327 //mem_reset (state); /* move to memory/ram.c */ 275
328 276 //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
329 //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 277 /*remove later. walimis 03.7.17 */
330 /*remove later. walimis 03.7.17 */ 278 //io_reset(state);
331 //io_reset(state); 279 //lcd_disable(state);
332 //lcd_disable(state); 280
333 281 /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will
334 /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will 282 *be configured in skyeye_option_init and it is called after ARMul_NewState*/
335 *be configured in skyeye_option_init and it is called after ARMul_NewState*/ 283 state->tea_break_ok = 0;
336 state->tea_break_ok = 0; 284 state->tea_break_addr = 0;
337 state->tea_break_addr = 0; 285 state->tea_pc = 0;
338 state->tea_pc = 0;
339#ifdef DBCT 286#ifdef DBCT
340 if (!skyeye_config.no_dbct) { 287 if (!skyeye_config.no_dbct) {
341 //teawater add for arm2x86 2005.02.14------------------------------------------- 288 //teawater add for arm2x86 2005.02.14-------------------------------------------
342 if (arm2x86_init (state)) { 289 if (arm2x86_init (state)) {
343 printf ("SKYEYE: arm2x86_init error\n"); 290 printf ("SKYEYE: arm2x86_init error\n");
344 skyeye_exit (-1); 291 //skyeye_exit (-1);
345 } 292 }
346 //AJ2D-------------------------------------------------------------------------- 293 //AJ2D--------------------------------------------------------------------------
347 } 294 }
348#endif 295#endif
349} 296}
350 297
@@ -361,8 +308,9 @@ static ARMul_State *dbct_test_speed_state = NULL;
361static void 308static void
362dbct_test_speed_sig(int signo) 309dbct_test_speed_sig(int signo)
363{ 310{
364 printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count); 311 printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count);
365 skyeye_exit(0); 312 exit(0);
313 //skyeye_exit(0);
366} 314}
367#endif //DBCT_TEST_SPEED 315#endif //DBCT_TEST_SPEED
368//AJ2D-------------------------------------------------------------------------- 316//AJ2D--------------------------------------------------------------------------
@@ -370,92 +318,91 @@ dbct_test_speed_sig(int signo)
370ARMword 318ARMword
371ARMul_DoProg (ARMul_State * state) 319ARMul_DoProg (ARMul_State * state)
372{ 320{
373 ARMword pc = 0; 321 ARMword pc = 0;
374 322
375 /* 323 /*
376 * 2007-01-24 removed the term-io functions by Anthony Lee, 324 * 2007-01-24 removed the term-io functions by Anthony Lee,
377 * moved to "device/uart/skyeye_uart_stdio.c". 325 * moved to "device/uart/skyeye_uart_stdio.c".
378 */ 326 */
379 327
380//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- 328//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
381#ifdef DBCT_TEST_SPEED 329#ifdef DBCT_TEST_SPEED
382 { 330 {
383 if (!dbct_test_speed_state) { 331 if (!dbct_test_speed_state) {
384 //init timer 332 //init timer
385 struct itimerval value; 333 struct itimerval value;
386 struct sigaction act; 334 struct sigaction act;
387 335
388 dbct_test_speed_state = state; 336 dbct_test_speed_state = state;
389 state->instr_count = 0; 337 state->instr_count = 0;
390 act.sa_handler = dbct_test_speed_sig; 338 act.sa_handler = dbct_test_speed_sig;
391 act.sa_flags = SA_RESTART; 339 act.sa_flags = SA_RESTART;
392 //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF 340 //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF
393#ifndef __CYGWIN__ 341#ifndef __CYGWIN__
394 if (sigaction(SIGVTALRM, &act, NULL) == -1) { 342 if (sigaction(SIGVTALRM, &act, NULL) == -1) {
395#else 343#else
396 if (sigaction(SIGALRM, &act, NULL) == -1) { 344 if (sigaction(SIGALRM, &act, NULL) == -1) {
397#endif //__CYGWIN__ 345#endif //__CYGWIN__
398 fprintf(stderr, "init timer error.\n"); 346 fprintf(stderr, "init timer error.\n");
399 skyeye_exit(-1); 347 exit(-1);
400 } 348 //skyeye_exit(-1);
401 if (skyeye_config.dbct_test_speed_sec) { 349 }
402 value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec; 350 if (skyeye_config.dbct_test_speed_sec) {
403 } 351 value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec;
404 else { 352 } else {
405 value.it_value.tv_sec = DBCT_TEST_SPEED_SEC; 353 value.it_value.tv_sec = DBCT_TEST_SPEED_SEC;
406 } 354 }
407 printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec); 355 printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec);
408 value.it_value.tv_usec = 0; 356 value.it_value.tv_usec = 0;
409 value.it_interval.tv_sec = 0; 357 value.it_interval.tv_sec = 0;
410 value.it_interval.tv_usec = 0; 358 value.it_interval.tv_usec = 0;
411#ifndef __CYGWIN__ 359#ifndef __CYGWIN__
412 if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) { 360 if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) {
413#else 361#else
414 if (setitimer(ITIMER_REAL, &value, NULL) == -1) { 362 if (setitimer(ITIMER_REAL, &value, NULL) == -1) {
415#endif //__CYGWIN__ 363#endif //__CYGWIN__
416 fprintf(stderr, "init timer error.\n"); 364 fprintf(stderr, "init timer error.\n");
417 skyeye_exit(-1); 365 //skyeye_exit(-1);
418 } 366 }
419 } 367 }
420 } 368 }
421#endif //DBCT_TEST_SPEED 369#endif //DBCT_TEST_SPEED
422//AJ2D-------------------------------------------------------------------------- 370//AJ2D--------------------------------------------------------------------------
423 state->Emulate = RUN; 371 state->Emulate = RUN;
424 while (state->Emulate != STOP) { 372 while (state->Emulate != STOP) {
425 state->Emulate = RUN; 373 state->Emulate = RUN;
426 374
427 /*ywc 2005-03-31 */ 375 /*ywc 2005-03-31 */
428 if (state->prog32Sig && ARMul_MODE32BIT) { 376 if (state->prog32Sig && ARMul_MODE32BIT) {
429#ifdef DBCT 377#ifdef DBCT
430 if (skyeye_config.no_dbct) { 378 if (skyeye_config.no_dbct) {
431 pc = ARMul_Emulate32 (state); 379 pc = ARMul_Emulate32 (state);
432 } 380 } else {
433 else { 381 pc = ARMul_Emulate32_dbct (state);
434 pc = ARMul_Emulate32_dbct (state); 382 }
435 }
436#else 383#else
437 pc = ARMul_Emulate32 (state); 384 pc = ARMul_Emulate32 (state);
438#endif 385#endif
439 } 386 }
440 387
441 else { 388 else {
442 _dbg_assert_msg_(ARM11, false, "Unsupported ARM 26-bit Mode!"); 389 //pc = ARMul_Emulate26 (state);
443 } 390 }
444 //chy 2006-02-22, should test debugmode first 391 //chy 2006-02-22, should test debugmode first
445 //chy 2006-04-14, put below codes in ARMul_Emulate 392 //chy 2006-04-14, put below codes in ARMul_Emulate
446#if 0 393#if 0
447 if(debugmode) 394 if(debugmode)
448 if(remote_interrupt()) 395 if(remote_interrupt())
449 state->Emulate = STOP; 396 state->Emulate = STOP;
450#endif 397#endif
451 } 398 }
452 399
453 /* 400 /*
454 * 2007-01-24 removed the term-io functions by Anthony Lee, 401 * 2007-01-24 removed the term-io functions by Anthony Lee,
455 * moved to "device/uart/skyeye_uart_stdio.c". 402 * moved to "device/uart/skyeye_uart_stdio.c".
456 */ 403 */
457 404
458 return (pc); 405 return (pc);
459} 406}
460 407
461/***************************************************************************\ 408/***************************************************************************\
@@ -467,36 +414,34 @@ ARMul_DoProg (ARMul_State * state)
467ARMword 414ARMword
468ARMul_DoInstr (ARMul_State * state) 415ARMul_DoInstr (ARMul_State * state)
469{ 416{
470 ARMword pc = 0; 417 ARMword pc = 0;
471 418
472 state->Emulate = ONCE; 419 state->Emulate = ONCE;
473 420
474 /*ywc 2005-03-31 */ 421 /*ywc 2005-03-31 */
475 if (state->prog32Sig && ARMul_MODE32BIT) { 422 if (state->prog32Sig && ARMul_MODE32BIT) {
476#ifdef DBCT 423#ifdef DBCT
477 if (skyeye_config.no_dbct) { 424 if (skyeye_config.no_dbct) {
478 pc = ARMul_Emulate32 (state); 425 pc = ARMul_Emulate32 (state);
479 } 426 } else {
480 else {
481//teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- 427//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
482#ifndef DBCT_GDBRSP 428#ifndef DBCT_GDBRSP
483 printf("DBCT GDBRSP function switch is off.\n"); 429 printf("DBCT GDBRSP function switch is off.\n");
484 printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n"); 430 printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n");
485 skyeye_exit(-1); 431 skyeye_exit(-1);
486#endif //DBCT_GDBRSP 432#endif //DBCT_GDBRSP
487//AJ2D-------------------------------------------------------------------------- 433//AJ2D--------------------------------------------------------------------------
488 pc = ARMul_Emulate32_dbct (state); 434 pc = ARMul_Emulate32_dbct (state);
489 } 435 }
490#else 436#else
491 pc = ARMul_Emulate32 (state); 437 pc = ARMul_Emulate32 (state);
492#endif 438#endif
493 } 439 }
494 440
495 else { 441 //else
496 _dbg_assert_msg_(ARM11, false, "Unsupported ARM 26-bit Mode!"); 442 //pc = ARMul_Emulate26 (state);
497 }
498 443
499 return (pc); 444 return (pc);
500} 445}
501 446
502/***************************************************************************\ 447/***************************************************************************\
@@ -508,79 +453,74 @@ ARMul_DoInstr (ARMul_State * state)
508void 453void
509ARMul_Abort (ARMul_State * state, ARMword vector) 454ARMul_Abort (ARMul_State * state, ARMword vector)
510{ 455{
511 ARMword temp; 456 ARMword temp;
512 int isize = INSN_SIZE; 457 int isize = INSN_SIZE;
513 int esize = (TFLAG ? 0 : 4); 458 int esize = (TFLAG ? 0 : 4);
514 int e2size = (TFLAG ? -4 : 0); 459 int e2size = (TFLAG ? -4 : 0);
515 460
516 state->Aborted = FALSE; 461 state->Aborted = FALSE;
517 462
518 if (state->prog32Sig) 463 if (state->prog32Sig)
519 if (ARMul_MODE26BIT) 464 if (ARMul_MODE26BIT)
520 temp = R15PC; 465 temp = R15PC;
521 else 466 else
522 temp = state->Reg[15]; 467 temp = state->Reg[15];
523 else 468 else
524 temp = R15PC | ECC | ER15INT | EMODE; 469 temp = R15PC | ECC | ER15INT | EMODE;
525 470
526 switch (vector) { 471 switch (vector) {
527 case ARMul_ResetV: /* RESET */ 472 case ARMul_ResetV: /* RESET */
528 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 473 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE,
529 0); 474 0);
530 break; 475 break;
531 case ARMul_UndefinedInstrV: /* Undefined Instruction */ 476 case ARMul_UndefinedInstrV: /* Undefined Instruction */
532 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, 477 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE,
533 isize); 478 isize);
534 break; 479 break;
535 case ARMul_SWIV: /* Software Interrupt */ 480 case ARMul_SWIV: /* Software Interrupt */
536 // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE 481 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
537 // Instead of doing normal routine, backup R15 by one instruction (this is what PC will get 482 isize);
538 // set to, making it the next instruction after the SVC call), and skip setting the LR. 483 break;
539 SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, 484 case ARMul_PrefetchAbortV: /* Prefetch Abort */
540 isize); 485 state->AbortAddr = 1;
541 state->Reg[15] -= 4; 486 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
542 return; 487 esize);
543 case ARMul_PrefetchAbortV: /* Prefetch Abort */ 488 break;
544 state->AbortAddr = 1; 489 case ARMul_DataAbortV: /* Data Abort */
545 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, 490 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
546 esize); 491 e2size);
547 break; 492 break;
548 case ARMul_DataAbortV: /* Data Abort */ 493 case ARMul_AddrExceptnV: /* Address Exception */
549 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, 494 SETABORT (IBIT, SVC26MODE, isize);
550 e2size); 495 break;
551 break; 496 case ARMul_IRQV: /* IRQ */
552 case ARMul_AddrExceptnV: /* Address Exception */ 497 //chy 2003-09-02 the if sentence seems no use
553 SETABORT (IBIT, SVC26MODE, isize);
554 break;
555 case ARMul_IRQV: /* IRQ */
556 //chy 2003-09-02 the if sentence seems no use
557#if 0 498#if 0
558 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) 499 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
559 || (temp & ARMul_CP13_R0_IRQ)) 500 || (temp & ARMul_CP13_R0_IRQ))
560#endif 501#endif
561 SETABORT (IBIT, 502 SETABORT (IBIT,
562 state->prog32Sig ? IRQ32MODE : IRQ26MODE, 503 state->prog32Sig ? IRQ32MODE : IRQ26MODE,
563 esize); 504 esize);
564 break; 505 break;
565 case ARMul_FIQV: /* FIQ */ 506 case ARMul_FIQV: /* FIQ */
566 //chy 2003-09-02 the if sentence seems no use 507 //chy 2003-09-02 the if sentence seems no use
567#if 0 508#if 0
568 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) 509 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
569 || (temp & ARMul_CP13_R0_FIQ)) 510 || (temp & ARMul_CP13_R0_FIQ))
570#endif 511#endif
571 SETABORT (INTBITS, 512 SETABORT (INTBITS,
572 state->prog32Sig ? FIQ32MODE : FIQ26MODE, 513 state->prog32Sig ? FIQ32MODE : FIQ26MODE,
573 esize); 514 esize);
574 break; 515 break;
575 } 516 }
576 517
577 if (ARMul_MODE32BIT) { 518 if (ARMul_MODE32BIT) {
578 if (state->mmu.control & CONTROL_VECTOR) 519 /*if (state->mmu.control & CONTROL_VECTOR)
579 vector += 0xffff0000; //for v4 high exception address 520 vector += 0xffff0000; //for v4 high exception address*/
580 if (state->vector_remap_flag) 521 if (state->vector_remap_flag)
581 vector += state->vector_remap_addr; /* support some remap function in LPC processor */ 522 vector += state->vector_remap_addr; /* support some remap function in LPC processor */
582 ARMul_SetR15 (state, vector); 523 ARMul_SetR15 (state, vector);
583 } 524 } else
584 else 525 ARMul_SetR15 (state, R15CCINTMODE | vector);
585 ARMul_SetR15 (state, R15CCINTMODE | vector);
586} 526}
HIC SVNT DRACONES