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authorGravatar Normmatt2014-12-17 02:54:24 -0500
committerGravatar Lioncash2014-12-17 03:17:44 -0500
commitb5dbd6f2a27cc85a7262920942dd1c78fff21bb5 (patch)
tree25c9e49781d45aace8ce19c1559c834b21b61fc3 /src/core/arm/interpreter/armemu.cpp
parentarmemu: Fix SXTAH (diff)
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armemu: Fix SXTAB
Diffstat (limited to 'src/core/arm/interpreter/armemu.cpp')
-rw-r--r--src/core/arm/interpreter/armemu.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 843323293..cffbae7e7 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6044,7 +6044,7 @@ L_stm_s_takeabort:
6044 break; 6044 break;
6045 } 6045 }
6046 6046
6047 Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF); 6047 Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF;
6048 if (Rm & 0x80) 6048 if (Rm & 0x80)
6049 Rm |= 0xffffff00; 6049 Rm |= 0xffffff00;
6050 6050
@@ -6053,7 +6053,7 @@ L_stm_s_takeabort:
6053 state->Reg[BITS(12, 15)] = Rm; 6053 state->Reg[BITS(12, 15)] = Rm;
6054 else 6054 else
6055 /* SXTAB */ 6055 /* SXTAB */
6056 state->Reg[BITS(12, 15)] += Rm; 6056 state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
6057 6057
6058 return 1; 6058 return 1;
6059 } 6059 }