dyncom: Implement SMLAD/SMUAD/SMLSD/SMUSD

1 files changed, 4 insertions, 2 deletions

diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 43b1ba40e..40e4837d8 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6470,10 +6470,12 @@ L_stm_s_takeabort:
 
                     if (BITS(12, 15) != 15) {
                         state->Reg[rd_idx] += state->Reg[ra_idx];
-                        ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
+                        if (ARMul_AddOverflowQ(product1 + product2, state->Reg[ra_idx]))
+                            SETQ;
                     }
 
-                    ARMul_AddOverflowQ(state, product1, product2);
+                    if (ARMul_AddOverflowQ(product1, product2))
+                        SETQ;
                 }
                 // SMUSD and SMLSD
                 else {