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| author | 2015-01-31 20:34:26 -0500 | |
|---|---|---|
| committer | 2015-01-31 20:43:03 -0500 | |
| commit | f44781fd7b0c5f99573e917ccdd92716a99a9b0d (patch) | |
| tree | ad31575f5653316488371cd654d961ce803e2c01 /src/core/arm/interpreter/armcopro.cpp | |
| parent | Merge pull request #512 from lioncash/assignment (diff) | |
| download | yuzu-f44781fd7b0c5f99573e917ccdd92716a99a9b0d.tar.gz yuzu-f44781fd7b0c5f99573e917ccdd92716a99a9b0d.tar.xz yuzu-f44781fd7b0c5f99573e917ccdd92716a99a9b0d.zip | |
arm: Adios armemu
Diffstat (limited to 'src/core/arm/interpreter/armcopro.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armcopro.cpp | 254 |
1 files changed, 36 insertions, 218 deletions
diff --git a/src/core/arm/interpreter/armcopro.cpp b/src/core/arm/interpreter/armcopro.cpp index b4ddc3d96..bb9ca98fe 100644 --- a/src/core/arm/interpreter/armcopro.cpp +++ b/src/core/arm/interpreter/armcopro.cpp | |||
| @@ -19,213 +19,45 @@ | |||
| 19 | #include "core/arm/skyeye_common/armemu.h" | 19 | #include "core/arm/skyeye_common/armemu.h" |
| 20 | #include "core/arm/skyeye_common/vfp/vfp.h" | 20 | #include "core/arm/skyeye_common/vfp/vfp.h" |
| 21 | 21 | ||
| 22 | //chy 2005-07-08 | 22 | // Dummy Co-processors. |
| 23 | //#include "ansidecl.h" | ||
| 24 | //chy ------- | ||
| 25 | //#include "iwmmxt.h" | ||
| 26 | 23 | ||
| 27 | /* Dummy Co-processors. */ | 24 | static unsigned int NoCoPro3R(ARMul_State* state, unsigned int a, ARMword b) |
| 28 | |||
| 29 | static unsigned | ||
| 30 | NoCoPro3R(ARMul_State * state, | ||
| 31 | unsigned a, ARMword b) | ||
| 32 | { | 25 | { |
| 33 | return ARMul_CANT; | 26 | return ARMul_CANT; |
| 34 | } | 27 | } |
| 35 | 28 | ||
| 36 | static unsigned | 29 | static unsigned int NoCoPro4R(ARMul_State* state, unsigned int a, ARMword b, ARMword c) |
| 37 | NoCoPro4R(ARMul_State * state, | ||
| 38 | unsigned a, | ||
| 39 | ARMword b, ARMword c) | ||
| 40 | { | 30 | { |
| 41 | return ARMul_CANT; | 31 | return ARMul_CANT; |
| 42 | } | 32 | } |
| 43 | 33 | ||
| 44 | static unsigned | 34 | static unsigned int NoCoPro4W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c) |
| 45 | NoCoPro4W(ARMul_State * state, | ||
| 46 | unsigned a, | ||
| 47 | ARMword b, ARMword * c) | ||
| 48 | { | 35 | { |
| 49 | return ARMul_CANT; | 36 | return ARMul_CANT; |
| 50 | } | 37 | } |
| 51 | 38 | ||
| 52 | static unsigned | 39 | static unsigned int NoCoPro5R(ARMul_State* state, unsigned int a, ARMword b, ARMword c, ARMword d) |
| 53 | NoCoPro5R(ARMul_State * state, | ||
| 54 | unsigned a, | ||
| 55 | ARMword b, | ||
| 56 | ARMword c, ARMword d) | ||
| 57 | { | 40 | { |
| 58 | return ARMul_CANT; | 41 | return ARMul_CANT; |
| 59 | } | 42 | } |
| 60 | 43 | ||
| 61 | static unsigned | 44 | static unsigned int NoCoPro5W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c, ARMword* d) |
| 62 | NoCoPro5W(ARMul_State * state, | ||
| 63 | unsigned a, | ||
| 64 | ARMword b, | ||
| 65 | ARMword * c, ARMword * d) | ||
| 66 | { | 45 | { |
| 67 | return ARMul_CANT; | 46 | return ARMul_CANT; |
| 68 | } | 47 | } |
| 69 | 48 | ||
| 70 | /* The XScale Co-processors. */ | 49 | // Install co-processor instruction handlers in this routine. |
| 71 | 50 | unsigned int ARMul_CoProInit(ARMul_State* state) | |
| 72 | /* Coprocessor 15: System Control. */ | ||
| 73 | static void write_cp14_reg(unsigned, ARMword); | ||
| 74 | static ARMword read_cp14_reg(unsigned); | ||
| 75 | |||
| 76 | /* Check an access to a register. */ | ||
| 77 | |||
| 78 | static unsigned | ||
| 79 | check_cp15_access(ARMul_State * state, | ||
| 80 | unsigned reg, | ||
| 81 | unsigned CRm, unsigned opcode_1, unsigned opcode_2) | ||
| 82 | { | ||
| 83 | /* Do not allow access to these register in USER mode. */ | ||
| 84 | //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode | ||
| 85 | if (state->Mode == USER26MODE || state->Mode == USER32MODE) | ||
| 86 | return ARMul_CANT; | ||
| 87 | |||
| 88 | /* Opcode_1should be zero. */ | ||
| 89 | if (opcode_1 != 0) | ||
| 90 | return ARMul_CANT; | ||
| 91 | |||
| 92 | /* Different register have different access requirements. */ | ||
| 93 | switch (reg) { | ||
| 94 | case 0: | ||
| 95 | case 1: | ||
| 96 | /* CRm must be 0. Opcode_2 can be anything. */ | ||
| 97 | if (CRm != 0) | ||
| 98 | return ARMul_CANT; | ||
| 99 | break; | ||
| 100 | case 2: | ||
| 101 | case 3: | ||
| 102 | /* CRm must be 0. Opcode_2 must be zero. */ | ||
| 103 | if ((CRm != 0) || (opcode_2 != 0)) | ||
| 104 | return ARMul_CANT; | ||
| 105 | break; | ||
| 106 | case 4: | ||
| 107 | /* Access not allowed. */ | ||
| 108 | return ARMul_CANT; | ||
| 109 | case 5: | ||
| 110 | case 6: | ||
| 111 | /* Opcode_2 must be zero. CRm must be 0. */ | ||
| 112 | if ((CRm != 0) || (opcode_2 != 0)) | ||
| 113 | return ARMul_CANT; | ||
| 114 | break; | ||
| 115 | case 7: | ||
| 116 | /* Permissable combinations: | ||
| 117 | Opcode_2 CRm | ||
| 118 | 0 5 | ||
| 119 | 0 6 | ||
| 120 | 0 7 | ||
| 121 | 1 5 | ||
| 122 | 1 6 | ||
| 123 | 1 10 | ||
| 124 | 4 10 | ||
| 125 | 5 2 | ||
| 126 | 6 5 */ | ||
| 127 | switch (opcode_2) { | ||
| 128 | default: | ||
| 129 | return ARMul_CANT; | ||
| 130 | case 6: | ||
| 131 | if (CRm != 5) | ||
| 132 | return ARMul_CANT; | ||
| 133 | break; | ||
| 134 | case 5: | ||
| 135 | if (CRm != 2) | ||
| 136 | return ARMul_CANT; | ||
| 137 | break; | ||
| 138 | case 4: | ||
| 139 | if (CRm != 10) | ||
| 140 | return ARMul_CANT; | ||
| 141 | break; | ||
| 142 | case 1: | ||
| 143 | if ((CRm != 5) && (CRm != 6) && (CRm != 10)) | ||
| 144 | return ARMul_CANT; | ||
| 145 | break; | ||
| 146 | case 0: | ||
| 147 | if ((CRm < 5) || (CRm > 7)) | ||
| 148 | return ARMul_CANT; | ||
| 149 | break; | ||
| 150 | } | ||
| 151 | break; | ||
| 152 | |||
| 153 | case 8: | ||
| 154 | /* Permissable combinations: | ||
| 155 | Opcode_2 CRm | ||
| 156 | 0 5 | ||
| 157 | 0 6 | ||
| 158 | 0 7 | ||
| 159 | 1 5 | ||
| 160 | 1 6 */ | ||
| 161 | if (opcode_2 > 1) | ||
| 162 | return ARMul_CANT; | ||
| 163 | if ((CRm < 5) || (CRm > 7)) | ||
| 164 | return ARMul_CANT; | ||
| 165 | if (opcode_2 == 1 && CRm == 7) | ||
| 166 | return ARMul_CANT; | ||
| 167 | break; | ||
| 168 | case 9: | ||
| 169 | /* Opcode_2 must be zero or one. CRm must be 1 or 2. */ | ||
| 170 | if (((CRm != 0) && (CRm != 1)) | ||
| 171 | || ((opcode_2 != 1) && (opcode_2 != 2))) | ||
| 172 | return ARMul_CANT; | ||
| 173 | break; | ||
| 174 | case 10: | ||
| 175 | /* Opcode_2 must be zero or one. CRm must be 4 or 8. */ | ||
| 176 | if (((CRm != 0) && (CRm != 1)) | ||
| 177 | || ((opcode_2 != 4) && (opcode_2 != 8))) | ||
| 178 | return ARMul_CANT; | ||
| 179 | break; | ||
| 180 | case 11: | ||
| 181 | /* Access not allowed. */ | ||
| 182 | return ARMul_CANT; | ||
| 183 | case 12: | ||
| 184 | /* Access not allowed. */ | ||
| 185 | return ARMul_CANT; | ||
| 186 | case 13: | ||
| 187 | /* Opcode_2 must be zero. CRm must be 0. */ | ||
| 188 | if ((CRm != 0) || (opcode_2 != 0)) | ||
| 189 | return ARMul_CANT; | ||
| 190 | break; | ||
| 191 | case 14: | ||
| 192 | /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */ | ||
| 193 | if (opcode_2 != 0) | ||
| 194 | return ARMul_CANT; | ||
| 195 | |||
| 196 | if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) | ||
| 197 | && (CRm != 9)) | ||
| 198 | return ARMul_CANT; | ||
| 199 | break; | ||
| 200 | case 15: | ||
| 201 | /* Opcode_2 must be zero. CRm must be 1. */ | ||
| 202 | if ((CRm != 1) || (opcode_2 != 0)) | ||
| 203 | return ARMul_CANT; | ||
| 204 | break; | ||
| 205 | default: | ||
| 206 | /* Should never happen. */ | ||
| 207 | return ARMul_CANT; | ||
| 208 | } | ||
| 209 | |||
| 210 | return ARMul_DONE; | ||
| 211 | } | ||
| 212 | |||
| 213 | /* Install co-processor instruction handlers in this routine. */ | ||
| 214 | |||
| 215 | unsigned | ||
| 216 | ARMul_CoProInit(ARMul_State * state) | ||
| 217 | { | 51 | { |
| 218 | unsigned int i; | 52 | // Initialise tham all first. |
| 219 | 53 | for (unsigned int i = 0; i < 16; i++) | |
| 220 | /* Initialise tham all first. */ | ||
| 221 | for (i = 0; i < 16; i++) | ||
| 222 | ARMul_CoProDetach(state, i); | 54 | ARMul_CoProDetach(state, i); |
| 223 | 55 | ||
| 224 | /* Install CoPro Instruction handlers here. | 56 | // Install CoPro Instruction handlers here. |
| 225 | The format is: | 57 | // The format is: |
| 226 | ARMul_CoProAttach (state, CP Number, Init routine, Exit routine | 58 | // ARMul_CoProAttach (state, CP Number, Init routine, Exit routine |
| 227 | LDC routine, STC routine, MRC routine, MCR routine, | 59 | // LDC routine, STC routine, MRC routine, MCR routine, |
| 228 | CDP routine, Read Reg routine, Write Reg routine). */ | 60 | // CDP routine, Read Reg routine, Write Reg routine). |
| 229 | if (state->is_v6) { | 61 | if (state->is_v6) { |
| 230 | ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC, | 62 | ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC, |
| 231 | VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); | 63 | VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); |
| @@ -235,57 +67,44 @@ ARMul_CoProInit(ARMul_State * state) | |||
| 235 | /*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, | 67 | /*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, |
| 236 | MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/ | 68 | MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/ |
| 237 | } | 69 | } |
| 238 | //chy 2003-09-03 do it in future!!!!???? | ||
| 239 | #if 0 | ||
| 240 | if (state->is_iWMMXt) { | ||
| 241 | ARMul_CoProAttach(state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC, | ||
| 242 | NULL, NULL, IwmmxtCDP, NULL, NULL); | ||
| 243 | 70 | ||
| 244 | ARMul_CoProAttach(state, 1, NULL, NULL, NULL, NULL, | 71 | // No handlers below here. |
| 245 | IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, | ||
| 246 | NULL); | ||
| 247 | } | ||
| 248 | #endif | ||
| 249 | /* No handlers below here. */ | ||
| 250 | 72 | ||
| 251 | /* Call all the initialisation routines. */ | 73 | // Call all the initialisation routines. |
| 252 | for (i = 0; i < 16; i++) | 74 | for (unsigned int i = 0; i < 16; i++) |
| 253 | if (state->CPInit[i]) | 75 | if (state->CPInit[i]) |
| 254 | (state->CPInit[i]) (state); | 76 | (state->CPInit[i]) (state); |
| 255 | 77 | ||
| 256 | return TRUE; | 78 | return TRUE; |
| 257 | } | 79 | } |
| 258 | 80 | ||
| 259 | /* Install co-processor finalisation routines in this routine. */ | 81 | // Install co-processor finalisation routines in this routine. |
| 260 | 82 | void ARMul_CoProExit(ARMul_State * state) | |
| 261 | void | ||
| 262 | ARMul_CoProExit(ARMul_State * state) | ||
| 263 | { | 83 | { |
| 264 | register unsigned i; | 84 | for (unsigned int i = 0; i < 16; i++) |
| 265 | |||
| 266 | for (i = 0; i < 16; i++) | ||
| 267 | if (state->CPExit[i]) | 85 | if (state->CPExit[i]) |
| 268 | (state->CPExit[i]) (state); | 86 | (state->CPExit[i]) (state); |
| 269 | 87 | ||
| 270 | for (i = 0; i < 16; i++) /* Detach all handlers. */ | 88 | // Detach all handlers. |
| 89 | for (unsigned int i = 0; i < 16; i++) | ||
| 271 | ARMul_CoProDetach(state, i); | 90 | ARMul_CoProDetach(state, i); |
| 272 | } | 91 | } |
| 273 | 92 | ||
| 274 | /* Routines to hook Co-processors into ARMulator. */ | 93 | // Routines to hook Co-processors into ARMulator. |
| 275 | 94 | ||
| 276 | void | 95 | void |
| 277 | ARMul_CoProAttach(ARMul_State * state, | 96 | ARMul_CoProAttach(ARMul_State* state, |
| 278 | unsigned number, | 97 | unsigned number, |
| 279 | ARMul_CPInits * init, | 98 | ARMul_CPInits* init, |
| 280 | ARMul_CPExits * exit, | 99 | ARMul_CPExits* exit, |
| 281 | ARMul_LDCs * ldc, | 100 | ARMul_LDCs* ldc, |
| 282 | ARMul_STCs * stc, | 101 | ARMul_STCs* stc, |
| 283 | ARMul_MRCs * mrc, | 102 | ARMul_MRCs* mrc, |
| 284 | ARMul_MCRs * mcr, | 103 | ARMul_MCRs* mcr, |
| 285 | ARMul_MRRCs * mrrc, | 104 | ARMul_MRRCs* mrrc, |
| 286 | ARMul_MCRRs * mcrr, | 105 | ARMul_MCRRs* mcrr, |
| 287 | ARMul_CDPs * cdp, | 106 | ARMul_CDPs* cdp, |
| 288 | ARMul_CPReads * read, ARMul_CPWrites * write) | 107 | ARMul_CPReads* read, ARMul_CPWrites* write) |
| 289 | { | 108 | { |
| 290 | if (init != NULL) | 109 | if (init != NULL) |
| 291 | state->CPInit[number] = init; | 110 | state->CPInit[number] = init; |
| @@ -311,8 +130,7 @@ ARMul_CPReads * read, ARMul_CPWrites * write) | |||
| 311 | state->CPWrite[number] = write; | 130 | state->CPWrite[number] = write; |
| 312 | } | 131 | } |
| 313 | 132 | ||
| 314 | void | 133 | void ARMul_CoProDetach(ARMul_State* state, unsigned number) |
| 315 | ARMul_CoProDetach(ARMul_State * state, unsigned number) | ||
| 316 | { | 134 | { |
| 317 | ARMul_CoProAttach(state, number, NULL, NULL, | 135 | ARMul_CoProAttach(state, number, NULL, NULL, |
| 318 | NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, | 136 | NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, |