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authorGravatar bunnei2015-04-02 20:21:11 -0400
committerGravatar bunnei2015-04-02 20:21:11 -0400
commite25ffaba86c5b5a79256faf80c39f7e37343701d (patch)
treee65dfe42e08d9cb1fab735c8a62ec414fabee31e /src/core/arm/dyncom
parentMerge pull request #678 from lioncash/disasm (diff)
parentdyncom: Move CP15 register writing into its own function. (diff)
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Merge pull request #677 from lioncash/cp15
dyncom: Isolate CP15 register reading and writing
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp141
1 files changed, 5 insertions, 136 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 2765cb36e..b0efd7194 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3690,10 +3690,6 @@ static int clz(unsigned int x) {
3690 return n; 3690 return n;
3691} 3691}
3692 3692
3693static bool InAPrivilegedMode(ARMul_State* core) {
3694 return (core->Mode != USER32MODE);
3695}
3696
3697unsigned InterpreterMainLoop(ARMul_State* state) { 3693unsigned InterpreterMainLoop(ARMul_State* state) {
3698 Common::Profiling::ScopeTimer timer_execute(profile_execute); 3694 Common::Profiling::ScopeTimer timer_execute(profile_execute);
3699 3695
@@ -3701,6 +3697,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
3701 #undef RS 3697 #undef RS
3702 3698
3703 #define CRn inst_cream->crn 3699 #define CRn inst_cream->crn
3700 #define OPCODE_1 inst_cream->opcode_1
3704 #define OPCODE_2 inst_cream->opcode_2 3701 #define OPCODE_2 inst_cream->opcode_2
3705 #define CRm inst_cream->crm 3702 #define CRm inst_cream->crm
3706 #define CP15_REG(n) cpu->CP15[CP15(n)] 3703 #define CP15_REG(n) cpu->CP15[CP15(n)]
@@ -4764,94 +4761,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4764 if (inst_cream->Rd == 15) { 4761 if (inst_cream->Rd == 15) {
4765 DEBUG_MSG; 4762 DEBUG_MSG;
4766 } else { 4763 } else {
4767 if (inst_cream->cp_num == 15) { 4764 if (inst_cream->cp_num == 15)
4768 if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { 4765 WriteCP15Register(cpu, RD, CRn, OPCODE_1, CRm, OPCODE_2);
4769 CP15_REG(CP15_CONTROL) = RD;
4770 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
4771 CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
4772 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
4773 CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
4774 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
4775 CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
4776 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
4777 CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
4778 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
4779 CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
4780 } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
4781 CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
4782 } else if(CRn == MMU_CACHE_OPS){
4783 //LOG_WARNING(Core_ARM11, "cache operations have not implemented.");
4784 } else if(CRn == MMU_TLB_OPS){
4785 switch (CRm) {
4786 case 5: // ITLB
4787 switch(OPCODE_2) {
4788 case 0: // Invalidate all
4789 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate all");
4790 break;
4791 case 1: // Invalidate by MVA
4792 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by mva");
4793 break;
4794 case 2: // Invalidate by asid
4795 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by asid");
4796 break;
4797 default:
4798 break;
4799 }
4800
4801 break;
4802 case 6: // DTLB
4803 switch(OPCODE_2){
4804 case 0: // Invalidate all
4805 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate all");
4806 break;
4807 case 1: // Invalidate by MVA
4808 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by mva");
4809 break;
4810 case 2: // Invalidate by asid
4811 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by asid");
4812 break;
4813 default:
4814 break;
4815 }
4816 break;
4817 case 7: // UNIFILED TLB
4818 switch(OPCODE_2){
4819 case 0: // invalidate all
4820 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate all");
4821 break;
4822 case 1: // Invalidate by MVA
4823 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by mva");
4824 break;
4825 case 2: // Invalidate by asid
4826 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by asid");
4827 break;
4828 default:
4829 break;
4830 }
4831 break;
4832 default:
4833 break;
4834 }
4835 } else if(CRn == MMU_PID) {
4836 if(OPCODE_2 == 0) {
4837 CP15_REG(CP15_PID) = RD;
4838 } else if(OPCODE_2 == 1) {
4839 CP15_REG(CP15_CONTEXT_ID) = RD;
4840 } else if (OPCODE_2 == 2) {
4841 CP15_REG(CP15_THREAD_UPRW) = RD;
4842 } else if(OPCODE_2 == 3) {
4843 if (InAPrivilegedMode(cpu))
4844 CP15_REG(CP15_THREAD_URO) = RD;
4845 } else if (OPCODE_2 == 4) {
4846 if (InAPrivilegedMode(cpu))
4847 CP15_REG(CP15_THREAD_PRW) = RD;
4848 } else {
4849 LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn);
4850 }
4851 } else {
4852 LOG_ERROR(Core_ARM11, "mcr CRn=%d, CRm=%d OP2=%d is not implemented", CRn, CRm, OPCODE_2);
4853 }
4854 }
4855 } 4766 }
4856 } 4767 }
4857 cpu->Reg[15] += GET_INST_SIZE(cpu); 4768 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -4926,50 +4837,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4926 CITRA_IGNORE_EXIT(-1); 4837 CITRA_IGNORE_EXIT(-1);
4927 goto END; 4838 goto END;
4928 } else { 4839 } else {
4929 if (inst_cream->cp_num == 15) { 4840 if (inst_cream->cp_num == 15)
4930 if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { 4841 RD = ReadCP15Register(cpu, CRn, OPCODE_1, CRm, OPCODE_2);
4931 RD = cpu->CP15[CP15(CP15_MAIN_ID)];
4932 } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
4933 RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
4934 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
4935 RD = cpu->CP15[CP15(CP15_CONTROL)];
4936 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
4937 RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
4938 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
4939 RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
4940 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
4941 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
4942 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
4943 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
4944 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
4945 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
4946 } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
4947 RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
4948 } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
4949 RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
4950 } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
4951 RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
4952 } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
4953 RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
4954 } else if (CRn == 13) {
4955 if(OPCODE_2 == 0) {
4956 RD = CP15_REG(CP15_PID);
4957 } else if(OPCODE_2 == 1) {
4958 RD = CP15_REG(CP15_CONTEXT_ID);
4959 } else if (OPCODE_2 == 2) {
4960 RD = CP15_REG(CP15_THREAD_UPRW);
4961 } else if(OPCODE_2 == 3) {
4962 RD = Memory::KERNEL_MEMORY_VADDR;
4963 } else if (OPCODE_2 == 4) {
4964 if (InAPrivilegedMode(cpu))
4965 RD = CP15_REG(CP15_THREAD_PRW);
4966 } else {
4967 LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn);
4968 }
4969 } else {
4970 LOG_ERROR(Core_ARM11, "mrc CRn=%d, CRm=%d, OP2=%d is not implemented", CRn, CRm, OPCODE_2);
4971 }
4972 }
4973 } 4842 }
4974 } 4843 }
4975 cpu->Reg[15] += GET_INST_SIZE(cpu); 4844 cpu->Reg[15] += GET_INST_SIZE(cpu);
HIC SVNT DRACONES