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| author | 2017-05-07 15:21:35 -0700 | |
|---|---|---|
| committer | 2017-05-07 15:33:46 -0700 | |
| commit | d97b9775409e05ffba8a78632bd41863570e9830 (patch) | |
| tree | 2bed3e545cb8b660d695763ce27dc3069847d7b1 /src/core/arm/dyncom | |
| parent | Dyncom: Tweak types and log formatting (diff) | |
| download | yuzu-d97b9775409e05ffba8a78632bd41863570e9830.tar.gz yuzu-d97b9775409e05ffba8a78632bd41863570e9830.tar.xz yuzu-d97b9775409e05ffba8a78632bd41863570e9830.zip | |
Dyncom: Remove disassembler code
Had licensing issue around it, in addition to several bugs.
Closes #1632, #1280
Diffstat (limited to 'src/core/arm/dyncom')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 8073bb705..f4fbb8d04 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -10,7 +10,6 @@ | |||
| 10 | #include "common/common_types.h" | 10 | #include "common/common_types.h" |
| 11 | #include "common/logging/log.h" | 11 | #include "common/logging/log.h" |
| 12 | #include "common/microprofile.h" | 12 | #include "common/microprofile.h" |
| 13 | #include "core/arm/disassembler/arm_disasm.h" | ||
| 14 | #include "core/arm/dyncom/arm_dyncom_dec.h" | 13 | #include "core/arm/dyncom/arm_dyncom_dec.h" |
| 15 | #include "core/arm/dyncom/arm_dyncom_interpreter.h" | 14 | #include "core/arm/dyncom/arm_dyncom_interpreter.h" |
| 16 | #include "core/arm/dyncom/arm_dyncom_run.h" | 15 | #include "core/arm/dyncom/arm_dyncom_run.h" |
| @@ -828,10 +827,8 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons | |||
| 828 | 827 | ||
| 829 | int idx; | 828 | int idx; |
| 830 | if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { | 829 | if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { |
| 831 | std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); | 830 | LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32, |
| 832 | LOG_ERROR(Core_ARM11, | 831 | phys_addr, inst); |
| 833 | "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %s [%08" PRIX32 "]", | ||
| 834 | phys_addr, disasm.c_str(), inst); | ||
| 835 | LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr, | 832 | LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr, |
| 836 | cpu->TFlag, cpu->Reg[15]); | 833 | cpu->TFlag, cpu->Reg[15]); |
| 837 | CITRA_IGNORE_EXIT(-1); | 834 | CITRA_IGNORE_EXIT(-1); |