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authorGravatar Yuri Kunde Schlesner2016-09-21 11:29:48 -0700
committerGravatar GitHub2016-09-21 11:29:48 -0700
commitd5d2ca8058a0f1c00ab7ca9fe2c058ba47546c0a (patch)
tree8a22ca73ff838f3f0090b29a548ae81087fc90ed /src/core/arm/dyncom
parentREADME: Specify master branch for Travis CI badge (diff)
parentFix Travis clang-format check (diff)
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Merge pull request #2086 from linkmauve/clang-format
Add clang-format as part of our {commit,travis}-time checks
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp12
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp14
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h7
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp6292
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp372
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.h6
-rw-r--r--src/core/arm/dyncom/arm_dyncom_trans.cpp1813
-rw-r--r--src/core/arm/dyncom/arm_dyncom_trans.h33
9 files changed, 4277 insertions, 4274 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index d84917529..34c7f945e 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -4,16 +4,13 @@
4 4
5#include <cstring> 5#include <cstring>
6#include <memory> 6#include <memory>
7
8#include "core/arm/skyeye_common/armstate.h"
9#include "core/arm/skyeye_common/armsupp.h"
10#include "core/arm/skyeye_common/vfp/vfp.h"
11
12#include "core/arm/dyncom/arm_dyncom.h" 7#include "core/arm/dyncom/arm_dyncom.h"
13#include "core/arm/dyncom/arm_dyncom_interpreter.h" 8#include "core/arm/dyncom/arm_dyncom_interpreter.h"
14#include "core/arm/dyncom/arm_dyncom_run.h" 9#include "core/arm/dyncom/arm_dyncom_run.h"
15#include "core/arm/dyncom/arm_dyncom_trans.h" 10#include "core/arm/dyncom/arm_dyncom_trans.h"
16 11#include "core/arm/skyeye_common/armstate.h"
12#include "core/arm/skyeye_common/armsupp.h"
13#include "core/arm/skyeye_common/vfp/vfp.h"
17#include "core/core.h" 14#include "core/core.h"
18#include "core/core_timing.h" 15#include "core/core_timing.h"
19 16
@@ -21,8 +18,7 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
21 state = std::make_unique<ARMul_State>(initial_mode); 18 state = std::make_unique<ARMul_State>(initial_mode);
22} 19}
23 20
24ARM_DynCom::~ARM_DynCom() { 21ARM_DynCom::~ARM_DynCom() {}
25}
26 22
27void ARM_DynCom::ClearInstructionCache() { 23void ARM_DynCom::ClearInstructionCache() {
28 state->instruction_cache.clear(); 24 state->instruction_cache.clear();
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 70f71a828..65db1f0f9 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -5,9 +5,7 @@
5#pragma once 5#pragma once
6 6
7#include <memory> 7#include <memory>
8
9#include "common/common_types.h" 8#include "common/common_types.h"
10
11#include "core/arm/arm_interface.h" 9#include "core/arm/arm_interface.h"
12#include "core/arm/skyeye_common/arm_regformat.h" 10#include "core/arm/skyeye_common/arm_regformat.h"
13#include "core/arm/skyeye_common/armstate.h" 11#include "core/arm/skyeye_common/armstate.h"
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 247d379e3..64dcaae08 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -5,6 +5,7 @@
5#include "core/arm/dyncom/arm_dyncom_dec.h" 5#include "core/arm/dyncom/arm_dyncom_dec.h"
6#include "core/arm/skyeye_common/armsupp.h" 6#include "core/arm/skyeye_common/armsupp.h"
7 7
8// clang-format off
8const InstructionSetEncodingItem arm_instruction[] = { 9const InstructionSetEncodingItem arm_instruction[] = {
9 { "vmla", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }}, 10 { "vmla", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0 }},
10 { "vmls", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }}, 11 { "vmls", 5, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 1, 4, 4, 0 }},
@@ -206,6 +207,7 @@ const InstructionSetEncodingItem arm_instruction[] = {
206 { "bbl", 1, 0, { 25, 27, 0x00000005 }}, 207 { "bbl", 1, 0, { 25, 27, 0x00000005 }},
207}; 208};
208 209
210
209const InstructionSetEncodingItem arm_exclusion_code[] = { 211const InstructionSetEncodingItem arm_exclusion_code[] = {
210 { "vmla", 0, ARMVFP2, { 0 }}, 212 { "vmla", 0, ARMVFP2, { 0 }},
211 { "vmls", 0, ARMVFP2, { 0 }}, 213 { "vmls", 0, ARMVFP2, { 0 }},
@@ -411,6 +413,7 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
411 { "blx_1_thumb", 0, INVALID, { 0 }}, // Should be located at table[-2] 413 { "blx_1_thumb", 0, INVALID, { 0 }}, // Should be located at table[-2]
412 { "invalid", 0, INVALID, { 0 }} 414 { "invalid", 0, INVALID, { 0 }}
413}; 415};
416// clang-format on
414 417
415ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { 418ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
416 int n = 0; 419 int n = 0;
@@ -427,12 +430,15 @@ ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
427 continue; 430 continue;
428 431
429 while (n) { 432 while (n) {
430 if (arm_instruction[i].content[base + 1] == 31 && arm_instruction[i].content[base] == 0) { 433 if (arm_instruction[i].content[base + 1] == 31 &&
434 arm_instruction[i].content[base] == 0) {
431 // clrex 435 // clrex
432 if (instr != arm_instruction[i].content[base + 2]) { 436 if (instr != arm_instruction[i].content[base + 2]) {
433 break; 437 break;
434 } 438 }
435 } else if (BITS(instr, arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { 439 } else if (BITS(instr, arm_instruction[i].content[base],
440 arm_instruction[i].content[base + 1]) !=
441 arm_instruction[i].content[base + 2]) {
436 break; 442 break;
437 } 443 }
438 base += 3; 444 base += 3;
@@ -448,7 +454,9 @@ ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
448 if (n != 0) { 454 if (n != 0) {
449 base = 0; 455 base = 0;
450 while (n) { 456 while (n) {
451 if (BITS(instr, arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { 457 if (BITS(instr, arm_exclusion_code[i].content[base],
458 arm_exclusion_code[i].content[base + 1]) !=
459 arm_exclusion_code[i].content[base + 2]) {
452 break; 460 break;
453 } 461 }
454 base += 3; 462 base += 3;
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index d7170e0fc..2fb7ac37c 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -6,15 +6,12 @@
6 6
7#include "common/common_types.h" 7#include "common/common_types.h"
8 8
9enum class ARMDecodeStatus { 9enum class ARMDecodeStatus { SUCCESS, FAILURE };
10 SUCCESS,
11 FAILURE
12};
13 10
14ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx); 11ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);
15 12
16struct InstructionSetEncodingItem { 13struct InstructionSetEncodingItem {
17 const char *name; 14 const char* name;
18 int attribute_value; 15 int attribute_value;
19 int version; 16 int version;
20 u32 content[21]; 17 u32 content[21];
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index c8d45c6db..7b8616702 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -6,34 +6,31 @@
6 6
7#include <algorithm> 7#include <algorithm>
8#include <cstdio> 8#include <cstdio>
9
10#include "common/common_types.h" 9#include "common/common_types.h"
11#include "common/logging/log.h" 10#include "common/logging/log.h"
12#include "common/microprofile.h" 11#include "common/microprofile.h"
13
14#include "core/memory.h"
15#include "core/hle/svc.h"
16#include "core/arm/disassembler/arm_disasm.h" 12#include "core/arm/disassembler/arm_disasm.h"
17#include "core/arm/dyncom/arm_dyncom_dec.h" 13#include "core/arm/dyncom/arm_dyncom_dec.h"
18#include "core/arm/dyncom/arm_dyncom_interpreter.h" 14#include "core/arm/dyncom/arm_dyncom_interpreter.h"
15#include "core/arm/dyncom/arm_dyncom_run.h"
19#include "core/arm/dyncom/arm_dyncom_thumb.h" 16#include "core/arm/dyncom/arm_dyncom_thumb.h"
20#include "core/arm/dyncom/arm_dyncom_trans.h" 17#include "core/arm/dyncom/arm_dyncom_trans.h"
21#include "core/arm/dyncom/arm_dyncom_run.h"
22#include "core/arm/skyeye_common/armstate.h" 18#include "core/arm/skyeye_common/armstate.h"
23#include "core/arm/skyeye_common/armsupp.h" 19#include "core/arm/skyeye_common/armsupp.h"
24#include "core/arm/skyeye_common/vfp/vfp.h" 20#include "core/arm/skyeye_common/vfp/vfp.h"
25
26#include "core/gdbstub/gdbstub.h" 21#include "core/gdbstub/gdbstub.h"
22#include "core/hle/svc.h"
23#include "core/memory.h"
27 24
28#define RM BITS(sht_oper, 0, 3) 25#define RM BITS(sht_oper, 0, 3)
29#define RS BITS(sht_oper, 8, 11) 26#define RS BITS(sht_oper, 8, 11)
30 27
31#define glue(x, y) x ## y 28#define glue(x, y) x##y
32#define DPO(s) glue(DataProcessingOperands, s) 29#define DPO(s) glue(DataProcessingOperands, s)
33#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i)) 30#define ROTATE_RIGHT(n, i, l) ((n << (l - i)) | (n >> i))
34#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i)) 31#define ROTATE_LEFT(n, i, l) ((n >> (l - i)) | (n << i))
35#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32) 32#define ROTATE_RIGHT_32(n, i) ROTATE_RIGHT(n, i, 32)
36#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32) 33#define ROTATE_LEFT_32(n, i) ROTATE_LEFT(n, i, 32)
37 34
38static bool CondPassed(const ARMul_State* cpu, unsigned int cond) { 35static bool CondPassed(const ARMul_State* cpu, unsigned int cond) {
39 const bool n_flag = cpu->NFlag != 0; 36 const bool n_flag = cpu->NFlag != 0;
@@ -232,17 +229,19 @@ static unsigned int DPO(RotateRightByRegister)(ARMul_State* cpu, unsigned int sh
232 return shifter_operand; 229 return shifter_operand;
233} 230}
234 231
235#define DEBUG_MSG LOG_DEBUG(Core_ARM11, "inst is %x", inst); CITRA_IGNORE_EXIT(0) 232#define DEBUG_MSG \
233 LOG_DEBUG(Core_ARM11, "inst is %x", inst); \
234 CITRA_IGNORE_EXIT(0)
236 235
237#define LnSWoUB(s) glue(LnSWoUB, s) 236#define LnSWoUB(s) glue(LnSWoUB, s)
238#define MLnS(s) glue(MLnS, s) 237#define MLnS(s) glue(MLnS, s)
239#define LdnStM(s) glue(LdnStM, s) 238#define LdnStM(s) glue(LdnStM, s)
240 239
241#define W_BIT BIT(inst, 21) 240#define W_BIT BIT(inst, 21)
242#define U_BIT BIT(inst, 23) 241#define U_BIT BIT(inst, 23)
243#define I_BIT BIT(inst, 25) 242#define I_BIT BIT(inst, 25)
244#define P_BIT BIT(inst, 24) 243#define P_BIT BIT(inst, 24)
245#define OFFSET_12 BITS(inst, 0, 11) 244#define OFFSET_12 BITS(inst, 0, 11)
246 245
247static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 246static void LnSWoUB(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
248 unsigned int Rn = BITS(inst, 16, 19); 247 unsigned int Rn = BITS(inst, 16, 19);
@@ -271,7 +270,8 @@ static void LnSWoUB(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigne
271 virt_addr = addr; 270 virt_addr = addr;
272} 271}
273 272
274static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 273static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst,
274 unsigned int& virt_addr) {
275 unsigned int Rn = BITS(inst, 16, 19); 275 unsigned int Rn = BITS(inst, 16, 19);
276 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); 276 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
277 277
@@ -283,7 +283,8 @@ static void LnSWoUB(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, u
283 virt_addr = addr; 283 virt_addr = addr;
284} 284}
285 285
286static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 286static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst,
287 unsigned int& virt_addr) {
287 unsigned int Rn = BITS(inst, 16, 19); 288 unsigned int Rn = BITS(inst, 16, 19);
288 unsigned int addr; 289 unsigned int addr;
289 290
@@ -301,7 +302,7 @@ static void LnSWoUB(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, un
301static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 302static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
302 unsigned int addr; 303 unsigned int addr;
303 unsigned int Rn = BITS(inst, 16, 19); 304 unsigned int Rn = BITS(inst, 16, 19);
304 unsigned int Rm = BITS(inst, 0, 3); 305 unsigned int Rm = BITS(inst, 0, 3);
305 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 306 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
306 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 307 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
307 308
@@ -316,7 +317,8 @@ static void MLnS(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsign
316 cpu->Reg[Rn] = addr; 317 cpu->Reg[Rn] = addr;
317} 318}
318 319
319static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 320static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst,
321 unsigned int& virt_addr) {
320 unsigned int Rn = BITS(inst, 16, 19); 322 unsigned int Rn = BITS(inst, 16, 19);
321 unsigned int Rm = BITS(inst, 0, 3); 323 unsigned int Rm = BITS(inst, 0, 3);
322 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 324 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
@@ -335,7 +337,8 @@ static void LnSWoUB(RegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, uns
335 } 337 }
336} 338}
337 339
338static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 340static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int inst,
341 unsigned int& virt_addr) {
339 unsigned int shift = BITS(inst, 5, 6); 342 unsigned int shift = BITS(inst, 5, 6);
340 unsigned int shift_imm = BITS(inst, 7, 11); 343 unsigned int shift_imm = BITS(inst, 7, 11);
341 unsigned int Rn = BITS(inst, 16, 19); 344 unsigned int Rn = BITS(inst, 16, 19);
@@ -386,7 +389,8 @@ static void LnSWoUB(ScaledRegisterPreIndexed)(ARMul_State* cpu, unsigned int ins
386 cpu->Reg[Rn] = addr; 389 cpu->Reg[Rn] = addr;
387} 390}
388 391
389static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 392static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int inst,
393 unsigned int& virt_addr) {
390 unsigned int shift = BITS(inst, 5, 6); 394 unsigned int shift = BITS(inst, 5, 6);
391 unsigned int shift_imm = BITS(inst, 7, 11); 395 unsigned int shift_imm = BITS(inst, 7, 11);
392 unsigned int Rn = BITS(inst, 16, 19); 396 unsigned int Rn = BITS(inst, 16, 19);
@@ -435,9 +439,10 @@ static void LnSWoUB(ScaledRegisterPostIndexed)(ARMul_State* cpu, unsigned int in
435 } 439 }
436} 440}
437 441
438static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 442static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst,
443 unsigned int& virt_addr) {
439 unsigned int Rn = BITS(inst, 16, 19); 444 unsigned int Rn = BITS(inst, 16, 19);
440 unsigned int Rm = BITS(inst, 0, 3); 445 unsigned int Rm = BITS(inst, 0, 3);
441 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 446 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
442 447
443 virt_addr = CHECK_READ_REG15_WA(cpu, Rn); 448 virt_addr = CHECK_READ_REG15_WA(cpu, Rn);
@@ -454,7 +459,7 @@ static void LnSWoUB(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, un
454static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 459static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
455 unsigned int immedL = BITS(inst, 0, 3); 460 unsigned int immedL = BITS(inst, 0, 3);
456 unsigned int immedH = BITS(inst, 8, 11); 461 unsigned int immedH = BITS(inst, 8, 11);
457 unsigned int Rn = BITS(inst, 16, 19); 462 unsigned int Rn = BITS(inst, 16, 19);
458 unsigned int addr; 463 unsigned int addr;
459 464
460 unsigned int offset_8 = (immedH << 4) | immedL; 465 unsigned int offset_8 = (immedH << 4) | immedL;
@@ -470,7 +475,7 @@ static void MLnS(ImmediateOffset)(ARMul_State* cpu, unsigned int inst, unsigned
470static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 475static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) {
471 unsigned int addr; 476 unsigned int addr;
472 unsigned int Rn = BITS(inst, 16, 19); 477 unsigned int Rn = BITS(inst, 16, 19);
473 unsigned int Rm = BITS(inst, 0, 3); 478 unsigned int Rm = BITS(inst, 0, 3);
474 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 479 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
475 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 480 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
476 481
@@ -482,10 +487,11 @@ static void MLnS(RegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned i
482 virt_addr = addr; 487 virt_addr = addr;
483} 488}
484 489
485static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 490static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst,
486 unsigned int Rn = BITS(inst, 16, 19); 491 unsigned int& virt_addr) {
487 unsigned int immedH = BITS(inst, 8, 11); 492 unsigned int Rn = BITS(inst, 16, 19);
488 unsigned int immedL = BITS(inst, 0, 3); 493 unsigned int immedH = BITS(inst, 8, 11);
494 unsigned int immedL = BITS(inst, 0, 3);
489 unsigned int addr; 495 unsigned int addr;
490 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 496 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
491 unsigned int offset_8 = (immedH << 4) | immedL; 497 unsigned int offset_8 = (immedH << 4) | immedL;
@@ -501,10 +507,11 @@ static void MLnS(ImmediatePreIndexed)(ARMul_State* cpu, unsigned int inst, unsig
501 cpu->Reg[Rn] = addr; 507 cpu->Reg[Rn] = addr;
502} 508}
503 509
504static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 510static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst,
505 unsigned int Rn = BITS(inst, 16, 19); 511 unsigned int& virt_addr) {
506 unsigned int immedH = BITS(inst, 8, 11); 512 unsigned int Rn = BITS(inst, 16, 19);
507 unsigned int immedL = BITS(inst, 0, 3); 513 unsigned int immedH = BITS(inst, 8, 11);
514 unsigned int immedL = BITS(inst, 0, 3);
508 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 515 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
509 516
510 virt_addr = rn; 517 virt_addr = rn;
@@ -520,9 +527,10 @@ static void MLnS(ImmediatePostIndexed)(ARMul_State* cpu, unsigned int inst, unsi
520 } 527 }
521} 528}
522 529
523static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 530static void MLnS(RegisterPostIndexed)(ARMul_State* cpu, unsigned int inst,
531 unsigned int& virt_addr) {
524 unsigned int Rn = BITS(inst, 16, 19); 532 unsigned int Rn = BITS(inst, 16, 19);
525 unsigned int Rm = BITS(inst, 0, 3); 533 unsigned int Rm = BITS(inst, 0, 3);
526 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 534 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
527 535
528 virt_addr = CHECK_READ_REG15_WA(cpu, Rn); 536 virt_addr = CHECK_READ_REG15_WA(cpu, Rn);
@@ -541,7 +549,8 @@ static void LdnStM(DecrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne
541 int count = 0; 549 int count = 0;
542 550
543 while (i) { 551 while (i) {
544 if (i & 1) count++; 552 if (i & 1)
553 count++;
545 i = i >> 1; 554 i = i >> 1;
546 } 555 }
547 556
@@ -557,7 +566,8 @@ static void LdnStM(IncrementBefore)(ARMul_State* cpu, unsigned int inst, unsigne
557 int count = 0; 566 int count = 0;
558 567
559 while (i) { 568 while (i) {
560 if (i & 1) count++; 569 if (i & 1)
570 count++;
561 i = i >> 1; 571 i = i >> 1;
562 } 572 }
563 573
@@ -572,8 +582,9 @@ static void LdnStM(IncrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned
572 unsigned int i = BITS(inst, 0, 15); 582 unsigned int i = BITS(inst, 0, 15);
573 int count = 0; 583 int count = 0;
574 584
575 while(i) { 585 while (i) {
576 if (i & 1) count++; 586 if (i & 1)
587 count++;
577 i = i >> 1; 588 i = i >> 1;
578 } 589 }
579 590
@@ -587,8 +598,9 @@ static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned
587 unsigned int Rn = BITS(inst, 16, 19); 598 unsigned int Rn = BITS(inst, 16, 19);
588 unsigned int i = BITS(inst, 0, 15); 599 unsigned int i = BITS(inst, 0, 15);
589 int count = 0; 600 int count = 0;
590 while(i) { 601 while (i) {
591 if(i & 1) count++; 602 if (i & 1)
603 count++;
592 i = i >> 1; 604 i = i >> 1;
593 } 605 }
594 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 606 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
@@ -601,7 +613,8 @@ static void LdnStM(DecrementAfter)(ARMul_State* cpu, unsigned int inst, unsigned
601 } 613 }
602} 614}
603 615
604static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr) { 616static void LnSWoUB(ScaledRegisterOffset)(ARMul_State* cpu, unsigned int inst,
617 unsigned int& virt_addr) {
605 unsigned int shift = BITS(inst, 5, 6); 618 unsigned int shift = BITS(inst, 5, 6);
606 unsigned int shift_imm = BITS(inst, 7, 11); 619 unsigned int shift_imm = BITS(inst, 7, 11);
607 unsigned int Rn = BITS(inst, 16, 19); 620 unsigned int Rn = BITS(inst, 16, 19);
@@ -693,17 +706,23 @@ get_addr_fp_t GetAddressingOp(unsigned int inst) {
693 return LnSWoUB(RegisterPostIndexed); 706 return LnSWoUB(RegisterPostIndexed);
694 } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) { 707 } else if (BITS(inst, 24, 27) == 6 && BIT(inst, 21) == 0 && BIT(inst, 4) == 0) {
695 return LnSWoUB(ScaledRegisterPostIndexed); 708 return LnSWoUB(ScaledRegisterPostIndexed);
696 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 709 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 &&
710 BIT(inst, 4) == 1) {
697 return MLnS(ImmediateOffset); 711 return MLnS(ImmediateOffset);
698 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 712 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 &&
713 BIT(inst, 4) == 1) {
699 return MLnS(RegisterOffset); 714 return MLnS(RegisterOffset);
700 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 715 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 3 && BIT(inst, 7) == 1 &&
716 BIT(inst, 4) == 1) {
701 return MLnS(ImmediatePreIndexed); 717 return MLnS(ImmediatePreIndexed);
702 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 718 } else if (BITS(inst, 24, 27) == 1 && BITS(inst, 21, 22) == 1 && BIT(inst, 7) == 1 &&
719 BIT(inst, 4) == 1) {
703 return MLnS(RegisterPreIndexed); 720 return MLnS(RegisterPreIndexed);
704 } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 721 } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 2 && BIT(inst, 7) == 1 &&
722 BIT(inst, 4) == 1) {
705 return MLnS(ImmediatePostIndexed); 723 return MLnS(ImmediatePostIndexed);
706 } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 && BIT(inst, 4) == 1) { 724 } else if (BITS(inst, 24, 27) == 0 && BITS(inst, 21, 22) == 0 && BIT(inst, 7) == 1 &&
725 BIT(inst, 4) == 1) {
707 return MLnS(RegisterPostIndexed); 726 return MLnS(RegisterPostIndexed);
708 } else if (BITS(inst, 23, 27) == 0x11) { 727 } else if (BITS(inst, 23, 27) == 0x11) {
709 return LdnStM(IncrementAfter); 728 return LdnStM(IncrementAfter);
@@ -732,14 +751,12 @@ get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst) {
732 return nullptr; 751 return nullptr;
733} 752}
734 753
735enum { 754enum { FETCH_SUCCESS, FETCH_FAILURE };
736 FETCH_SUCCESS,
737 FETCH_FAILURE
738};
739 755
740static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size, ARM_INST_PTR* ptr_inst_base) { 756static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_inst, u32* inst_size,
757 ARM_INST_PTR* ptr_inst_base) {
741 // Check if in Thumb mode 758 // Check if in Thumb mode
742 ThumbDecodeStatus ret = TranslateThumbInstruction (addr, inst, arm_inst, inst_size); 759 ThumbDecodeStatus ret = TranslateThumbInstruction(addr, inst, arm_inst, inst_size);
743 if (ret == ThumbDecodeStatus::BRANCH) { 760 if (ret == ThumbDecodeStatus::BRANCH) {
744 int inst_index; 761 int inst_index;
745 int table_length = arm_instruction_trans_len; 762 int table_length = arm_instruction_trans_len;
@@ -748,7 +765,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
748 switch ((tinstr & 0xF800) >> 11) { 765 switch ((tinstr & 0xF800) >> 11) {
749 case 26: 766 case 26:
750 case 27: 767 case 27:
751 if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)){ 768 if (((tinstr & 0x0F00) != 0x0E00) && ((tinstr & 0x0F00) != 0x0F00)) {
752 inst_index = table_length - 4; 769 inst_index = table_length - 4;
753 *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index); 770 *ptr_inst_base = arm_instruction_trans[inst_index](tinstr, inst_index);
754 } else { 771 } else {
@@ -785,21 +802,21 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
785 return ret; 802 return ret;
786} 803}
787 804
788enum { 805enum { KEEP_GOING, FETCH_EXCEPTION };
789 KEEP_GOING,
790 FETCH_EXCEPTION
791};
792 806
793MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64)); 807MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
794 808
795static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, ARM_INST_PTR& inst_base) { 809static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
810 ARM_INST_PTR& inst_base) {
796 unsigned int inst_size = 4; 811 unsigned int inst_size = 4;
797 unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC); 812 unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
798 813
799 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction 814 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
815 // instruction
800 if (cpu->TFlag) { 816 if (cpu->TFlag) {
801 u32 arm_inst; 817 u32 arm_inst;
802 ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base); 818 ThumbDecodeStatus state =
819 DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
803 820
804 // We have translated the Thumb branch instruction in the Thumb decoder 821 // We have translated the Thumb branch instruction in the Thumb decoder
805 if (state == ThumbDecodeStatus::BRANCH) { 822 if (state == ThumbDecodeStatus::BRANCH) {
@@ -811,8 +828,10 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
811 int idx; 828 int idx;
812 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { 829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
813 std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); 830 std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
814 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst); 831 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr,
815 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]); 832 disasm.c_str(), inst);
833 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag,
834 cpu->Reg[15]);
816 CITRA_IGNORE_EXIT(-1); 835 CITRA_IGNORE_EXIT(-1);
817 } 836 }
818 inst_base = arm_instruction_trans[idx](inst, idx); 837 inst_base = arm_instruction_trans[idx](inst, idx);
@@ -875,12 +894,25 @@ static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr)
875 894
876static int clz(unsigned int x) { 895static int clz(unsigned int x) {
877 int n; 896 int n;
878 if (x == 0) return (32); 897 if (x == 0)
898 return (32);
879 n = 1; 899 n = 1;
880 if ((x >> 16) == 0) { n = n + 16; x = x << 16;} 900 if ((x >> 16) == 0) {
881 if ((x >> 24) == 0) { n = n + 8; x = x << 8;} 901 n = n + 16;
882 if ((x >> 28) == 0) { n = n + 4; x = x << 4;} 902 x = x << 16;
883 if ((x >> 30) == 0) { n = n + 2; x = x << 2;} 903 }
904 if ((x >> 24) == 0) {
905 n = n + 8;
906 x = x << 8;
907 }
908 if ((x >> 28) == 0) {
909 n = n + 4;
910 x = x << 4;
911 }
912 if ((x >> 30) == 0) {
913 n = n + 2;
914 x = x << 2;
915 }
884 n = n - (x >> 31); 916 n = n - (x >> 31);
885 return n; 917 return n;
886} 918}
@@ -892,310 +924,698 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
892 924
893 GDBStub::BreakpointAddress breakpoint_data; 925 GDBStub::BreakpointAddress breakpoint_data;
894 926
895 #undef RM 927#undef RM
896 #undef RS 928#undef RS
897 929
898 #define CRn inst_cream->crn 930#define CRn inst_cream->crn
899 #define OPCODE_1 inst_cream->opcode_1 931#define OPCODE_1 inst_cream->opcode_1
900 #define OPCODE_2 inst_cream->opcode_2 932#define OPCODE_2 inst_cream->opcode_2
901 #define CRm inst_cream->crm 933#define CRm inst_cream->crm
902 #define RD cpu->Reg[inst_cream->Rd] 934#define RD cpu->Reg[inst_cream->Rd]
903 #define RD2 cpu->Reg[inst_cream->Rd + 1] 935#define RD2 cpu->Reg[inst_cream->Rd + 1]
904 #define RN cpu->Reg[inst_cream->Rn] 936#define RN cpu->Reg[inst_cream->Rn]
905 #define RM cpu->Reg[inst_cream->Rm] 937#define RM cpu->Reg[inst_cream->Rm]
906 #define RS cpu->Reg[inst_cream->Rs] 938#define RS cpu->Reg[inst_cream->Rs]
907 #define RDHI cpu->Reg[inst_cream->RdHi] 939#define RDHI cpu->Reg[inst_cream->RdHi]
908 #define RDLO cpu->Reg[inst_cream->RdLo] 940#define RDLO cpu->Reg[inst_cream->RdLo]
909 #define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4) 941#define LINK_RTN_ADDR (cpu->Reg[14] = cpu->Reg[15] + 4)
910 #define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24) 942#define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24)
911 #define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand) 943#define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand)
912 944
913 #define FETCH_INST if (inst_base->br != TransExtData::NON_BRANCH) goto DISPATCH; \ 945#define FETCH_INST \
914 inst_base = (arm_inst *)&trans_cache_buf[ptr] 946 if (inst_base->br != TransExtData::NON_BRANCH) \
915 947 goto DISPATCH; \
916 #define INC_PC(l) ptr += sizeof(arm_inst) + l 948 inst_base = (arm_inst*)&trans_cache_buf[ptr]
917 #define INC_PC_STUB ptr += sizeof(arm_inst) 949
918 950#define INC_PC(l) ptr += sizeof(arm_inst) + l
919#define GDB_BP_CHECK \ 951#define INC_PC_STUB ptr += sizeof(arm_inst)
920 cpu->Cpsr &= ~(1 << 5); \ 952
921 cpu->Cpsr |= cpu->TFlag << 5; \ 953#define GDB_BP_CHECK \
922 if (GDBStub::g_server_enabled) { \ 954 cpu->Cpsr &= ~(1 << 5); \
923 if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && PC == breakpoint_data.address)) { \ 955 cpu->Cpsr |= cpu->TFlag << 5; \
924 GDBStub::Break(); \ 956 if (GDBStub::g_server_enabled) { \
925 goto END; \ 957 if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && \
926 } \ 958 PC == breakpoint_data.address)) { \
959 GDBStub::Break(); \
960 goto END; \
961 } \
927 } 962 }
928 963
929// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a 964// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
930// clunky switch statement. 965// clunky switch statement.
931#if defined __GNUC__ || defined __clang__ 966#if defined __GNUC__ || defined __clang__
932#define GOTO_NEXT_INST \ 967#define GOTO_NEXT_INST \
933 GDB_BP_CHECK; \ 968 GDB_BP_CHECK; \
934 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ 969 if (num_instrs >= cpu->NumInstrsToExecute) \
935 num_instrs++; \ 970 goto END; \
936 goto *InstLabel[inst_base->idx] 971 num_instrs++; \
972 goto* InstLabel[inst_base->idx]
937#else 973#else
938#define GOTO_NEXT_INST \ 974#define GOTO_NEXT_INST \
939 GDB_BP_CHECK; \ 975 GDB_BP_CHECK; \
940 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ 976 if (num_instrs >= cpu->NumInstrsToExecute) \
941 num_instrs++; \ 977 goto END; \
942 switch(inst_base->idx) { \ 978 num_instrs++; \
943 case 0: goto VMLA_INST; \ 979 switch (inst_base->idx) { \
944 case 1: goto VMLS_INST; \ 980 case 0: \
945 case 2: goto VNMLA_INST; \ 981 goto VMLA_INST; \
946 case 3: goto VNMLS_INST; \ 982 case 1: \
947 case 4: goto VNMUL_INST; \ 983 goto VMLS_INST; \
948 case 5: goto VMUL_INST; \ 984 case 2: \
949 case 6: goto VADD_INST; \ 985 goto VNMLA_INST; \
950 case 7: goto VSUB_INST; \ 986 case 3: \
951 case 8: goto VDIV_INST; \ 987 goto VNMLS_INST; \
952 case 9: goto VMOVI_INST; \ 988 case 4: \
953 case 10: goto VMOVR_INST; \ 989 goto VNMUL_INST; \
954 case 11: goto VABS_INST; \ 990 case 5: \
955 case 12: goto VNEG_INST; \ 991 goto VMUL_INST; \
956 case 13: goto VSQRT_INST; \ 992 case 6: \
957 case 14: goto VCMP_INST; \ 993 goto VADD_INST; \
958 case 15: goto VCMP2_INST; \ 994 case 7: \
959 case 16: goto VCVTBDS_INST; \ 995 goto VSUB_INST; \
960 case 17: goto VCVTBFF_INST; \ 996 case 8: \
961 case 18: goto VCVTBFI_INST; \ 997 goto VDIV_INST; \
962 case 19: goto VMOVBRS_INST; \ 998 case 9: \
963 case 20: goto VMSR_INST; \ 999 goto VMOVI_INST; \
964 case 21: goto VMOVBRC_INST; \ 1000 case 10: \
965 case 22: goto VMRS_INST; \ 1001 goto VMOVR_INST; \
966 case 23: goto VMOVBCR_INST; \ 1002 case 11: \
967 case 24: goto VMOVBRRSS_INST; \ 1003 goto VABS_INST; \
968 case 25: goto VMOVBRRD_INST; \ 1004 case 12: \
969 case 26: goto VSTR_INST; \ 1005 goto VNEG_INST; \
970 case 27: goto VPUSH_INST; \ 1006 case 13: \
971 case 28: goto VSTM_INST; \ 1007 goto VSQRT_INST; \
972 case 29: goto VPOP_INST; \ 1008 case 14: \
973 case 30: goto VLDR_INST; \ 1009 goto VCMP_INST; \
974 case 31: goto VLDM_INST ; \ 1010 case 15: \
975 case 32: goto SRS_INST; \ 1011 goto VCMP2_INST; \
976 case 33: goto RFE_INST; \ 1012 case 16: \
977 case 34: goto BKPT_INST; \ 1013 goto VCVTBDS_INST; \
978 case 35: goto BLX_INST; \ 1014 case 17: \
979 case 36: goto CPS_INST; \ 1015 goto VCVTBFF_INST; \
980 case 37: goto PLD_INST; \ 1016 case 18: \
981 case 38: goto SETEND_INST; \ 1017 goto VCVTBFI_INST; \
982 case 39: goto CLREX_INST; \ 1018 case 19: \
983 case 40: goto REV16_INST; \ 1019 goto VMOVBRS_INST; \
984 case 41: goto USAD8_INST; \ 1020 case 20: \
985 case 42: goto SXTB_INST; \ 1021 goto VMSR_INST; \
986 case 43: goto UXTB_INST; \ 1022 case 21: \
987 case 44: goto SXTH_INST; \ 1023 goto VMOVBRC_INST; \
988 case 45: goto SXTB16_INST; \ 1024 case 22: \
989 case 46: goto UXTH_INST; \ 1025 goto VMRS_INST; \
990 case 47: goto UXTB16_INST; \ 1026 case 23: \
991 case 48: goto CPY_INST; \ 1027 goto VMOVBCR_INST; \
992 case 49: goto UXTAB_INST; \ 1028 case 24: \
993 case 50: goto SSUB8_INST; \ 1029 goto VMOVBRRSS_INST; \
994 case 51: goto SHSUB8_INST; \ 1030 case 25: \
995 case 52: goto SSUBADDX_INST; \ 1031 goto VMOVBRRD_INST; \
996 case 53: goto STREX_INST; \ 1032 case 26: \
997 case 54: goto STREXB_INST; \ 1033 goto VSTR_INST; \
998 case 55: goto SWP_INST; \ 1034 case 27: \
999 case 56: goto SWPB_INST; \ 1035 goto VPUSH_INST; \
1000 case 57: goto SSUB16_INST; \ 1036 case 28: \
1001 case 58: goto SSAT16_INST; \ 1037 goto VSTM_INST; \
1002 case 59: goto SHSUBADDX_INST; \ 1038 case 29: \
1003 case 60: goto QSUBADDX_INST; \ 1039 goto VPOP_INST; \
1004 case 61: goto SHADDSUBX_INST; \ 1040 case 30: \
1005 case 62: goto SHADD8_INST; \ 1041 goto VLDR_INST; \
1006 case 63: goto SHADD16_INST; \ 1042 case 31: \
1007 case 64: goto SEL_INST; \ 1043 goto VLDM_INST; \
1008 case 65: goto SADDSUBX_INST; \ 1044 case 32: \
1009 case 66: goto SADD8_INST; \ 1045 goto SRS_INST; \
1010 case 67: goto SADD16_INST; \ 1046 case 33: \
1011 case 68: goto SHSUB16_INST; \ 1047 goto RFE_INST; \
1012 case 69: goto UMAAL_INST; \ 1048 case 34: \
1013 case 70: goto UXTAB16_INST; \ 1049 goto BKPT_INST; \
1014 case 71: goto USUBADDX_INST; \ 1050 case 35: \
1015 case 72: goto USUB8_INST; \ 1051 goto BLX_INST; \
1016 case 73: goto USUB16_INST; \ 1052 case 36: \
1017 case 74: goto USAT16_INST; \ 1053 goto CPS_INST; \
1018 case 75: goto USADA8_INST; \ 1054 case 37: \
1019 case 76: goto UQSUBADDX_INST; \ 1055 goto PLD_INST; \
1020 case 77: goto UQSUB8_INST; \ 1056 case 38: \
1021 case 78: goto UQSUB16_INST; \ 1057 goto SETEND_INST; \
1022 case 79: goto UQADDSUBX_INST; \ 1058 case 39: \
1023 case 80: goto UQADD8_INST; \ 1059 goto CLREX_INST; \
1024 case 81: goto UQADD16_INST; \ 1060 case 40: \
1025 case 82: goto SXTAB_INST; \ 1061 goto REV16_INST; \
1026 case 83: goto UHSUBADDX_INST; \ 1062 case 41: \
1027 case 84: goto UHSUB8_INST; \ 1063 goto USAD8_INST; \
1028 case 85: goto UHSUB16_INST; \ 1064 case 42: \
1029 case 86: goto UHADDSUBX_INST; \ 1065 goto SXTB_INST; \
1030 case 87: goto UHADD8_INST; \ 1066 case 43: \
1031 case 88: goto UHADD16_INST; \ 1067 goto UXTB_INST; \
1032 case 89: goto UADDSUBX_INST; \ 1068 case 44: \
1033 case 90: goto UADD8_INST; \ 1069 goto SXTH_INST; \
1034 case 91: goto UADD16_INST; \ 1070 case 45: \
1035 case 92: goto SXTAH_INST; \ 1071 goto SXTB16_INST; \
1036 case 93: goto SXTAB16_INST; \ 1072 case 46: \
1037 case 94: goto QADD8_INST; \ 1073 goto UXTH_INST; \
1038 case 95: goto BXJ_INST; \ 1074 case 47: \
1039 case 96: goto CLZ_INST; \ 1075 goto UXTB16_INST; \
1040 case 97: goto UXTAH_INST; \ 1076 case 48: \
1041 case 98: goto BX_INST; \ 1077 goto CPY_INST; \
1042 case 99: goto REV_INST; \ 1078 case 49: \
1043 case 100: goto BLX_INST; \ 1079 goto UXTAB_INST; \
1044 case 101: goto REVSH_INST; \ 1080 case 50: \
1045 case 102: goto QADD_INST; \ 1081 goto SSUB8_INST; \
1046 case 103: goto QADD16_INST; \ 1082 case 51: \
1047 case 104: goto QADDSUBX_INST; \ 1083 goto SHSUB8_INST; \
1048 case 105: goto LDREX_INST; \ 1084 case 52: \
1049 case 106: goto QDADD_INST; \ 1085 goto SSUBADDX_INST; \
1050 case 107: goto QDSUB_INST; \ 1086 case 53: \
1051 case 108: goto QSUB_INST; \ 1087 goto STREX_INST; \
1052 case 109: goto LDREXB_INST; \ 1088 case 54: \
1053 case 110: goto QSUB8_INST; \ 1089 goto STREXB_INST; \
1054 case 111: goto QSUB16_INST; \ 1090 case 55: \
1055 case 112: goto SMUAD_INST; \ 1091 goto SWP_INST; \
1056 case 113: goto SMMUL_INST; \ 1092 case 56: \
1057 case 114: goto SMUSD_INST; \ 1093 goto SWPB_INST; \
1058 case 115: goto SMLSD_INST; \ 1094 case 57: \
1059 case 116: goto SMLSLD_INST; \ 1095 goto SSUB16_INST; \
1060 case 117: goto SMMLA_INST; \ 1096 case 58: \
1061 case 118: goto SMMLS_INST; \ 1097 goto SSAT16_INST; \
1062 case 119: goto SMLALD_INST; \ 1098 case 59: \
1063 case 120: goto SMLAD_INST; \ 1099 goto SHSUBADDX_INST; \
1064 case 121: goto SMLAW_INST; \ 1100 case 60: \
1065 case 122: goto SMULW_INST; \ 1101 goto QSUBADDX_INST; \
1066 case 123: goto PKHTB_INST; \ 1102 case 61: \
1067 case 124: goto PKHBT_INST; \ 1103 goto SHADDSUBX_INST; \
1068 case 125: goto SMUL_INST; \ 1104 case 62: \
1069 case 126: goto SMLALXY_INST; \ 1105 goto SHADD8_INST; \
1070 case 127: goto SMLA_INST; \ 1106 case 63: \
1071 case 128: goto MCRR_INST; \ 1107 goto SHADD16_INST; \
1072 case 129: goto MRRC_INST; \ 1108 case 64: \
1073 case 130: goto CMP_INST; \ 1109 goto SEL_INST; \
1074 case 131: goto TST_INST; \ 1110 case 65: \
1075 case 132: goto TEQ_INST; \ 1111 goto SADDSUBX_INST; \
1076 case 133: goto CMN_INST; \ 1112 case 66: \
1077 case 134: goto SMULL_INST; \ 1113 goto SADD8_INST; \
1078 case 135: goto UMULL_INST; \ 1114 case 67: \
1079 case 136: goto UMLAL_INST; \ 1115 goto SADD16_INST; \
1080 case 137: goto SMLAL_INST; \ 1116 case 68: \
1081 case 138: goto MUL_INST; \ 1117 goto SHSUB16_INST; \
1082 case 139: goto MLA_INST; \ 1118 case 69: \
1083 case 140: goto SSAT_INST; \ 1119 goto UMAAL_INST; \
1084 case 141: goto USAT_INST; \ 1120 case 70: \
1085 case 142: goto MRS_INST; \ 1121 goto UXTAB16_INST; \
1086 case 143: goto MSR_INST; \ 1122 case 71: \
1087 case 144: goto AND_INST; \ 1123 goto USUBADDX_INST; \
1088 case 145: goto BIC_INST; \ 1124 case 72: \
1089 case 146: goto LDM_INST; \ 1125 goto USUB8_INST; \
1090 case 147: goto EOR_INST; \ 1126 case 73: \
1091 case 148: goto ADD_INST; \ 1127 goto USUB16_INST; \
1092 case 149: goto RSB_INST; \ 1128 case 74: \
1093 case 150: goto RSC_INST; \ 1129 goto USAT16_INST; \
1094 case 151: goto SBC_INST; \ 1130 case 75: \
1095 case 152: goto ADC_INST; \ 1131 goto USADA8_INST; \
1096 case 153: goto SUB_INST; \ 1132 case 76: \
1097 case 154: goto ORR_INST; \ 1133 goto UQSUBADDX_INST; \
1098 case 155: goto MVN_INST; \ 1134 case 77: \
1099 case 156: goto MOV_INST; \ 1135 goto UQSUB8_INST; \
1100 case 157: goto STM_INST; \ 1136 case 78: \
1101 case 158: goto LDM_INST; \ 1137 goto UQSUB16_INST; \
1102 case 159: goto LDRSH_INST; \ 1138 case 79: \
1103 case 160: goto STM_INST; \ 1139 goto UQADDSUBX_INST; \
1104 case 161: goto LDM_INST; \ 1140 case 80: \
1105 case 162: goto LDRSB_INST; \ 1141 goto UQADD8_INST; \
1106 case 163: goto STRD_INST; \ 1142 case 81: \
1107 case 164: goto LDRH_INST; \ 1143 goto UQADD16_INST; \
1108 case 165: goto STRH_INST; \ 1144 case 82: \
1109 case 166: goto LDRD_INST; \ 1145 goto SXTAB_INST; \
1110 case 167: goto STRT_INST; \ 1146 case 83: \
1111 case 168: goto STRBT_INST; \ 1147 goto UHSUBADDX_INST; \
1112 case 169: goto LDRBT_INST; \ 1148 case 84: \
1113 case 170: goto LDRT_INST; \ 1149 goto UHSUB8_INST; \
1114 case 171: goto MRC_INST; \ 1150 case 85: \
1115 case 172: goto MCR_INST; \ 1151 goto UHSUB16_INST; \
1116 case 173: goto MSR_INST; \ 1152 case 86: \
1117 case 174: goto MSR_INST; \ 1153 goto UHADDSUBX_INST; \
1118 case 175: goto MSR_INST; \ 1154 case 87: \
1119 case 176: goto MSR_INST; \ 1155 goto UHADD8_INST; \
1120 case 177: goto MSR_INST; \ 1156 case 88: \
1121 case 178: goto LDRB_INST; \ 1157 goto UHADD16_INST; \
1122 case 179: goto STRB_INST; \ 1158 case 89: \
1123 case 180: goto LDR_INST; \ 1159 goto UADDSUBX_INST; \
1124 case 181: goto LDRCOND_INST ; \ 1160 case 90: \
1125 case 182: goto STR_INST; \ 1161 goto UADD8_INST; \
1126 case 183: goto CDP_INST; \ 1162 case 91: \
1127 case 184: goto STC_INST; \ 1163 goto UADD16_INST; \
1128 case 185: goto LDC_INST; \ 1164 case 92: \
1129 case 186: goto LDREXD_INST; \ 1165 goto SXTAH_INST; \
1130 case 187: goto STREXD_INST; \ 1166 case 93: \
1131 case 188: goto LDREXH_INST; \ 1167 goto SXTAB16_INST; \
1132 case 189: goto STREXH_INST; \ 1168 case 94: \
1133 case 190: goto NOP_INST; \ 1169 goto QADD8_INST; \
1134 case 191: goto YIELD_INST; \ 1170 case 95: \
1135 case 192: goto WFE_INST; \ 1171 goto BXJ_INST; \
1136 case 193: goto WFI_INST; \ 1172 case 96: \
1137 case 194: goto SEV_INST; \ 1173 goto CLZ_INST; \
1138 case 195: goto SWI_INST; \ 1174 case 97: \
1139 case 196: goto BBL_INST; \ 1175 goto UXTAH_INST; \
1140 case 197: goto B_2_THUMB ; \ 1176 case 98: \
1141 case 198: goto B_COND_THUMB ; \ 1177 goto BX_INST; \
1142 case 199: goto BL_1_THUMB ; \ 1178 case 99: \
1143 case 200: goto BL_2_THUMB ; \ 1179 goto REV_INST; \
1144 case 201: goto BLX_1_THUMB ; \ 1180 case 100: \
1145 case 202: goto DISPATCH; \ 1181 goto BLX_INST; \
1146 case 203: goto INIT_INST_LENGTH; \ 1182 case 101: \
1147 case 204: goto END; \ 1183 goto REVSH_INST; \
1184 case 102: \
1185 goto QADD_INST; \
1186 case 103: \
1187 goto QADD16_INST; \
1188 case 104: \
1189 goto QADDSUBX_INST; \
1190 case 105: \
1191 goto LDREX_INST; \
1192 case 106: \
1193 goto QDADD_INST; \
1194 case 107: \
1195 goto QDSUB_INST; \
1196 case 108: \
1197 goto QSUB_INST; \
1198 case 109: \
1199 goto LDREXB_INST; \
1200 case 110: \
1201 goto QSUB8_INST; \
1202 case 111: \
1203 goto QSUB16_INST; \
1204 case 112: \
1205 goto SMUAD_INST; \
1206 case 113: \
1207 goto SMMUL_INST; \
1208 case 114: \
1209 goto SMUSD_INST; \
1210 case 115: \
1211 goto SMLSD_INST; \
1212 case 116: \
1213 goto SMLSLD_INST; \
1214 case 117: \
1215 goto SMMLA_INST; \
1216 case 118: \
1217 goto SMMLS_INST; \
1218 case 119: \
1219 goto SMLALD_INST; \
1220 case 120: \
1221 goto SMLAD_INST; \
1222 case 121: \
1223 goto SMLAW_INST; \
1224 case 122: \
1225 goto SMULW_INST; \
1226 case 123: \
1227 goto PKHTB_INST; \
1228 case 124: \
1229 goto PKHBT_INST; \
1230 case 125: \
1231 goto SMUL_INST; \
1232 case 126: \
1233 goto SMLALXY_INST; \
1234 case 127: \
1235 goto SMLA_INST; \
1236 case 128: \
1237 goto MCRR_INST; \
1238 case 129: \
1239 goto MRRC_INST; \
1240 case 130: \
1241 goto CMP_INST; \
1242 case 131: \
1243 goto TST_INST; \
1244 case 132: \
1245 goto TEQ_INST; \
1246 case 133: \
1247 goto CMN_INST; \
1248 case 134: \
1249 goto SMULL_INST; \
1250 case 135: \
1251 goto UMULL_INST; \
1252 case 136: \
1253 goto UMLAL_INST; \
1254 case 137: \
1255 goto SMLAL_INST; \
1256 case 138: \
1257 goto MUL_INST; \
1258 case 139: \
1259 goto MLA_INST; \
1260 case 140: \
1261 goto SSAT_INST; \
1262 case 141: \
1263 goto USAT_INST; \
1264 case 142: \
1265 goto MRS_INST; \
1266 case 143: \
1267 goto MSR_INST; \
1268 case 144: \
1269 goto AND_INST; \
1270 case 145: \
1271 goto BIC_INST; \
1272 case 146: \
1273 goto LDM_INST; \
1274 case 147: \
1275 goto EOR_INST; \
1276 case 148: \
1277 goto ADD_INST; \
1278 case 149: \
1279 goto RSB_INST; \
1280 case 150: \
1281 goto RSC_INST; \
1282 case 151: \
1283 goto SBC_INST; \
1284 case 152: \
1285 goto ADC_INST; \
1286 case 153: \
1287 goto SUB_INST; \
1288 case 154: \
1289 goto ORR_INST; \
1290 case 155: \
1291 goto MVN_INST; \
1292 case 156: \
1293 goto MOV_INST; \
1294 case 157: \
1295 goto STM_INST; \
1296 case 158: \
1297 goto LDM_INST; \
1298 case 159: \
1299 goto LDRSH_INST; \
1300 case 160: \
1301 goto STM_INST; \
1302 case 161: \
1303 goto LDM_INST; \
1304 case 162: \
1305 goto LDRSB_INST; \
1306 case 163: \
1307 goto STRD_INST; \
1308 case 164: \
1309 goto LDRH_INST; \
1310 case 165: \
1311 goto STRH_INST; \
1312 case 166: \
1313 goto LDRD_INST; \
1314 case 167: \
1315 goto STRT_INST; \
1316 case 168: \
1317 goto STRBT_INST; \
1318 case 169: \
1319 goto LDRBT_INST; \
1320 case 170: \
1321 goto LDRT_INST; \
1322 case 171: \
1323 goto MRC_INST; \
1324 case 172: \
1325 goto MCR_INST; \
1326 case 173: \
1327 goto MSR_INST; \
1328 case 174: \
1329 goto MSR_INST; \
1330 case 175: \
1331 goto MSR_INST; \
1332 case 176: \
1333 goto MSR_INST; \
1334 case 177: \
1335 goto MSR_INST; \
1336 case 178: \
1337 goto LDRB_INST; \
1338 case 179: \
1339 goto STRB_INST; \
1340 case 180: \
1341 goto LDR_INST; \
1342 case 181: \
1343 goto LDRCOND_INST; \
1344 case 182: \
1345 goto STR_INST; \
1346 case 183: \
1347 goto CDP_INST; \
1348 case 184: \
1349 goto STC_INST; \
1350 case 185: \
1351 goto LDC_INST; \
1352 case 186: \
1353 goto LDREXD_INST; \
1354 case 187: \
1355 goto STREXD_INST; \
1356 case 188: \
1357 goto LDREXH_INST; \
1358 case 189: \
1359 goto STREXH_INST; \
1360 case 190: \
1361 goto NOP_INST; \
1362 case 191: \
1363 goto YIELD_INST; \
1364 case 192: \
1365 goto WFE_INST; \
1366 case 193: \
1367 goto WFI_INST; \
1368 case 194: \
1369 goto SEV_INST; \
1370 case 195: \
1371 goto SWI_INST; \
1372 case 196: \
1373 goto BBL_INST; \
1374 case 197: \
1375 goto B_2_THUMB; \
1376 case 198: \
1377 goto B_COND_THUMB; \
1378 case 199: \
1379 goto BL_1_THUMB; \
1380 case 200: \
1381 goto BL_2_THUMB; \
1382 case 201: \
1383 goto BLX_1_THUMB; \
1384 case 202: \
1385 goto DISPATCH; \
1386 case 203: \
1387 goto INIT_INST_LENGTH; \
1388 case 204: \
1389 goto END; \
1148 } 1390 }
1149#endif 1391#endif
1150 1392
1151 #define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0) 1393#define UPDATE_NFLAG(dst) (cpu->NFlag = BIT(dst, 31) ? 1 : 0)
1152 #define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1) 1394#define UPDATE_ZFLAG(dst) (cpu->ZFlag = dst ? 0 : 1)
1153 #define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out) 1395#define UPDATE_CFLAG_WITH_SC (cpu->CFlag = cpu->shifter_carry_out)
1154 1396
1155 #define SAVE_NZCVT cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | \ 1397#define SAVE_NZCVT \
1156 (cpu->NFlag << 31) | \ 1398 cpu->Cpsr = (cpu->Cpsr & 0x0fffffdf) | (cpu->NFlag << 31) | (cpu->ZFlag << 30) | \
1157 (cpu->ZFlag << 30) | \ 1399 (cpu->CFlag << 29) | (cpu->VFlag << 28) | (cpu->TFlag << 5)
1158 (cpu->CFlag << 29) | \ 1400#define LOAD_NZCVT \
1159 (cpu->VFlag << 28) | \ 1401 cpu->NFlag = (cpu->Cpsr >> 31); \
1160 (cpu->TFlag << 5) 1402 cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \
1161 #define LOAD_NZCVT cpu->NFlag = (cpu->Cpsr >> 31); \ 1403 cpu->CFlag = (cpu->Cpsr >> 29) & 1; \
1162 cpu->ZFlag = (cpu->Cpsr >> 30) & 1; \ 1404 cpu->VFlag = (cpu->Cpsr >> 28) & 1; \
1163 cpu->CFlag = (cpu->Cpsr >> 29) & 1; \ 1405 cpu->TFlag = (cpu->Cpsr >> 5) & 1;
1164 cpu->VFlag = (cpu->Cpsr >> 28) & 1; \ 1406
1165 cpu->TFlag = (cpu->Cpsr >> 5) & 1; 1407#define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE)
1166 1408#define PC (cpu->Reg[15])
1167 #define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE) 1409
1168 #define PC (cpu->Reg[15]) 1410// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
1169 1411// to a clunky switch statement.
1170 // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
1171 // to a clunky switch statement.
1172#if defined __GNUC__ || defined __clang__ 1412#if defined __GNUC__ || defined __clang__
1173 void *InstLabel[] = { 1413 void* InstLabel[] = {&&VMLA_INST,
1174 &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST, 1414 &&VMLS_INST,
1175 &&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST, 1415 &&VNMLA_INST,
1176 &&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST, 1416 &&VNMLS_INST,
1177 &&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST, 1417 &&VNMUL_INST,
1178 1418 &&VMUL_INST,
1179 &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST, 1419 &&VADD_INST,
1180 &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST, 1420 &&VSUB_INST,
1181 &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST, 1421 &&VDIV_INST,
1182 &&SHADD8_INST,&&SHADD16_INST,&&SEL_INST,&&SADDSUBX_INST,&&SADD8_INST,&&SADD16_INST,&&SHSUB16_INST,&&UMAAL_INST,&&UXTAB16_INST, 1422 &&VMOVI_INST,
1183 &&USUBADDX_INST,&&USUB8_INST,&&USUB16_INST,&&USAT16_INST,&&USADA8_INST,&&UQSUBADDX_INST,&&UQSUB8_INST,&&UQSUB16_INST, 1423 &&VMOVR_INST,
1184 &&UQADDSUBX_INST,&&UQADD8_INST,&&UQADD16_INST,&&SXTAB_INST,&&UHSUBADDX_INST,&&UHSUB8_INST,&&UHSUB16_INST,&&UHADDSUBX_INST,&&UHADD8_INST, 1424 &&VABS_INST,
1185 &&UHADD16_INST,&&UADDSUBX_INST,&&UADD8_INST,&&UADD16_INST,&&SXTAH_INST,&&SXTAB16_INST,&&QADD8_INST,&&BXJ_INST,&&CLZ_INST,&&UXTAH_INST, 1425 &&VNEG_INST,
1186 &&BX_INST,&&REV_INST,&&BLX_INST,&&REVSH_INST,&&QADD_INST,&&QADD16_INST,&&QADDSUBX_INST,&&LDREX_INST,&&QDADD_INST,&&QDSUB_INST, 1426 &&VSQRT_INST,
1187 &&QSUB_INST,&&LDREXB_INST,&&QSUB8_INST,&&QSUB16_INST,&&SMUAD_INST,&&SMMUL_INST,&&SMUSD_INST,&&SMLSD_INST,&&SMLSLD_INST,&&SMMLA_INST, 1427 &&VCMP_INST,
1188 &&SMMLS_INST,&&SMLALD_INST,&&SMLAD_INST,&&SMLAW_INST,&&SMULW_INST,&&PKHTB_INST,&&PKHBT_INST,&&SMUL_INST,&&SMLALXY_INST,&&SMLA_INST, 1428 &&VCMP2_INST,
1189 &&MCRR_INST,&&MRRC_INST,&&CMP_INST,&&TST_INST,&&TEQ_INST,&&CMN_INST,&&SMULL_INST,&&UMULL_INST,&&UMLAL_INST,&&SMLAL_INST,&&MUL_INST, 1429 &&VCVTBDS_INST,
1190 &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, 1430 &&VCVTBFF_INST,
1191 &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, 1431 &&VCVTBFI_INST,
1192 &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST, 1432 &&VMOVBRS_INST,
1193 &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, &&MSR_INST, 1433 &&VMSR_INST,
1194 &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST, 1434 &&VMOVBRC_INST,
1195 &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&NOP_INST, &&YIELD_INST, &&WFE_INST, &&WFI_INST, &&SEV_INST, &&SWI_INST,&&BBL_INST, 1435 &&VMRS_INST,
1196 &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, 1436 &&VMOVBCR_INST,
1197 &&INIT_INST_LENGTH,&&END 1437 &&VMOVBRRSS_INST,
1198 }; 1438 &&VMOVBRRD_INST,
1439 &&VSTR_INST,
1440 &&VPUSH_INST,
1441 &&VSTM_INST,
1442 &&VPOP_INST,
1443 &&VLDR_INST,
1444 &&VLDM_INST,
1445
1446 &&SRS_INST,
1447 &&RFE_INST,
1448 &&BKPT_INST,
1449 &&BLX_INST,
1450 &&CPS_INST,
1451 &&PLD_INST,
1452 &&SETEND_INST,
1453 &&CLREX_INST,
1454 &&REV16_INST,
1455 &&USAD8_INST,
1456 &&SXTB_INST,
1457 &&UXTB_INST,
1458 &&SXTH_INST,
1459 &&SXTB16_INST,
1460 &&UXTH_INST,
1461 &&UXTB16_INST,
1462 &&CPY_INST,
1463 &&UXTAB_INST,
1464 &&SSUB8_INST,
1465 &&SHSUB8_INST,
1466 &&SSUBADDX_INST,
1467 &&STREX_INST,
1468 &&STREXB_INST,
1469 &&SWP_INST,
1470 &&SWPB_INST,
1471 &&SSUB16_INST,
1472 &&SSAT16_INST,
1473 &&SHSUBADDX_INST,
1474 &&QSUBADDX_INST,
1475 &&SHADDSUBX_INST,
1476 &&SHADD8_INST,
1477 &&SHADD16_INST,
1478 &&SEL_INST,
1479 &&SADDSUBX_INST,
1480 &&SADD8_INST,
1481 &&SADD16_INST,
1482 &&SHSUB16_INST,
1483 &&UMAAL_INST,
1484 &&UXTAB16_INST,
1485 &&USUBADDX_INST,
1486 &&USUB8_INST,
1487 &&USUB16_INST,
1488 &&USAT16_INST,
1489 &&USADA8_INST,
1490 &&UQSUBADDX_INST,
1491 &&UQSUB8_INST,
1492 &&UQSUB16_INST,
1493 &&UQADDSUBX_INST,
1494 &&UQADD8_INST,
1495 &&UQADD16_INST,
1496 &&SXTAB_INST,
1497 &&UHSUBADDX_INST,
1498 &&UHSUB8_INST,
1499 &&UHSUB16_INST,
1500 &&UHADDSUBX_INST,
1501 &&UHADD8_INST,
1502 &&UHADD16_INST,
1503 &&UADDSUBX_INST,
1504 &&UADD8_INST,
1505 &&UADD16_INST,
1506 &&SXTAH_INST,
1507 &&SXTAB16_INST,
1508 &&QADD8_INST,
1509 &&BXJ_INST,
1510 &&CLZ_INST,
1511 &&UXTAH_INST,
1512 &&BX_INST,
1513 &&REV_INST,
1514 &&BLX_INST,
1515 &&REVSH_INST,
1516 &&QADD_INST,
1517 &&QADD16_INST,
1518 &&QADDSUBX_INST,
1519 &&LDREX_INST,
1520 &&QDADD_INST,
1521 &&QDSUB_INST,
1522 &&QSUB_INST,
1523 &&LDREXB_INST,
1524 &&QSUB8_INST,
1525 &&QSUB16_INST,
1526 &&SMUAD_INST,
1527 &&SMMUL_INST,
1528 &&SMUSD_INST,
1529 &&SMLSD_INST,
1530 &&SMLSLD_INST,
1531 &&SMMLA_INST,
1532 &&SMMLS_INST,
1533 &&SMLALD_INST,
1534 &&SMLAD_INST,
1535 &&SMLAW_INST,
1536 &&SMULW_INST,
1537 &&PKHTB_INST,
1538 &&PKHBT_INST,
1539 &&SMUL_INST,
1540 &&SMLALXY_INST,
1541 &&SMLA_INST,
1542 &&MCRR_INST,
1543 &&MRRC_INST,
1544 &&CMP_INST,
1545 &&TST_INST,
1546 &&TEQ_INST,
1547 &&CMN_INST,
1548 &&SMULL_INST,
1549 &&UMULL_INST,
1550 &&UMLAL_INST,
1551 &&SMLAL_INST,
1552 &&MUL_INST,
1553 &&MLA_INST,
1554 &&SSAT_INST,
1555 &&USAT_INST,
1556 &&MRS_INST,
1557 &&MSR_INST,
1558 &&AND_INST,
1559 &&BIC_INST,
1560 &&LDM_INST,
1561 &&EOR_INST,
1562 &&ADD_INST,
1563 &&RSB_INST,
1564 &&RSC_INST,
1565 &&SBC_INST,
1566 &&ADC_INST,
1567 &&SUB_INST,
1568 &&ORR_INST,
1569 &&MVN_INST,
1570 &&MOV_INST,
1571 &&STM_INST,
1572 &&LDM_INST,
1573 &&LDRSH_INST,
1574 &&STM_INST,
1575 &&LDM_INST,
1576 &&LDRSB_INST,
1577 &&STRD_INST,
1578 &&LDRH_INST,
1579 &&STRH_INST,
1580 &&LDRD_INST,
1581 &&STRT_INST,
1582 &&STRBT_INST,
1583 &&LDRBT_INST,
1584 &&LDRT_INST,
1585 &&MRC_INST,
1586 &&MCR_INST,
1587 &&MSR_INST,
1588 &&MSR_INST,
1589 &&MSR_INST,
1590 &&MSR_INST,
1591 &&MSR_INST,
1592 &&LDRB_INST,
1593 &&STRB_INST,
1594 &&LDR_INST,
1595 &&LDRCOND_INST,
1596 &&STR_INST,
1597 &&CDP_INST,
1598 &&STC_INST,
1599 &&LDC_INST,
1600 &&LDREXD_INST,
1601 &&STREXD_INST,
1602 &&LDREXH_INST,
1603 &&STREXH_INST,
1604 &&NOP_INST,
1605 &&YIELD_INST,
1606 &&WFE_INST,
1607 &&WFI_INST,
1608 &&SEV_INST,
1609 &&SWI_INST,
1610 &&BBL_INST,
1611 &&B_2_THUMB,
1612 &&B_COND_THUMB,
1613 &&BL_1_THUMB,
1614 &&BL_2_THUMB,
1615 &&BLX_1_THUMB,
1616 &&DISPATCH,
1617 &&INIT_INST_LENGTH,
1618 &&END};
1199#endif 1619#endif
1200 arm_inst* inst_base; 1620 arm_inst* inst_base;
1201 unsigned int addr; 1621 unsigned int addr;
@@ -1204,516 +1624,517 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
1204 int ptr; 1624 int ptr;
1205 1625
1206 LOAD_NZCVT; 1626 LOAD_NZCVT;
1207 DISPATCH: 1627DISPATCH : {
1208 { 1628 if (!cpu->NirqSig) {
1209 if (!cpu->NirqSig) { 1629 if (!(cpu->Cpsr & 0x80)) {
1210 if (!(cpu->Cpsr & 0x80)) { 1630 goto END;
1211 goto END;
1212 }
1213 } 1631 }
1632 }
1214 1633
1215 if (cpu->TFlag) 1634 if (cpu->TFlag)
1216 cpu->Reg[15] &= 0xfffffffe; 1635 cpu->Reg[15] &= 0xfffffffe;
1217 else 1636 else
1218 cpu->Reg[15] &= 0xfffffffc; 1637 cpu->Reg[15] &= 0xfffffffc;
1219 1638
1220 // Find the cached instruction cream, otherwise translate it... 1639 // Find the cached instruction cream, otherwise translate it...
1221 auto itr = cpu->instruction_cache.find(cpu->Reg[15]); 1640 auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
1222 if (itr != cpu->instruction_cache.end()) { 1641 if (itr != cpu->instruction_cache.end()) {
1223 ptr = itr->second; 1642 ptr = itr->second;
1224 } else if (cpu->NumInstrsToExecute != 1) { 1643 } else if (cpu->NumInstrsToExecute != 1) {
1225 if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) 1644 if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
1226 goto END; 1645 goto END;
1227 } else { 1646 } else {
1228 if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) 1647 if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
1229 goto END; 1648 goto END;
1230 } 1649 }
1231 1650
1232 // Find breakpoint if one exists within the block 1651 // Find breakpoint if one exists within the block
1233 if (GDBStub::g_server_enabled && GDBStub::IsConnected()) { 1652 if (GDBStub::g_server_enabled && GDBStub::IsConnected()) {
1234 breakpoint_data = GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute); 1653 breakpoint_data =
1235 } 1654 GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute);
1655 }
1236 1656
1237 inst_base = (arm_inst *)&trans_cache_buf[ptr]; 1657 inst_base = (arm_inst*)&trans_cache_buf[ptr];
1238 GOTO_NEXT_INST; 1658 GOTO_NEXT_INST;
1659}
1660ADC_INST : {
1661 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1662 adc_inst* const inst_cream = (adc_inst*)inst_base->component;
1663
1664 u32 rn_val = RN;
1665 if (inst_cream->Rn == 15)
1666 rn_val += 2 * cpu->GetInstructionSize();
1667
1668 bool carry;
1669 bool overflow;
1670 RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
1671
1672 if (inst_cream->S && (inst_cream->Rd == 15)) {
1673 if (CurrentModeHasSPSR) {
1674 cpu->Cpsr = cpu->Spsr_copy;
1675 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
1676 LOAD_NZCVT;
1677 }
1678 } else if (inst_cream->S) {
1679 UPDATE_NFLAG(RD);
1680 UPDATE_ZFLAG(RD);
1681 cpu->CFlag = carry;
1682 cpu->VFlag = overflow;
1683 }
1684 if (inst_cream->Rd == 15) {
1685 INC_PC(sizeof(adc_inst));
1686 goto DISPATCH;
1687 }
1239 } 1688 }
1240 ADC_INST: 1689 cpu->Reg[15] += cpu->GetInstructionSize();
1241 { 1690 INC_PC(sizeof(adc_inst));
1242 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1691 FETCH_INST;
1243 adc_inst* const inst_cream = (adc_inst*)inst_base->component; 1692 GOTO_NEXT_INST;
1693}
1694ADD_INST : {
1695 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1696 add_inst* const inst_cream = (add_inst*)inst_base->component;
1244 1697
1245 u32 rn_val = RN; 1698 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
1246 if (inst_cream->Rn == 15)
1247 rn_val += 2 * cpu->GetInstructionSize();
1248 1699
1249 bool carry; 1700 bool carry;
1250 bool overflow; 1701 bool overflow;
1251 RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); 1702 RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
1252 1703
1253 if (inst_cream->S && (inst_cream->Rd == 15)) { 1704 if (inst_cream->S && (inst_cream->Rd == 15)) {
1254 if (CurrentModeHasSPSR) { 1705 if (CurrentModeHasSPSR) {
1255 cpu->Cpsr = cpu->Spsr_copy; 1706 cpu->Cpsr = cpu->Spsr_copy;
1256 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 1707 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
1257 LOAD_NZCVT; 1708 LOAD_NZCVT;
1258 }
1259 } else if (inst_cream->S) {
1260 UPDATE_NFLAG(RD);
1261 UPDATE_ZFLAG(RD);
1262 cpu->CFlag = carry;
1263 cpu->VFlag = overflow;
1264 }
1265 if (inst_cream->Rd == 15) {
1266 INC_PC(sizeof(adc_inst));
1267 goto DISPATCH;
1268 } 1709 }
1710 } else if (inst_cream->S) {
1711 UPDATE_NFLAG(RD);
1712 UPDATE_ZFLAG(RD);
1713 cpu->CFlag = carry;
1714 cpu->VFlag = overflow;
1269 } 1715 }
1270 cpu->Reg[15] += cpu->GetInstructionSize(); 1716 if (inst_cream->Rd == 15) {
1271 INC_PC(sizeof(adc_inst)); 1717 INC_PC(sizeof(add_inst));
1272 FETCH_INST; 1718 goto DISPATCH;
1273 GOTO_NEXT_INST;
1274 }
1275 ADD_INST:
1276 {
1277 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1278 add_inst* const inst_cream = (add_inst*)inst_base->component;
1279
1280 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
1281
1282 bool carry;
1283 bool overflow;
1284 RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
1285
1286 if (inst_cream->S && (inst_cream->Rd == 15)) {
1287 if (CurrentModeHasSPSR) {
1288 cpu->Cpsr = cpu->Spsr_copy;
1289 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
1290 LOAD_NZCVT;
1291 }
1292 } else if (inst_cream->S) {
1293 UPDATE_NFLAG(RD);
1294 UPDATE_ZFLAG(RD);
1295 cpu->CFlag = carry;
1296 cpu->VFlag = overflow;
1297 }
1298 if (inst_cream->Rd == 15) {
1299 INC_PC(sizeof(add_inst));
1300 goto DISPATCH;
1301 }
1302 } 1719 }
1303 cpu->Reg[15] += cpu->GetInstructionSize();
1304 INC_PC(sizeof(add_inst));
1305 FETCH_INST;
1306 GOTO_NEXT_INST;
1307 } 1720 }
1308 AND_INST: 1721 cpu->Reg[15] += cpu->GetInstructionSize();
1309 { 1722 INC_PC(sizeof(add_inst));
1310 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1723 FETCH_INST;
1311 and_inst* const inst_cream = (and_inst*)inst_base->component; 1724 GOTO_NEXT_INST;
1725}
1726AND_INST : {
1727 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1728 and_inst* const inst_cream = (and_inst*)inst_base->component;
1312 1729
1313 u32 lop = RN; 1730 u32 lop = RN;
1314 u32 rop = SHIFTER_OPERAND; 1731 u32 rop = SHIFTER_OPERAND;
1315 1732
1316 if (inst_cream->Rn == 15) 1733 if (inst_cream->Rn == 15)
1317 lop += 2 * cpu->GetInstructionSize(); 1734 lop += 2 * cpu->GetInstructionSize();
1318 1735
1319 RD = lop & rop; 1736 RD = lop & rop;
1320 1737
1321 if (inst_cream->S && (inst_cream->Rd == 15)) { 1738 if (inst_cream->S && (inst_cream->Rd == 15)) {
1322 if (CurrentModeHasSPSR) { 1739 if (CurrentModeHasSPSR) {
1323 cpu->Cpsr = cpu->Spsr_copy; 1740 cpu->Cpsr = cpu->Spsr_copy;
1324 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); 1741 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
1325 LOAD_NZCVT; 1742 LOAD_NZCVT;
1326 }
1327 } else if (inst_cream->S) {
1328 UPDATE_NFLAG(RD);
1329 UPDATE_ZFLAG(RD);
1330 UPDATE_CFLAG_WITH_SC;
1331 }
1332 if (inst_cream->Rd == 15) {
1333 INC_PC(sizeof(and_inst));
1334 goto DISPATCH;
1335 } 1743 }
1744 } else if (inst_cream->S) {
1745 UPDATE_NFLAG(RD);
1746 UPDATE_ZFLAG(RD);
1747 UPDATE_CFLAG_WITH_SC;
1336 } 1748 }
1337 cpu->Reg[15] += cpu->GetInstructionSize(); 1749 if (inst_cream->Rd == 15) {
1338 INC_PC(sizeof(and_inst)); 1750 INC_PC(sizeof(and_inst));
1339 FETCH_INST;
1340 GOTO_NEXT_INST;
1341 }
1342 BBL_INST:
1343 {
1344 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
1345 bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
1346 if (inst_cream->L) {
1347 LINK_RTN_ADDR;
1348 }
1349 SET_PC;
1350 INC_PC(sizeof(bbl_inst));
1351 goto DISPATCH; 1751 goto DISPATCH;
1352 } 1752 }
1353 cpu->Reg[15] += cpu->GetInstructionSize(); 1753 }
1754 cpu->Reg[15] += cpu->GetInstructionSize();
1755 INC_PC(sizeof(and_inst));
1756 FETCH_INST;
1757 GOTO_NEXT_INST;
1758}
1759BBL_INST : {
1760 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
1761 bbl_inst* inst_cream = (bbl_inst*)inst_base->component;
1762 if (inst_cream->L) {
1763 LINK_RTN_ADDR;
1764 }
1765 SET_PC;
1354 INC_PC(sizeof(bbl_inst)); 1766 INC_PC(sizeof(bbl_inst));
1355 goto DISPATCH; 1767 goto DISPATCH;
1356 } 1768 }
1357 BIC_INST: 1769 cpu->Reg[15] += cpu->GetInstructionSize();
1358 { 1770 INC_PC(sizeof(bbl_inst));
1359 bic_inst *inst_cream = (bic_inst *)inst_base->component; 1771 goto DISPATCH;
1360 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) { 1772}
1361 u32 lop = RN; 1773BIC_INST : {
1362 if (inst_cream->Rn == 15) { 1774 bic_inst* inst_cream = (bic_inst*)inst_base->component;
1363 lop += 2 * cpu->GetInstructionSize(); 1775 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
1364 } 1776 u32 lop = RN;
1365 u32 rop = SHIFTER_OPERAND; 1777 if (inst_cream->Rn == 15) {
1366 RD = lop & (~rop); 1778 lop += 2 * cpu->GetInstructionSize();
1367 if ((inst_cream->S) && (inst_cream->Rd == 15)) {
1368 if (CurrentModeHasSPSR) {
1369 cpu->Cpsr = cpu->Spsr_copy;
1370 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
1371 LOAD_NZCVT;
1372 }
1373 } else if (inst_cream->S) {
1374 UPDATE_NFLAG(RD);
1375 UPDATE_ZFLAG(RD);
1376 UPDATE_CFLAG_WITH_SC;
1377 }
1378 if (inst_cream->Rd == 15) {
1379 INC_PC(sizeof(bic_inst));
1380 goto DISPATCH;
1381 }
1382 }
1383 cpu->Reg[15] += cpu->GetInstructionSize();
1384 INC_PC(sizeof(bic_inst));
1385 FETCH_INST;
1386 GOTO_NEXT_INST;
1387 }
1388 BKPT_INST:
1389 {
1390 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1391 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
1392 LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
1393 } 1779 }
1394 cpu->Reg[15] += cpu->GetInstructionSize(); 1780 u32 rop = SHIFTER_OPERAND;
1395 INC_PC(sizeof(bkpt_inst)); 1781 RD = lop & (~rop);
1396 FETCH_INST; 1782 if ((inst_cream->S) && (inst_cream->Rd == 15)) {
1397 GOTO_NEXT_INST; 1783 if (CurrentModeHasSPSR) {
1398 } 1784 cpu->Cpsr = cpu->Spsr_copy;
1399 BLX_INST: 1785 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
1400 { 1786 LOAD_NZCVT;
1401 blx_inst *inst_cream = (blx_inst *)inst_base->component;
1402 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
1403 unsigned int inst = inst_cream->inst;
1404 if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
1405 const u32 jump_address = cpu->Reg[inst_cream->val.Rm];
1406 cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
1407 if(cpu->TFlag)
1408 cpu->Reg[14] |= 0x1;
1409 cpu->Reg[15] = jump_address & 0xfffffffe;
1410 cpu->TFlag = jump_address & 0x1;
1411 } else {
1412 cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
1413 cpu->TFlag = 0x1;
1414 int signed_int = inst_cream->val.signed_immed_24;
1415 signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int;
1416 signed_int = signed_int << 2;
1417 cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1);
1418 } 1787 }
1419 INC_PC(sizeof(blx_inst)); 1788 } else if (inst_cream->S) {
1789 UPDATE_NFLAG(RD);
1790 UPDATE_ZFLAG(RD);
1791 UPDATE_CFLAG_WITH_SC;
1792 }
1793 if (inst_cream->Rd == 15) {
1794 INC_PC(sizeof(bic_inst));
1420 goto DISPATCH; 1795 goto DISPATCH;
1421 } 1796 }
1422 cpu->Reg[15] += cpu->GetInstructionSize(); 1797 }
1798 cpu->Reg[15] += cpu->GetInstructionSize();
1799 INC_PC(sizeof(bic_inst));
1800 FETCH_INST;
1801 GOTO_NEXT_INST;
1802}
1803BKPT_INST : {
1804 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1805 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
1806 LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
1807 }
1808 cpu->Reg[15] += cpu->GetInstructionSize();
1809 INC_PC(sizeof(bkpt_inst));
1810 FETCH_INST;
1811 GOTO_NEXT_INST;
1812}
1813BLX_INST : {
1814 blx_inst* inst_cream = (blx_inst*)inst_base->component;
1815 if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
1816 unsigned int inst = inst_cream->inst;
1817 if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
1818 const u32 jump_address = cpu->Reg[inst_cream->val.Rm];
1819 cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
1820 if (cpu->TFlag)
1821 cpu->Reg[14] |= 0x1;
1822 cpu->Reg[15] = jump_address & 0xfffffffe;
1823 cpu->TFlag = jump_address & 0x1;
1824 } else {
1825 cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
1826 cpu->TFlag = 0x1;
1827 int signed_int = inst_cream->val.signed_immed_24;
1828 signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int;
1829 signed_int = signed_int << 2;
1830 cpu->Reg[15] = cpu->Reg[15] + 8 + signed_int + (BIT(inst, 24) << 1);
1831 }
1423 INC_PC(sizeof(blx_inst)); 1832 INC_PC(sizeof(blx_inst));
1424 goto DISPATCH; 1833 goto DISPATCH;
1425 } 1834 }
1835 cpu->Reg[15] += cpu->GetInstructionSize();
1836 INC_PC(sizeof(blx_inst));
1837 goto DISPATCH;
1838}
1426 1839
1427 BX_INST: 1840BX_INST:
1428 BXJ_INST: 1841BXJ_INST : {
1429 { 1842 // Note that only the 'fail' case of BXJ is emulated. This is because
1430 // Note that only the 'fail' case of BXJ is emulated. This is because 1843 // the facilities for Jazelle emulation are not implemented.
1431 // the facilities for Jazelle emulation are not implemented. 1844 //
1432 // 1845 // According to the ARM documentation on BXJ, if setting the J bit in the APSR
1433 // According to the ARM documentation on BXJ, if setting the J bit in the APSR 1846 // fails, then BXJ functions identically like a regular BX instruction.
1434 // fails, then BXJ functions identically like a regular BX instruction. 1847 //
1435 // 1848 // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle.
1436 // This is sufficient for citra, as the CPU for the 3DS does not implement Jazelle.
1437
1438 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1439 bx_inst* const inst_cream = (bx_inst*)inst_base->component;
1440 1849
1441 u32 address = RM; 1850 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1851 bx_inst* const inst_cream = (bx_inst*)inst_base->component;
1442 1852
1443 if (inst_cream->Rm == 15) 1853 u32 address = RM;
1444 address += 2 * cpu->GetInstructionSize();
1445 1854
1446 cpu->TFlag = address & 1; 1855 if (inst_cream->Rm == 15)
1447 cpu->Reg[15] = address & 0xfffffffe; 1856 address += 2 * cpu->GetInstructionSize();
1448 INC_PC(sizeof(bx_inst));
1449 goto DISPATCH;
1450 }
1451 1857
1452 cpu->Reg[15] += cpu->GetInstructionSize(); 1858 cpu->TFlag = address & 1;
1859 cpu->Reg[15] = address & 0xfffffffe;
1453 INC_PC(sizeof(bx_inst)); 1860 INC_PC(sizeof(bx_inst));
1454 goto DISPATCH; 1861 goto DISPATCH;
1455 } 1862 }
1456 1863
1457 CDP_INST: 1864 cpu->Reg[15] += cpu->GetInstructionSize();
1458 { 1865 INC_PC(sizeof(bx_inst));
1459 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1866 goto DISPATCH;
1460 // Undefined instruction here 1867}
1461 cpu->NumInstrsToExecute = 0; 1868
1462 return num_instrs; 1869CDP_INST : {
1870 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1871 // Undefined instruction here
1872 cpu->NumInstrsToExecute = 0;
1873 return num_instrs;
1874 }
1875 cpu->Reg[15] += cpu->GetInstructionSize();
1876 INC_PC(sizeof(cdp_inst));
1877 FETCH_INST;
1878 GOTO_NEXT_INST;
1879}
1880
1881CLREX_INST : {
1882 cpu->UnsetExclusiveMemoryAddress();
1883 cpu->Reg[15] += cpu->GetInstructionSize();
1884 INC_PC(sizeof(clrex_inst));
1885 FETCH_INST;
1886 GOTO_NEXT_INST;
1887}
1888CLZ_INST : {
1889 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1890 clz_inst* inst_cream = (clz_inst*)inst_base->component;
1891 RD = clz(RM);
1892 }
1893 cpu->Reg[15] += cpu->GetInstructionSize();
1894 INC_PC(sizeof(clz_inst));
1895 FETCH_INST;
1896 GOTO_NEXT_INST;
1897}
1898CMN_INST : {
1899 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1900 cmn_inst* const inst_cream = (cmn_inst*)inst_base->component;
1901
1902 u32 rn_val = RN;
1903 if (inst_cream->Rn == 15)
1904 rn_val += 2 * cpu->GetInstructionSize();
1905
1906 bool carry;
1907 bool overflow;
1908 u32 result = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
1909
1910 UPDATE_NFLAG(result);
1911 UPDATE_ZFLAG(result);
1912 cpu->CFlag = carry;
1913 cpu->VFlag = overflow;
1914 }
1915 cpu->Reg[15] += cpu->GetInstructionSize();
1916 INC_PC(sizeof(cmn_inst));
1917 FETCH_INST;
1918 GOTO_NEXT_INST;
1919}
1920CMP_INST : {
1921 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1922 cmp_inst* const inst_cream = (cmp_inst*)inst_base->component;
1923
1924 u32 rn_val = RN;
1925 if (inst_cream->Rn == 15)
1926 rn_val += 2 * cpu->GetInstructionSize();
1927
1928 bool carry;
1929 bool overflow;
1930 u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
1931
1932 UPDATE_NFLAG(result);
1933 UPDATE_ZFLAG(result);
1934 cpu->CFlag = carry;
1935 cpu->VFlag = overflow;
1936 }
1937 cpu->Reg[15] += cpu->GetInstructionSize();
1938 INC_PC(sizeof(cmp_inst));
1939 FETCH_INST;
1940 GOTO_NEXT_INST;
1941}
1942CPS_INST : {
1943 cps_inst* inst_cream = (cps_inst*)inst_base->component;
1944 u32 aif_val = 0;
1945 u32 aif_mask = 0;
1946 if (cpu->InAPrivilegedMode()) {
1947 if (inst_cream->imod1) {
1948 if (inst_cream->A) {
1949 aif_val |= (inst_cream->imod0 << 8);
1950 aif_mask |= 1 << 8;
1951 }
1952 if (inst_cream->I) {
1953 aif_val |= (inst_cream->imod0 << 7);
1954 aif_mask |= 1 << 7;
1955 }
1956 if (inst_cream->F) {
1957 aif_val |= (inst_cream->imod0 << 6);
1958 aif_mask |= 1 << 6;
1959 }
1960 aif_mask = ~aif_mask;
1961 cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val;
1463 } 1962 }
1464 cpu->Reg[15] += cpu->GetInstructionSize(); 1963 if (inst_cream->mmod) {
1465 INC_PC(sizeof(cdp_inst)); 1964 cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode;
1466 FETCH_INST; 1965 cpu->ChangePrivilegeMode(inst_cream->mode);
1467 GOTO_NEXT_INST;
1468 }
1469
1470 CLREX_INST:
1471 {
1472 cpu->UnsetExclusiveMemoryAddress();
1473 cpu->Reg[15] += cpu->GetInstructionSize();
1474 INC_PC(sizeof(clrex_inst));
1475 FETCH_INST;
1476 GOTO_NEXT_INST;
1477 }
1478 CLZ_INST:
1479 {
1480 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1481 clz_inst* inst_cream = (clz_inst*)inst_base->component;
1482 RD = clz(RM);
1483 } 1966 }
1484 cpu->Reg[15] += cpu->GetInstructionSize(); 1967 }
1485 INC_PC(sizeof(clz_inst)); 1968 cpu->Reg[15] += cpu->GetInstructionSize();
1486 FETCH_INST; 1969 INC_PC(sizeof(cps_inst));
1487 GOTO_NEXT_INST; 1970 FETCH_INST;
1488 } 1971 GOTO_NEXT_INST;
1489 CMN_INST: 1972}
1490 { 1973CPY_INST : {
1491 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1974 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1492 cmn_inst* const inst_cream = (cmn_inst*)inst_base->component; 1975 mov_inst* inst_cream = (mov_inst*)inst_base->component;
1493 1976
1494 u32 rn_val = RN; 1977 RD = SHIFTER_OPERAND;
1495 if (inst_cream->Rn == 15) 1978 if (inst_cream->Rd == 15) {
1496 rn_val += 2 * cpu->GetInstructionSize(); 1979 INC_PC(sizeof(mov_inst));
1497 1980 goto DISPATCH;
1498 bool carry;
1499 bool overflow;
1500 u32 result = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
1501
1502 UPDATE_NFLAG(result);
1503 UPDATE_ZFLAG(result);
1504 cpu->CFlag = carry;
1505 cpu->VFlag = overflow;
1506 } 1981 }
1507 cpu->Reg[15] += cpu->GetInstructionSize(); 1982 }
1508 INC_PC(sizeof(cmn_inst)); 1983 cpu->Reg[15] += cpu->GetInstructionSize();
1509 FETCH_INST; 1984 INC_PC(sizeof(mov_inst));
1510 GOTO_NEXT_INST; 1985 FETCH_INST;
1511 } 1986 GOTO_NEXT_INST;
1512 CMP_INST: 1987}
1513 { 1988EOR_INST : {
1514 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 1989 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1515 cmp_inst* const inst_cream = (cmp_inst*)inst_base->component; 1990 eor_inst* inst_cream = (eor_inst*)inst_base->component;
1516 1991
1517 u32 rn_val = RN; 1992 u32 lop = RN;
1518 if (inst_cream->Rn == 15) 1993 if (inst_cream->Rn == 15) {
1519 rn_val += 2 * cpu->GetInstructionSize(); 1994 lop += 2 * cpu->GetInstructionSize();
1520
1521 bool carry;
1522 bool overflow;
1523 u32 result = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
1524
1525 UPDATE_NFLAG(result);
1526 UPDATE_ZFLAG(result);
1527 cpu->CFlag = carry;
1528 cpu->VFlag = overflow;
1529 } 1995 }
1530 cpu->Reg[15] += cpu->GetInstructionSize(); 1996 u32 rop = SHIFTER_OPERAND;
1531 INC_PC(sizeof(cmp_inst)); 1997 RD = lop ^ rop;
1532 FETCH_INST; 1998 if (inst_cream->S && (inst_cream->Rd == 15)) {
1533 GOTO_NEXT_INST; 1999 if (CurrentModeHasSPSR) {
1534 } 2000 cpu->Cpsr = cpu->Spsr_copy;
1535 CPS_INST: 2001 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
1536 { 2002 LOAD_NZCVT;
1537 cps_inst *inst_cream = (cps_inst *)inst_base->component;
1538 u32 aif_val = 0;
1539 u32 aif_mask = 0;
1540 if (cpu->InAPrivilegedMode()) {
1541 if (inst_cream->imod1) {
1542 if (inst_cream->A) {
1543 aif_val |= (inst_cream->imod0 << 8);
1544 aif_mask |= 1 << 8;
1545 }
1546 if (inst_cream->I) {
1547 aif_val |= (inst_cream->imod0 << 7);
1548 aif_mask |= 1 << 7;
1549 }
1550 if (inst_cream->F) {
1551 aif_val |= (inst_cream->imod0 << 6);
1552 aif_mask |= 1 << 6;
1553 }
1554 aif_mask = ~aif_mask;
1555 cpu->Cpsr = (cpu->Cpsr & aif_mask) | aif_val;
1556 }
1557 if (inst_cream->mmod) {
1558 cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode;
1559 cpu->ChangePrivilegeMode(inst_cream->mode);
1560 } 2003 }
2004 } else if (inst_cream->S) {
2005 UPDATE_NFLAG(RD);
2006 UPDATE_ZFLAG(RD);
2007 UPDATE_CFLAG_WITH_SC;
2008 }
2009 if (inst_cream->Rd == 15) {
2010 INC_PC(sizeof(eor_inst));
2011 goto DISPATCH;
1561 } 2012 }
1562 cpu->Reg[15] += cpu->GetInstructionSize();
1563 INC_PC(sizeof(cps_inst));
1564 FETCH_INST;
1565 GOTO_NEXT_INST;
1566 } 2013 }
1567 CPY_INST: 2014 cpu->Reg[15] += cpu->GetInstructionSize();
1568 { 2015 INC_PC(sizeof(eor_inst));
1569 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2016 FETCH_INST;
1570 mov_inst* inst_cream = (mov_inst*)inst_base->component; 2017 GOTO_NEXT_INST;
2018}
2019LDC_INST : {
2020 // Instruction not implemented
2021 // LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
2022 cpu->Reg[15] += cpu->GetInstructionSize();
2023 INC_PC(sizeof(ldc_inst));
2024 FETCH_INST;
2025 GOTO_NEXT_INST;
2026}
2027LDM_INST : {
2028 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2029 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2030 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1571 2031
1572 RD = SHIFTER_OPERAND; 2032 unsigned int inst = inst_cream->inst;
1573 if (inst_cream->Rd == 15) { 2033 if (BIT(inst, 22) && !BIT(inst, 15)) {
1574 INC_PC(sizeof(mov_inst)); 2034 for (int i = 0; i < 13; i++) {
1575 goto DISPATCH; 2035 if (BIT(inst, i)) {
1576 } 2036 cpu->Reg[i] = cpu->ReadMemory32(addr);
1577 } 2037 addr += 4;
1578 cpu->Reg[15] += cpu->GetInstructionSize();
1579 INC_PC(sizeof(mov_inst));
1580 FETCH_INST;
1581 GOTO_NEXT_INST;
1582 }
1583 EOR_INST:
1584 {
1585 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1586 eor_inst* inst_cream = (eor_inst*)inst_base->component;
1587
1588 u32 lop = RN;
1589 if (inst_cream->Rn == 15) {
1590 lop += 2 * cpu->GetInstructionSize();
1591 }
1592 u32 rop = SHIFTER_OPERAND;
1593 RD = lop ^ rop;
1594 if (inst_cream->S && (inst_cream->Rd == 15)) {
1595 if (CurrentModeHasSPSR) {
1596 cpu->Cpsr = cpu->Spsr_copy;
1597 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
1598 LOAD_NZCVT;
1599 } 2038 }
1600 } else if (inst_cream->S) {
1601 UPDATE_NFLAG(RD);
1602 UPDATE_ZFLAG(RD);
1603 UPDATE_CFLAG_WITH_SC;
1604 } 2039 }
1605 if (inst_cream->Rd == 15) { 2040 if (BIT(inst, 13)) {
1606 INC_PC(sizeof(eor_inst)); 2041 if (cpu->Mode == USER32MODE)
1607 goto DISPATCH; 2042 cpu->Reg[13] = cpu->ReadMemory32(addr);
2043 else
2044 cpu->Reg_usr[0] = cpu->ReadMemory32(addr);
2045
2046 addr += 4;
1608 } 2047 }
1609 } 2048 if (BIT(inst, 14)) {
1610 cpu->Reg[15] += cpu->GetInstructionSize(); 2049 if (cpu->Mode == USER32MODE)
1611 INC_PC(sizeof(eor_inst)); 2050 cpu->Reg[14] = cpu->ReadMemory32(addr);
1612 FETCH_INST; 2051 else
1613 GOTO_NEXT_INST; 2052 cpu->Reg_usr[1] = cpu->ReadMemory32(addr);
1614 } 2053
1615 LDC_INST: 2054 addr += 4;
1616 { 2055 }
1617 // Instruction not implemented 2056 } else if (!BIT(inst, 22)) {
1618 //LOG_CRITICAL(Core_ARM11, "unimplemented instruction"); 2057 for (int i = 0; i < 16; i++) {
1619 cpu->Reg[15] += cpu->GetInstructionSize(); 2058 if (BIT(inst, i)) {
1620 INC_PC(sizeof(ldc_inst)); 2059 unsigned int ret = cpu->ReadMemory32(addr);
1621 FETCH_INST; 2060
1622 GOTO_NEXT_INST; 2061 // For armv5t, should enter thumb when bits[0] is non-zero.
1623 } 2062 if (i == 15) {
1624 LDM_INST: 2063 cpu->TFlag = ret & 0x1;
1625 { 2064 ret &= 0xFFFFFFFE;
1626 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1627 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1628 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1629
1630 unsigned int inst = inst_cream->inst;
1631 if (BIT(inst, 22) && !BIT(inst, 15)) {
1632 for (int i = 0; i < 13; i++) {
1633 if(BIT(inst, i)) {
1634 cpu->Reg[i] = cpu->ReadMemory32(addr);
1635 addr += 4;
1636 } 2065 }
1637 }
1638 if (BIT(inst, 13)) {
1639 if (cpu->Mode == USER32MODE)
1640 cpu->Reg[13] = cpu->ReadMemory32(addr);
1641 else
1642 cpu->Reg_usr[0] = cpu->ReadMemory32(addr);
1643 2066
2067 cpu->Reg[i] = ret;
1644 addr += 4; 2068 addr += 4;
1645 } 2069 }
1646 if (BIT(inst, 14)) { 2070 }
1647 if (cpu->Mode == USER32MODE) 2071 } else if (BIT(inst, 22) && BIT(inst, 15)) {
1648 cpu->Reg[14] = cpu->ReadMemory32(addr); 2072 for (int i = 0; i < 15; i++) {
1649 else 2073 if (BIT(inst, i)) {
1650 cpu->Reg_usr[1] = cpu->ReadMemory32(addr); 2074 cpu->Reg[i] = cpu->ReadMemory32(addr);
1651
1652 addr += 4; 2075 addr += 4;
1653 } 2076 }
1654 } else if (!BIT(inst, 22)) {
1655 for(int i = 0; i < 16; i++ ){
1656 if(BIT(inst, i)){
1657 unsigned int ret = cpu->ReadMemory32(addr);
1658
1659 // For armv5t, should enter thumb when bits[0] is non-zero.
1660 if(i == 15){
1661 cpu->TFlag = ret & 0x1;
1662 ret &= 0xFFFFFFFE;
1663 }
1664
1665 cpu->Reg[i] = ret;
1666 addr += 4;
1667 }
1668 }
1669 } else if (BIT(inst, 22) && BIT(inst, 15)) {
1670 for(int i = 0; i < 15; i++ ){
1671 if(BIT(inst, i)){
1672 cpu->Reg[i] = cpu->ReadMemory32(addr);
1673 addr += 4;
1674 }
1675 }
1676
1677 if (CurrentModeHasSPSR) {
1678 cpu->Cpsr = cpu->Spsr_copy;
1679 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
1680 LOAD_NZCVT;
1681 }
1682
1683 cpu->Reg[15] = cpu->ReadMemory32(addr);
1684 } 2077 }
1685 2078
1686 if (BIT(inst, 15)) { 2079 if (CurrentModeHasSPSR) {
1687 INC_PC(sizeof(ldst_inst)); 2080 cpu->Cpsr = cpu->Spsr_copy;
1688 goto DISPATCH; 2081 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
2082 LOAD_NZCVT;
1689 } 2083 }
2084
2085 cpu->Reg[15] = cpu->ReadMemory32(addr);
2086 }
2087
2088 if (BIT(inst, 15)) {
2089 INC_PC(sizeof(ldst_inst));
2090 goto DISPATCH;
1690 } 2091 }
1691 cpu->Reg[15] += cpu->GetInstructionSize();
1692 INC_PC(sizeof(ldst_inst));
1693 FETCH_INST;
1694 GOTO_NEXT_INST;
1695 } 2092 }
1696 SXTH_INST: 2093 cpu->Reg[15] += cpu->GetInstructionSize();
1697 { 2094 INC_PC(sizeof(ldst_inst));
1698 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2095 FETCH_INST;
1699 sxth_inst* inst_cream = (sxth_inst*)inst_base->component; 2096 GOTO_NEXT_INST;
2097}
2098SXTH_INST : {
2099 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2100 sxth_inst* inst_cream = (sxth_inst*)inst_base->component;
1700 2101
1701 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); 2102 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
1702 if (BIT(operand2, 15)) { 2103 if (BIT(operand2, 15)) {
1703 operand2 |= 0xffff0000; 2104 operand2 |= 0xffff0000;
1704 } else { 2105 } else {
1705 operand2 &= 0xffff; 2106 operand2 &= 0xffff;
1706 }
1707 RD = operand2;
1708 } 2107 }
1709 cpu->Reg[15] += cpu->GetInstructionSize(); 2108 RD = operand2;
1710 INC_PC(sizeof(sxth_inst)); 2109 }
1711 FETCH_INST; 2110 cpu->Reg[15] += cpu->GetInstructionSize();
1712 GOTO_NEXT_INST; 2111 INC_PC(sizeof(sxth_inst));
1713 } 2112 FETCH_INST;
1714 LDR_INST: 2113 GOTO_NEXT_INST;
1715 { 2114}
1716 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 2115LDR_INST : {
2116 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2117 inst_cream->get_addr(cpu, inst_cream->inst, addr);
2118
2119 unsigned int value = cpu->ReadMemory32(addr);
2120 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
2121
2122 if (BITS(inst_cream->inst, 12, 15) == 15) {
2123 // For armv5t, should enter thumb when bits[0] is non-zero.
2124 cpu->TFlag = value & 0x1;
2125 cpu->Reg[15] &= 0xFFFFFFFE;
2126 INC_PC(sizeof(ldst_inst));
2127 goto DISPATCH;
2128 }
2129
2130 cpu->Reg[15] += cpu->GetInstructionSize();
2131 INC_PC(sizeof(ldst_inst));
2132 FETCH_INST;
2133 GOTO_NEXT_INST;
2134}
2135LDRCOND_INST : {
2136 if (CondPassed(cpu, inst_base->cond)) {
2137 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1717 inst_cream->get_addr(cpu, inst_cream->inst, addr); 2138 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1718 2139
1719 unsigned int value = cpu->ReadMemory32(addr); 2140 unsigned int value = cpu->ReadMemory32(addr);
@@ -1726,2546 +2147,2433 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
1726 INC_PC(sizeof(ldst_inst)); 2147 INC_PC(sizeof(ldst_inst));
1727 goto DISPATCH; 2148 goto DISPATCH;
1728 } 2149 }
2150 }
2151 cpu->Reg[15] += cpu->GetInstructionSize();
2152 INC_PC(sizeof(ldst_inst));
2153 FETCH_INST;
2154 GOTO_NEXT_INST;
2155}
2156UXTH_INST : {
2157 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2158 uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
2159 RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
2160 }
2161 cpu->Reg[15] += cpu->GetInstructionSize();
2162 INC_PC(sizeof(uxth_inst));
2163 FETCH_INST;
2164 GOTO_NEXT_INST;
2165}
2166UXTAH_INST : {
2167 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2168 uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component;
2169 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
1729 2170
1730 cpu->Reg[15] += cpu->GetInstructionSize(); 2171 RD = RN + operand2;
1731 INC_PC(sizeof(ldst_inst)); 2172 }
1732 FETCH_INST; 2173 cpu->Reg[15] += cpu->GetInstructionSize();
1733 GOTO_NEXT_INST; 2174 INC_PC(sizeof(uxtah_inst));
1734 } 2175 FETCH_INST;
1735 LDRCOND_INST: 2176 GOTO_NEXT_INST;
1736 { 2177}
1737 if (CondPassed(cpu, inst_base->cond)) { 2178LDRB_INST : {
1738 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 2179 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1739 inst_cream->get_addr(cpu, inst_cream->inst, addr); 2180 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1740 2181 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1741 unsigned int value = cpu->ReadMemory32(addr); 2182
1742 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 2183 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
1743
1744 if (BITS(inst_cream->inst, 12, 15) == 15) {
1745 // For armv5t, should enter thumb when bits[0] is non-zero.
1746 cpu->TFlag = value & 0x1;
1747 cpu->Reg[15] &= 0xFFFFFFFE;
1748 INC_PC(sizeof(ldst_inst));
1749 goto DISPATCH;
1750 }
1751 }
1752 cpu->Reg[15] += cpu->GetInstructionSize();
1753 INC_PC(sizeof(ldst_inst));
1754 FETCH_INST;
1755 GOTO_NEXT_INST;
1756 }
1757 UXTH_INST:
1758 {
1759 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1760 uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
1761 RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
1762 }
1763 cpu->Reg[15] += cpu->GetInstructionSize();
1764 INC_PC(sizeof(uxth_inst));
1765 FETCH_INST;
1766 GOTO_NEXT_INST;
1767 }
1768 UXTAH_INST:
1769 {
1770 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1771 uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component;
1772 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
1773
1774 RD = RN + operand2;
1775 }
1776 cpu->Reg[15] += cpu->GetInstructionSize();
1777 INC_PC(sizeof(uxtah_inst));
1778 FETCH_INST;
1779 GOTO_NEXT_INST;
1780 }
1781 LDRB_INST:
1782 {
1783 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1784 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1785 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1786
1787 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
1788 }
1789 cpu->Reg[15] += cpu->GetInstructionSize();
1790 INC_PC(sizeof(ldst_inst));
1791 FETCH_INST;
1792 GOTO_NEXT_INST;
1793 } 2184 }
1794 LDRBT_INST: 2185 cpu->Reg[15] += cpu->GetInstructionSize();
1795 { 2186 INC_PC(sizeof(ldst_inst));
1796 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2187 FETCH_INST;
1797 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 2188 GOTO_NEXT_INST;
1798 inst_cream->get_addr(cpu, inst_cream->inst, addr); 2189}
2190LDRBT_INST : {
2191 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2192 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2193 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1799 2194
1800 const u32 dest_index = BITS(inst_cream->inst, 12, 15); 2195 const u32 dest_index = BITS(inst_cream->inst, 12, 15);
1801 const u32 previous_mode = cpu->Mode; 2196 const u32 previous_mode = cpu->Mode;
1802 2197
1803 cpu->ChangePrivilegeMode(USER32MODE); 2198 cpu->ChangePrivilegeMode(USER32MODE);
1804 const u8 value = cpu->ReadMemory8(addr); 2199 const u8 value = cpu->ReadMemory8(addr);
1805 cpu->ChangePrivilegeMode(previous_mode); 2200 cpu->ChangePrivilegeMode(previous_mode);
1806 2201
1807 cpu->Reg[dest_index] = value; 2202 cpu->Reg[dest_index] = value;
1808 }
1809 cpu->Reg[15] += cpu->GetInstructionSize();
1810 INC_PC(sizeof(ldst_inst));
1811 FETCH_INST;
1812 GOTO_NEXT_INST;
1813 }
1814 LDRD_INST:
1815 {
1816 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1817 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1818 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
1819 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1820
1821 // The 3DS doesn't have LPAE (Large Physical Access Extension), so it
1822 // wouldn't do this as a single read.
1823 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr);
1824 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4);
1825
1826 // No dispatch since this operation should not modify R15
1827 }
1828 cpu->Reg[15] += 4;
1829 INC_PC(sizeof(ldst_inst));
1830 FETCH_INST;
1831 GOTO_NEXT_INST;
1832 } 2203 }
2204 cpu->Reg[15] += cpu->GetInstructionSize();
2205 INC_PC(sizeof(ldst_inst));
2206 FETCH_INST;
2207 GOTO_NEXT_INST;
2208}
2209LDRD_INST : {
2210 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2211 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2212 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 ||
2213 // addr[2] == 0)
2214 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1833 2215
1834 LDREX_INST: 2216 // The 3DS doesn't have LPAE (Large Physical Access Extension), so it
1835 { 2217 // wouldn't do this as a single read.
1836 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2218 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr);
1837 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; 2219 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4);
1838 unsigned int read_addr = RN;
1839
1840 cpu->SetExclusiveMemoryAddress(read_addr);
1841 2220
1842 RD = cpu->ReadMemory32(read_addr); 2221 // No dispatch since this operation should not modify R15
1843 }
1844 cpu->Reg[15] += cpu->GetInstructionSize();
1845 INC_PC(sizeof(generic_arm_inst));
1846 FETCH_INST;
1847 GOTO_NEXT_INST;
1848 } 2222 }
1849 LDREXB_INST: 2223 cpu->Reg[15] += 4;
1850 { 2224 INC_PC(sizeof(ldst_inst));
1851 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2225 FETCH_INST;
1852 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; 2226 GOTO_NEXT_INST;
1853 unsigned int read_addr = RN; 2227}
1854 2228
1855 cpu->SetExclusiveMemoryAddress(read_addr); 2229LDREX_INST : {
2230 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2231 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
2232 unsigned int read_addr = RN;
1856 2233
1857 RD = cpu->ReadMemory8(read_addr); 2234 cpu->SetExclusiveMemoryAddress(read_addr);
1858 } 2235
1859 cpu->Reg[15] += cpu->GetInstructionSize(); 2236 RD = cpu->ReadMemory32(read_addr);
1860 INC_PC(sizeof(generic_arm_inst));
1861 FETCH_INST;
1862 GOTO_NEXT_INST;
1863 } 2237 }
1864 LDREXH_INST: 2238 cpu->Reg[15] += cpu->GetInstructionSize();
1865 { 2239 INC_PC(sizeof(generic_arm_inst));
1866 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2240 FETCH_INST;
1867 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; 2241 GOTO_NEXT_INST;
1868 unsigned int read_addr = RN; 2242}
2243LDREXB_INST : {
2244 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2245 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
2246 unsigned int read_addr = RN;
1869 2247
1870 cpu->SetExclusiveMemoryAddress(read_addr); 2248 cpu->SetExclusiveMemoryAddress(read_addr);
1871 2249
1872 RD = cpu->ReadMemory16(read_addr); 2250 RD = cpu->ReadMemory8(read_addr);
1873 }
1874 cpu->Reg[15] += cpu->GetInstructionSize();
1875 INC_PC(sizeof(generic_arm_inst));
1876 FETCH_INST;
1877 GOTO_NEXT_INST;
1878 } 2251 }
1879 LDREXD_INST: 2252 cpu->Reg[15] += cpu->GetInstructionSize();
1880 { 2253 INC_PC(sizeof(generic_arm_inst));
1881 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2254 FETCH_INST;
1882 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; 2255 GOTO_NEXT_INST;
1883 unsigned int read_addr = RN; 2256}
2257LDREXH_INST : {
2258 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2259 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
2260 unsigned int read_addr = RN;
1884 2261
1885 cpu->SetExclusiveMemoryAddress(read_addr); 2262 cpu->SetExclusiveMemoryAddress(read_addr);
1886 2263
1887 RD = cpu->ReadMemory32(read_addr); 2264 RD = cpu->ReadMemory16(read_addr);
1888 RD2 = cpu->ReadMemory32(read_addr + 4);
1889 }
1890 cpu->Reg[15] += cpu->GetInstructionSize();
1891 INC_PC(sizeof(generic_arm_inst));
1892 FETCH_INST;
1893 GOTO_NEXT_INST;
1894 }
1895 LDRH_INST:
1896 {
1897 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1898 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1899 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1900
1901 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);
1902 }
1903 cpu->Reg[15] += cpu->GetInstructionSize();
1904 INC_PC(sizeof(ldst_inst));
1905 FETCH_INST;
1906 GOTO_NEXT_INST;
1907 }
1908 LDRSB_INST:
1909 {
1910 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1911 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1912 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1913 unsigned int value = cpu->ReadMemory8(addr);
1914 if (BIT(value, 7)) {
1915 value |= 0xffffff00;
1916 }
1917 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
1918 }
1919 cpu->Reg[15] += cpu->GetInstructionSize();
1920 INC_PC(sizeof(ldst_inst));
1921 FETCH_INST;
1922 GOTO_NEXT_INST;
1923 }
1924 LDRSH_INST:
1925 {
1926 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1927 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1928 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1929
1930 unsigned int value = cpu->ReadMemory16(addr);
1931 if (BIT(value, 15)) {
1932 value |= 0xffff0000;
1933 }
1934 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
1935 }
1936 cpu->Reg[15] += cpu->GetInstructionSize();
1937 INC_PC(sizeof(ldst_inst));
1938 FETCH_INST;
1939 GOTO_NEXT_INST;
1940 } 2265 }
1941 LDRT_INST: 2266 cpu->Reg[15] += cpu->GetInstructionSize();
1942 { 2267 INC_PC(sizeof(generic_arm_inst));
1943 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2268 FETCH_INST;
1944 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 2269 GOTO_NEXT_INST;
1945 inst_cream->get_addr(cpu, inst_cream->inst, addr); 2270}
2271LDREXD_INST : {
2272 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2273 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
2274 unsigned int read_addr = RN;
1946 2275
1947 const u32 dest_index = BITS(inst_cream->inst, 12, 15); 2276 cpu->SetExclusiveMemoryAddress(read_addr);
1948 const u32 previous_mode = cpu->Mode;
1949 2277
1950 cpu->ChangePrivilegeMode(USER32MODE); 2278 RD = cpu->ReadMemory32(read_addr);
1951 const u32 value = cpu->ReadMemory32(addr); 2279 RD2 = cpu->ReadMemory32(read_addr + 4);
1952 cpu->ChangePrivilegeMode(previous_mode); 2280 }
2281 cpu->Reg[15] += cpu->GetInstructionSize();
2282 INC_PC(sizeof(generic_arm_inst));
2283 FETCH_INST;
2284 GOTO_NEXT_INST;
2285}
2286LDRH_INST : {
2287 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2288 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2289 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1953 2290
1954 cpu->Reg[dest_index] = value; 2291 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);
2292 }
2293 cpu->Reg[15] += cpu->GetInstructionSize();
2294 INC_PC(sizeof(ldst_inst));
2295 FETCH_INST;
2296 GOTO_NEXT_INST;
2297}
2298LDRSB_INST : {
2299 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2300 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2301 inst_cream->get_addr(cpu, inst_cream->inst, addr);
2302 unsigned int value = cpu->ReadMemory8(addr);
2303 if (BIT(value, 7)) {
2304 value |= 0xffffff00;
1955 } 2305 }
1956 cpu->Reg[15] += cpu->GetInstructionSize(); 2306 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
1957 INC_PC(sizeof(ldst_inst));
1958 FETCH_INST;
1959 GOTO_NEXT_INST;
1960 } 2307 }
1961 MCR_INST: 2308 cpu->Reg[15] += cpu->GetInstructionSize();
1962 { 2309 INC_PC(sizeof(ldst_inst));
1963 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2310 FETCH_INST;
1964 mcr_inst* inst_cream = (mcr_inst*)inst_base->component; 2311 GOTO_NEXT_INST;
2312}
2313LDRSH_INST : {
2314 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2315 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2316 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1965 2317
1966 unsigned int inst = inst_cream->inst; 2318 unsigned int value = cpu->ReadMemory16(addr);
1967 if (inst_cream->Rd == 15) { 2319 if (BIT(value, 15)) {
1968 DEBUG_MSG; 2320 value |= 0xffff0000;
1969 } else {
1970 if (inst_cream->cp_num == 15)
1971 cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2);
1972 }
1973 } 2321 }
1974 cpu->Reg[15] += cpu->GetInstructionSize(); 2322 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
1975 INC_PC(sizeof(mcr_inst));
1976 FETCH_INST;
1977 GOTO_NEXT_INST;
1978 } 2323 }
2324 cpu->Reg[15] += cpu->GetInstructionSize();
2325 INC_PC(sizeof(ldst_inst));
2326 FETCH_INST;
2327 GOTO_NEXT_INST;
2328}
2329LDRT_INST : {
2330 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2331 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
2332 inst_cream->get_addr(cpu, inst_cream->inst, addr);
1979 2333
1980 MCRR_INST: 2334 const u32 dest_index = BITS(inst_cream->inst, 12, 15);
1981 { 2335 const u32 previous_mode = cpu->Mode;
1982 // Stubbed, as the MPCore doesn't have any registers that are accessible
1983 // through this instruction.
1984 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
1985 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
1986 2336
1987 LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", 2337 cpu->ChangePrivilegeMode(USER32MODE);
1988 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2); 2338 const u32 value = cpu->ReadMemory32(addr);
2339 cpu->ChangePrivilegeMode(previous_mode);
2340
2341 cpu->Reg[dest_index] = value;
2342 }
2343 cpu->Reg[15] += cpu->GetInstructionSize();
2344 INC_PC(sizeof(ldst_inst));
2345 FETCH_INST;
2346 GOTO_NEXT_INST;
2347}
2348MCR_INST : {
2349 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2350 mcr_inst* inst_cream = (mcr_inst*)inst_base->component;
2351
2352 unsigned int inst = inst_cream->inst;
2353 if (inst_cream->Rd == 15) {
2354 DEBUG_MSG;
2355 } else {
2356 if (inst_cream->cp_num == 15)
2357 cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2);
1989 } 2358 }
2359 }
2360 cpu->Reg[15] += cpu->GetInstructionSize();
2361 INC_PC(sizeof(mcr_inst));
2362 FETCH_INST;
2363 GOTO_NEXT_INST;
2364}
2365
2366MCRR_INST : {
2367 // Stubbed, as the MPCore doesn't have any registers that are accessible
2368 // through this instruction.
2369 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2370 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
1990 2371
1991 cpu->Reg[15] += cpu->GetInstructionSize(); 2372 LOG_ERROR(Core_ARM11, "MCRR executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
1992 INC_PC(sizeof(mcrr_inst)); 2373 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
1993 FETCH_INST; 2374 inst_cream->rt2);
1994 GOTO_NEXT_INST;
1995 } 2375 }
1996 2376
1997 MLA_INST: 2377 cpu->Reg[15] += cpu->GetInstructionSize();
1998 { 2378 INC_PC(sizeof(mcrr_inst));
1999 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2379 FETCH_INST;
2000 mla_inst* inst_cream = (mla_inst*)inst_base->component; 2380 GOTO_NEXT_INST;
2381}
2001 2382
2002 u64 rm = RM; 2383MLA_INST : {
2003 u64 rs = RS; 2384 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2004 u64 rn = RN; 2385 mla_inst* inst_cream = (mla_inst*)inst_base->component;
2005 2386
2006 RD = static_cast<u32>((rm * rs + rn) & 0xffffffff); 2387 u64 rm = RM;
2007 if (inst_cream->S) { 2388 u64 rs = RS;
2008 UPDATE_NFLAG(RD); 2389 u64 rn = RN;
2009 UPDATE_ZFLAG(RD); 2390
2010 } 2391 RD = static_cast<u32>((rm * rs + rn) & 0xffffffff);
2392 if (inst_cream->S) {
2393 UPDATE_NFLAG(RD);
2394 UPDATE_ZFLAG(RD);
2011 } 2395 }
2012 cpu->Reg[15] += cpu->GetInstructionSize(); 2396 }
2013 INC_PC(sizeof(mla_inst)); 2397 cpu->Reg[15] += cpu->GetInstructionSize();
2014 FETCH_INST; 2398 INC_PC(sizeof(mla_inst));
2015 GOTO_NEXT_INST; 2399 FETCH_INST;
2016 } 2400 GOTO_NEXT_INST;
2017 MOV_INST: 2401}
2018 { 2402MOV_INST : {
2019 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2403 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2020 mov_inst* inst_cream = (mov_inst*)inst_base->component; 2404 mov_inst* inst_cream = (mov_inst*)inst_base->component;
2021 2405
2022 RD = SHIFTER_OPERAND; 2406 RD = SHIFTER_OPERAND;
2023 if (inst_cream->S && (inst_cream->Rd == 15)) { 2407 if (inst_cream->S && (inst_cream->Rd == 15)) {
2024 if (CurrentModeHasSPSR) { 2408 if (CurrentModeHasSPSR) {
2025 cpu->Cpsr = cpu->Spsr_copy; 2409 cpu->Cpsr = cpu->Spsr_copy;
2026 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 2410 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2027 LOAD_NZCVT; 2411 LOAD_NZCVT;
2028 }
2029 } else if (inst_cream->S) {
2030 UPDATE_NFLAG(RD);
2031 UPDATE_ZFLAG(RD);
2032 UPDATE_CFLAG_WITH_SC;
2033 }
2034 if (inst_cream->Rd == 15) {
2035 INC_PC(sizeof(mov_inst));
2036 goto DISPATCH;
2037 } 2412 }
2413 } else if (inst_cream->S) {
2414 UPDATE_NFLAG(RD);
2415 UPDATE_ZFLAG(RD);
2416 UPDATE_CFLAG_WITH_SC;
2038 } 2417 }
2039 cpu->Reg[15] += cpu->GetInstructionSize(); 2418 if (inst_cream->Rd == 15) {
2040 INC_PC(sizeof(mov_inst)); 2419 INC_PC(sizeof(mov_inst));
2041 FETCH_INST; 2420 goto DISPATCH;
2042 GOTO_NEXT_INST;
2043 }
2044 MRC_INST:
2045 {
2046 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2047 mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
2048
2049 if (inst_cream->cp_num == 15) {
2050 const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
2051
2052 if (inst_cream->Rd == 15) {
2053 cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000);
2054 LOAD_NZCVT;
2055 } else {
2056 RD = value;
2057 }
2058 }
2059 } 2421 }
2060 cpu->Reg[15] += cpu->GetInstructionSize();
2061 INC_PC(sizeof(mrc_inst));
2062 FETCH_INST;
2063 GOTO_NEXT_INST;
2064 } 2422 }
2423 cpu->Reg[15] += cpu->GetInstructionSize();
2424 INC_PC(sizeof(mov_inst));
2425 FETCH_INST;
2426 GOTO_NEXT_INST;
2427}
2428MRC_INST : {
2429 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2430 mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
2065 2431
2066 MRRC_INST: 2432 if (inst_cream->cp_num == 15) {
2067 { 2433 const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
2068 // Stubbed, as the MPCore doesn't have any registers that are accessible
2069 // through this instruction.
2070 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2071 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
2072 2434
2073 LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u", 2435 if (inst_cream->Rd == 15) {
2074 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2); 2436 cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000);
2437 LOAD_NZCVT;
2438 } else {
2439 RD = value;
2440 }
2075 } 2441 }
2442 }
2443 cpu->Reg[15] += cpu->GetInstructionSize();
2444 INC_PC(sizeof(mrc_inst));
2445 FETCH_INST;
2446 GOTO_NEXT_INST;
2447}
2076 2448
2077 cpu->Reg[15] += cpu->GetInstructionSize(); 2449MRRC_INST : {
2078 INC_PC(sizeof(mcrr_inst)); 2450 // Stubbed, as the MPCore doesn't have any registers that are accessible
2079 FETCH_INST; 2451 // through this instruction.
2080 GOTO_NEXT_INST; 2452 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2453 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
2454
2455 LOG_ERROR(Core_ARM11, "MRRC executed | Coprocessor: %u, CRm %u, opc1: %u, Rt: %u, Rt2: %u",
2456 inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt,
2457 inst_cream->rt2);
2081 } 2458 }
2082 2459
2083 MRS_INST: 2460 cpu->Reg[15] += cpu->GetInstructionSize();
2084 { 2461 INC_PC(sizeof(mcrr_inst));
2085 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2462 FETCH_INST;
2086 mrs_inst* inst_cream = (mrs_inst*)inst_base->component; 2463 GOTO_NEXT_INST;
2464}
2087 2465
2088 if (inst_cream->R) { 2466MRS_INST : {
2089 RD = cpu->Spsr_copy; 2467 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2090 } else { 2468 mrs_inst* inst_cream = (mrs_inst*)inst_base->component;
2091 SAVE_NZCVT; 2469
2092 RD = cpu->Cpsr; 2470 if (inst_cream->R) {
2093 } 2471 RD = cpu->Spsr_copy;
2472 } else {
2473 SAVE_NZCVT;
2474 RD = cpu->Cpsr;
2475 }
2476 }
2477 cpu->Reg[15] += cpu->GetInstructionSize();
2478 INC_PC(sizeof(mrs_inst));
2479 FETCH_INST;
2480 GOTO_NEXT_INST;
2481}
2482MSR_INST : {
2483 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2484 msr_inst* inst_cream = (msr_inst*)inst_base->component;
2485 const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
2486 unsigned int inst = inst_cream->inst;
2487 unsigned int operand;
2488
2489 if (BIT(inst, 25)) {
2490 int rot_imm = BITS(inst, 8, 11) * 2;
2491 operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm);
2492 } else {
2493 operand = cpu->Reg[BITS(inst, 0, 3)];
2094 } 2494 }
2095 cpu->Reg[15] += cpu->GetInstructionSize(); 2495 u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) |
2096 INC_PC(sizeof(mrs_inst)); 2496 (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
2097 FETCH_INST; 2497 u32 mask = 0;
2098 GOTO_NEXT_INST; 2498 if (!inst_cream->R) {
2099 } 2499 if (cpu->InAPrivilegedMode()) {
2100 MSR_INST: 2500 if ((operand & StateMask) != 0) {
2101 { 2501 /// UNPREDICTABLE
2102 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2502 DEBUG_MSG;
2103 msr_inst* inst_cream = (msr_inst*)inst_base->component; 2503 } else
2104 const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; 2504 mask = byte_mask & (UserMask | PrivMask);
2105 unsigned int inst = inst_cream->inst;
2106 unsigned int operand;
2107
2108 if (BIT(inst, 25)) {
2109 int rot_imm = BITS(inst, 8, 11) * 2;
2110 operand = ROTATE_RIGHT_32(BITS(inst, 0, 7), rot_imm);
2111 } else { 2505 } else {
2112 operand = cpu->Reg[BITS(inst, 0, 3)]; 2506 mask = byte_mask & UserMask;
2113 } 2507 }
2114 u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0) 2508 SAVE_NZCVT;
2115 | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
2116 u32 mask = 0;
2117 if (!inst_cream->R) {
2118 if (cpu->InAPrivilegedMode()) {
2119 if ((operand & StateMask) != 0) {
2120 /// UNPREDICTABLE
2121 DEBUG_MSG;
2122 } else
2123 mask = byte_mask & (UserMask | PrivMask);
2124 } else {
2125 mask = byte_mask & UserMask;
2126 }
2127 SAVE_NZCVT;
2128 2509
2129 cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask); 2510 cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask);
2130 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); 2511 cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
2131 LOAD_NZCVT; 2512 LOAD_NZCVT;
2132 } else { 2513 } else {
2133 if (CurrentModeHasSPSR) { 2514 if (CurrentModeHasSPSR) {
2134 mask = byte_mask & (UserMask | PrivMask | StateMask); 2515 mask = byte_mask & (UserMask | PrivMask | StateMask);
2135 cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); 2516 cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask);
2136 }
2137 } 2517 }
2138 } 2518 }
2139 cpu->Reg[15] += cpu->GetInstructionSize(); 2519 }
2140 INC_PC(sizeof(msr_inst)); 2520 cpu->Reg[15] += cpu->GetInstructionSize();
2141 FETCH_INST; 2521 INC_PC(sizeof(msr_inst));
2142 GOTO_NEXT_INST; 2522 FETCH_INST;
2143 } 2523 GOTO_NEXT_INST;
2144 MUL_INST: 2524}
2145 { 2525MUL_INST : {
2146 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2526 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2147 mul_inst* inst_cream = (mul_inst*)inst_base->component; 2527 mul_inst* inst_cream = (mul_inst*)inst_base->component;
2148 2528
2149 u64 rm = RM; 2529 u64 rm = RM;
2150 u64 rs = RS; 2530 u64 rs = RS;
2151 RD = static_cast<u32>((rm * rs) & 0xffffffff); 2531 RD = static_cast<u32>((rm * rs) & 0xffffffff);
2152 if (inst_cream->S) { 2532 if (inst_cream->S) {
2153 UPDATE_NFLAG(RD); 2533 UPDATE_NFLAG(RD);
2154 UPDATE_ZFLAG(RD); 2534 UPDATE_ZFLAG(RD);
2155 }
2156 } 2535 }
2157 cpu->Reg[15] += cpu->GetInstructionSize(); 2536 }
2158 INC_PC(sizeof(mul_inst)); 2537 cpu->Reg[15] += cpu->GetInstructionSize();
2159 FETCH_INST; 2538 INC_PC(sizeof(mul_inst));
2160 GOTO_NEXT_INST; 2539 FETCH_INST;
2161 } 2540 GOTO_NEXT_INST;
2162 MVN_INST: 2541}
2163 { 2542MVN_INST : {
2164 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2543 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2165 mvn_inst* const inst_cream = (mvn_inst*)inst_base->component; 2544 mvn_inst* const inst_cream = (mvn_inst*)inst_base->component;
2166 2545
2167 RD = ~SHIFTER_OPERAND; 2546 RD = ~SHIFTER_OPERAND;
2168 2547
2169 if (inst_cream->S && (inst_cream->Rd == 15)) { 2548 if (inst_cream->S && (inst_cream->Rd == 15)) {
2170 if (CurrentModeHasSPSR) { 2549 if (CurrentModeHasSPSR) {
2171 cpu->Cpsr = cpu->Spsr_copy; 2550 cpu->Cpsr = cpu->Spsr_copy;
2172 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 2551 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2173 LOAD_NZCVT; 2552 LOAD_NZCVT;
2174 }
2175 } else if (inst_cream->S) {
2176 UPDATE_NFLAG(RD);
2177 UPDATE_ZFLAG(RD);
2178 UPDATE_CFLAG_WITH_SC;
2179 }
2180 if (inst_cream->Rd == 15) {
2181 INC_PC(sizeof(mvn_inst));
2182 goto DISPATCH;
2183 } 2553 }
2554 } else if (inst_cream->S) {
2555 UPDATE_NFLAG(RD);
2556 UPDATE_ZFLAG(RD);
2557 UPDATE_CFLAG_WITH_SC;
2558 }
2559 if (inst_cream->Rd == 15) {
2560 INC_PC(sizeof(mvn_inst));
2561 goto DISPATCH;
2184 } 2562 }
2185 cpu->Reg[15] += cpu->GetInstructionSize();
2186 INC_PC(sizeof(mvn_inst));
2187 FETCH_INST;
2188 GOTO_NEXT_INST;
2189 } 2563 }
2190 ORR_INST: 2564 cpu->Reg[15] += cpu->GetInstructionSize();
2191 { 2565 INC_PC(sizeof(mvn_inst));
2192 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2566 FETCH_INST;
2193 orr_inst* const inst_cream = (orr_inst*)inst_base->component; 2567 GOTO_NEXT_INST;
2568}
2569ORR_INST : {
2570 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2571 orr_inst* const inst_cream = (orr_inst*)inst_base->component;
2194 2572
2195 u32 lop = RN; 2573 u32 lop = RN;
2196 u32 rop = SHIFTER_OPERAND; 2574 u32 rop = SHIFTER_OPERAND;
2197 2575
2198 if (inst_cream->Rn == 15) 2576 if (inst_cream->Rn == 15)
2199 lop += 2 * cpu->GetInstructionSize(); 2577 lop += 2 * cpu->GetInstructionSize();
2200 2578
2201 RD = lop | rop; 2579 RD = lop | rop;
2202 2580
2203 if (inst_cream->S && (inst_cream->Rd == 15)) { 2581 if (inst_cream->S && (inst_cream->Rd == 15)) {
2204 if (CurrentModeHasSPSR) { 2582 if (CurrentModeHasSPSR) {
2205 cpu->Cpsr = cpu->Spsr_copy; 2583 cpu->Cpsr = cpu->Spsr_copy;
2206 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 2584 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2207 LOAD_NZCVT; 2585 LOAD_NZCVT;
2208 }
2209 } else if (inst_cream->S) {
2210 UPDATE_NFLAG(RD);
2211 UPDATE_ZFLAG(RD);
2212 UPDATE_CFLAG_WITH_SC;
2213 }
2214 if (inst_cream->Rd == 15) {
2215 INC_PC(sizeof(orr_inst));
2216 goto DISPATCH;
2217 } 2586 }
2587 } else if (inst_cream->S) {
2588 UPDATE_NFLAG(RD);
2589 UPDATE_ZFLAG(RD);
2590 UPDATE_CFLAG_WITH_SC;
2591 }
2592 if (inst_cream->Rd == 15) {
2593 INC_PC(sizeof(orr_inst));
2594 goto DISPATCH;
2218 } 2595 }
2219 cpu->Reg[15] += cpu->GetInstructionSize();
2220 INC_PC(sizeof(orr_inst));
2221 FETCH_INST;
2222 GOTO_NEXT_INST;
2223 } 2596 }
2597 cpu->Reg[15] += cpu->GetInstructionSize();
2598 INC_PC(sizeof(orr_inst));
2599 FETCH_INST;
2600 GOTO_NEXT_INST;
2601}
2224 2602
2225 NOP_INST: 2603NOP_INST : {
2226 { 2604 cpu->Reg[15] += cpu->GetInstructionSize();
2227 cpu->Reg[15] += cpu->GetInstructionSize(); 2605 INC_PC_STUB;
2228 INC_PC_STUB; 2606 FETCH_INST;
2229 FETCH_INST; 2607 GOTO_NEXT_INST;
2230 GOTO_NEXT_INST; 2608}
2609
2610PKHBT_INST : {
2611 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2612 pkh_inst* inst_cream = (pkh_inst*)inst_base->component;
2613 RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000);
2231 } 2614 }
2615 cpu->Reg[15] += cpu->GetInstructionSize();
2616 INC_PC(sizeof(pkh_inst));
2617 FETCH_INST;
2618 GOTO_NEXT_INST;
2619}
2232 2620
2233 PKHBT_INST: 2621PKHTB_INST : {
2234 { 2622 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2235 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2623 pkh_inst* inst_cream = (pkh_inst*)inst_base->component;
2236 pkh_inst *inst_cream = (pkh_inst *)inst_base->component; 2624 int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
2237 RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000); 2625 RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
2238 } 2626 }
2239 cpu->Reg[15] += cpu->GetInstructionSize(); 2627 cpu->Reg[15] += cpu->GetInstructionSize();
2240 INC_PC(sizeof(pkh_inst)); 2628 INC_PC(sizeof(pkh_inst));
2241 FETCH_INST; 2629 FETCH_INST;
2242 GOTO_NEXT_INST; 2630 GOTO_NEXT_INST;
2243 } 2631}
2244
2245 PKHTB_INST:
2246 {
2247 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2248 pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
2249 int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
2250 RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
2251 }
2252 cpu->Reg[15] += cpu->GetInstructionSize();
2253 INC_PC(sizeof(pkh_inst));
2254 FETCH_INST;
2255 GOTO_NEXT_INST;
2256 }
2257
2258 PLD_INST:
2259 {
2260 // Not implemented. PLD is a hint instruction, so it's optional.
2261
2262 cpu->Reg[15] += cpu->GetInstructionSize();
2263 INC_PC(sizeof(pld_inst));
2264 FETCH_INST;
2265 GOTO_NEXT_INST;
2266 }
2267
2268 QADD_INST:
2269 QDADD_INST:
2270 QDSUB_INST:
2271 QSUB_INST:
2272 {
2273 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2274 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2275 const u8 op1 = inst_cream->op1;
2276 const u32 rm_val = RM;
2277 const u32 rn_val = RN;
2278 2632
2279 u32 result = 0; 2633PLD_INST : {
2634 // Not implemented. PLD is a hint instruction, so it's optional.
2280 2635
2281 // QADD 2636 cpu->Reg[15] += cpu->GetInstructionSize();
2282 if (op1 == 0x00) { 2637 INC_PC(sizeof(pld_inst));
2283 result = rm_val + rn_val; 2638 FETCH_INST;
2639 GOTO_NEXT_INST;
2640}
2284 2641
2285 if (AddOverflow(rm_val, rn_val, result)) { 2642QADD_INST:
2286 result = POS(result) ? 0x80000000 : 0x7FFFFFFF; 2643QDADD_INST:
2287 cpu->Cpsr |= (1 << 27); 2644QDSUB_INST:
2288 } 2645QSUB_INST : {
2289 } 2646 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2290 // QSUB 2647 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2291 else if (op1 == 0x01) { 2648 const u8 op1 = inst_cream->op1;
2292 result = rm_val - rn_val; 2649 const u32 rm_val = RM;
2650 const u32 rn_val = RN;
2293 2651
2294 if (SubOverflow(rm_val, rn_val, result)) { 2652 u32 result = 0;
2295 result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
2296 cpu->Cpsr |= (1 << 27);
2297 }
2298 }
2299 // QDADD
2300 else if (op1 == 0x02) {
2301 u32 mul = (rn_val * 2);
2302 2653
2303 if (AddOverflow(rn_val, rn_val, rn_val * 2)) { 2654 // QADD
2304 mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; 2655 if (op1 == 0x00) {
2305 cpu->Cpsr |= (1 << 27); 2656 result = rm_val + rn_val;
2306 }
2307 2657
2308 result = mul + rm_val; 2658 if (AddOverflow(rm_val, rn_val, result)) {
2659 result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
2660 cpu->Cpsr |= (1 << 27);
2661 }
2662 }
2663 // QSUB
2664 else if (op1 == 0x01) {
2665 result = rm_val - rn_val;
2309 2666
2310 if (AddOverflow(rm_val, mul, result)) { 2667 if (SubOverflow(rm_val, rn_val, result)) {
2311 result = POS(result) ? 0x80000000 : 0x7FFFFFFF; 2668 result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
2312 cpu->Cpsr |= (1 << 27); 2669 cpu->Cpsr |= (1 << 27);
2313 }
2314 } 2670 }
2315 // QDSUB 2671 }
2316 else if (op1 == 0x03) { 2672 // QDADD
2317 u32 mul = (rn_val * 2); 2673 else if (op1 == 0x02) {
2674 u32 mul = (rn_val * 2);
2318 2675
2319 if (AddOverflow(rn_val, rn_val, mul)) { 2676 if (AddOverflow(rn_val, rn_val, rn_val * 2)) {
2320 mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF; 2677 mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
2321 cpu->Cpsr |= (1 << 27); 2678 cpu->Cpsr |= (1 << 27);
2322 } 2679 }
2323 2680
2324 result = rm_val - mul; 2681 result = mul + rm_val;
2325 2682
2326 if (SubOverflow(rm_val, mul, result)) { 2683 if (AddOverflow(rm_val, mul, result)) {
2327 result = POS(result) ? 0x80000000 : 0x7FFFFFFF; 2684 result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
2328 cpu->Cpsr |= (1 << 27); 2685 cpu->Cpsr |= (1 << 27);
2329 }
2330 } 2686 }
2331
2332 RD = result;
2333 } 2687 }
2688 // QDSUB
2689 else if (op1 == 0x03) {
2690 u32 mul = (rn_val * 2);
2334 2691
2335 cpu->Reg[15] += cpu->GetInstructionSize(); 2692 if (AddOverflow(rn_val, rn_val, mul)) {
2336 INC_PC(sizeof(generic_arm_inst)); 2693 mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
2337 FETCH_INST; 2694 cpu->Cpsr |= (1 << 27);
2338 GOTO_NEXT_INST;
2339 }
2340
2341 QADD8_INST:
2342 QADD16_INST:
2343 QADDSUBX_INST:
2344 QSUB8_INST:
2345 QSUB16_INST:
2346 QSUBADDX_INST:
2347 {
2348 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2349 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2350 const u16 rm_lo = (RM & 0xFFFF);
2351 const u16 rm_hi = ((RM >> 16) & 0xFFFF);
2352 const u16 rn_lo = (RN & 0xFFFF);
2353 const u16 rn_hi = ((RN >> 16) & 0xFFFF);
2354 const u8 op2 = inst_cream->op2;
2355
2356 u16 lo_result = 0;
2357 u16 hi_result = 0;
2358
2359 // QADD16
2360 if (op2 == 0x00) {
2361 lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo);
2362 hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi);
2363 }
2364 // QASX
2365 else if (op2 == 0x01) {
2366 lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi);
2367 hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo);
2368 }
2369 // QSAX
2370 else if (op2 == 0x02) {
2371 lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi);
2372 hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo);
2373 }
2374 // QSUB16
2375 else if (op2 == 0x03) {
2376 lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo);
2377 hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi);
2378 }
2379 // QADD8
2380 else if (op2 == 0x04) {
2381 lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) |
2382 ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8;
2383 hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) |
2384 ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8;
2385 } 2695 }
2386 // QSUB8 2696
2387 else if (op2 == 0x07) { 2697 result = rm_val - mul;
2388 lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) | 2698
2389 ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8; 2699 if (SubOverflow(rm_val, mul, result)) {
2390 hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) | 2700 result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
2391 ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8; 2701 cpu->Cpsr |= (1 << 27);
2392 } 2702 }
2703 }
2393 2704
2394 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); 2705 RD = result;
2706 }
2707
2708 cpu->Reg[15] += cpu->GetInstructionSize();
2709 INC_PC(sizeof(generic_arm_inst));
2710 FETCH_INST;
2711 GOTO_NEXT_INST;
2712}
2713
2714QADD8_INST:
2715QADD16_INST:
2716QADDSUBX_INST:
2717QSUB8_INST:
2718QSUB16_INST:
2719QSUBADDX_INST : {
2720 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2721 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2722 const u16 rm_lo = (RM & 0xFFFF);
2723 const u16 rm_hi = ((RM >> 16) & 0xFFFF);
2724 const u16 rn_lo = (RN & 0xFFFF);
2725 const u16 rn_hi = ((RN >> 16) & 0xFFFF);
2726 const u8 op2 = inst_cream->op2;
2727
2728 u16 lo_result = 0;
2729 u16 hi_result = 0;
2730
2731 // QADD16
2732 if (op2 == 0x00) {
2733 lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_lo);
2734 hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_hi);
2735 }
2736 // QASX
2737 else if (op2 == 0x01) {
2738 lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_hi);
2739 hi_result = ARMul_SignedSaturatedAdd16(rn_hi, rm_lo);
2740 }
2741 // QSAX
2742 else if (op2 == 0x02) {
2743 lo_result = ARMul_SignedSaturatedAdd16(rn_lo, rm_hi);
2744 hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_lo);
2745 }
2746 // QSUB16
2747 else if (op2 == 0x03) {
2748 lo_result = ARMul_SignedSaturatedSub16(rn_lo, rm_lo);
2749 hi_result = ARMul_SignedSaturatedSub16(rn_hi, rm_hi);
2750 }
2751 // QADD8
2752 else if (op2 == 0x04) {
2753 lo_result = ARMul_SignedSaturatedAdd8(rn_lo & 0xFF, rm_lo & 0xFF) |
2754 ARMul_SignedSaturatedAdd8(rn_lo >> 8, rm_lo >> 8) << 8;
2755 hi_result = ARMul_SignedSaturatedAdd8(rn_hi & 0xFF, rm_hi & 0xFF) |
2756 ARMul_SignedSaturatedAdd8(rn_hi >> 8, rm_hi >> 8) << 8;
2757 }
2758 // QSUB8
2759 else if (op2 == 0x07) {
2760 lo_result = ARMul_SignedSaturatedSub8(rn_lo & 0xFF, rm_lo & 0xFF) |
2761 ARMul_SignedSaturatedSub8(rn_lo >> 8, rm_lo >> 8) << 8;
2762 hi_result = ARMul_SignedSaturatedSub8(rn_hi & 0xFF, rm_hi & 0xFF) |
2763 ARMul_SignedSaturatedSub8(rn_hi >> 8, rm_hi >> 8) << 8;
2395 } 2764 }
2396 2765
2397 cpu->Reg[15] += cpu->GetInstructionSize(); 2766 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
2398 INC_PC(sizeof(generic_arm_inst));
2399 FETCH_INST;
2400 GOTO_NEXT_INST;
2401 } 2767 }
2402 2768
2403 REV_INST: 2769 cpu->Reg[15] += cpu->GetInstructionSize();
2404 REV16_INST: 2770 INC_PC(sizeof(generic_arm_inst));
2405 REVSH_INST: 2771 FETCH_INST;
2406 { 2772 GOTO_NEXT_INST;
2773}
2407 2774
2408 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2775REV_INST:
2409 rev_inst* const inst_cream = (rev_inst*)inst_base->component; 2776REV16_INST:
2777REVSH_INST : {
2410 2778
2411 const u8 op1 = inst_cream->op1; 2779 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2412 const u8 op2 = inst_cream->op2; 2780 rev_inst* const inst_cream = (rev_inst*)inst_base->component;
2413 2781
2414 // REV 2782 const u8 op1 = inst_cream->op1;
2415 if (op1 == 0x03 && op2 == 0x01) { 2783 const u8 op2 = inst_cream->op2;
2416 RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) | ((RM >> 24) & 0xFF);
2417 }
2418 // REV16
2419 else if (op1 == 0x03 && op2 == 0x05) {
2420 RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) | ((RM & 0xFF000000) >> 8);
2421 }
2422 // REVSH
2423 else if (op1 == 0x07 && op2 == 0x05) {
2424 RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8);
2425 if (RD & 0x8000)
2426 RD |= 0xffff0000;
2427 }
2428 }
2429 2784
2430 cpu->Reg[15] += cpu->GetInstructionSize(); 2785 // REV
2431 INC_PC(sizeof(rev_inst)); 2786 if (op1 == 0x03 && op2 == 0x01) {
2432 FETCH_INST; 2787 RD = ((RM & 0xFF) << 24) | (((RM >> 8) & 0xFF) << 16) | (((RM >> 16) & 0xFF) << 8) |
2433 GOTO_NEXT_INST; 2788 ((RM >> 24) & 0xFF);
2789 }
2790 // REV16
2791 else if (op1 == 0x03 && op2 == 0x05) {
2792 RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8) | ((RM & 0xFF0000) << 8) |
2793 ((RM & 0xFF000000) >> 8);
2794 }
2795 // REVSH
2796 else if (op1 == 0x07 && op2 == 0x05) {
2797 RD = ((RM & 0xFF) << 8) | ((RM & 0xFF00) >> 8);
2798 if (RD & 0x8000)
2799 RD |= 0xffff0000;
2800 }
2434 } 2801 }
2435 2802
2436 RFE_INST: 2803 cpu->Reg[15] += cpu->GetInstructionSize();
2437 { 2804 INC_PC(sizeof(rev_inst));
2438 // RFE is unconditional 2805 FETCH_INST;
2439 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; 2806 GOTO_NEXT_INST;
2807}
2440 2808
2441 u32 address = 0; 2809RFE_INST : {
2442 inst_cream->get_addr(cpu, inst_cream->inst, address); 2810 // RFE is unconditional
2811 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
2443 2812
2444 cpu->Cpsr = cpu->ReadMemory32(address); 2813 u32 address = 0;
2445 cpu->Reg[15] = cpu->ReadMemory32(address + 4); 2814 inst_cream->get_addr(cpu, inst_cream->inst, address);
2446 2815
2447 INC_PC(sizeof(ldst_inst)); 2816 cpu->Cpsr = cpu->ReadMemory32(address);
2448 goto DISPATCH; 2817 cpu->Reg[15] = cpu->ReadMemory32(address + 4);
2449 } 2818
2819 INC_PC(sizeof(ldst_inst));
2820 goto DISPATCH;
2821}
2450 2822
2451 RSB_INST: 2823RSB_INST : {
2452 { 2824 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2453 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2825 rsb_inst* const inst_cream = (rsb_inst*)inst_base->component;
2454 rsb_inst* const inst_cream = (rsb_inst*)inst_base->component;
2455 2826
2456 u32 rn_val = RN; 2827 u32 rn_val = RN;
2457 if (inst_cream->Rn == 15) 2828 if (inst_cream->Rn == 15)
2458 rn_val += 2 * cpu->GetInstructionSize(); 2829 rn_val += 2 * cpu->GetInstructionSize();
2459 2830
2460 bool carry; 2831 bool carry;
2461 bool overflow; 2832 bool overflow;
2462 RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); 2833 RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow);
2463 2834
2464 if (inst_cream->S && (inst_cream->Rd == 15)) { 2835 if (inst_cream->S && (inst_cream->Rd == 15)) {
2465 if (CurrentModeHasSPSR) { 2836 if (CurrentModeHasSPSR) {
2466 cpu->Cpsr = cpu->Spsr_copy; 2837 cpu->Cpsr = cpu->Spsr_copy;
2467 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 2838 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2468 LOAD_NZCVT; 2839 LOAD_NZCVT;
2469 }
2470 } else if (inst_cream->S) {
2471 UPDATE_NFLAG(RD);
2472 UPDATE_ZFLAG(RD);
2473 cpu->CFlag = carry;
2474 cpu->VFlag = overflow;
2475 } 2840 }
2476 if (inst_cream->Rd == 15) { 2841 } else if (inst_cream->S) {
2477 INC_PC(sizeof(rsb_inst)); 2842 UPDATE_NFLAG(RD);
2478 goto DISPATCH; 2843 UPDATE_ZFLAG(RD);
2844 cpu->CFlag = carry;
2845 cpu->VFlag = overflow;
2846 }
2847 if (inst_cream->Rd == 15) {
2848 INC_PC(sizeof(rsb_inst));
2849 goto DISPATCH;
2850 }
2851 }
2852 cpu->Reg[15] += cpu->GetInstructionSize();
2853 INC_PC(sizeof(rsb_inst));
2854 FETCH_INST;
2855 GOTO_NEXT_INST;
2856}
2857RSC_INST : {
2858 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2859 rsc_inst* const inst_cream = (rsc_inst*)inst_base->component;
2860
2861 u32 rn_val = RN;
2862 if (inst_cream->Rn == 15)
2863 rn_val += 2 * cpu->GetInstructionSize();
2864
2865 bool carry;
2866 bool overflow;
2867 RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
2868
2869 if (inst_cream->S && (inst_cream->Rd == 15)) {
2870 if (CurrentModeHasSPSR) {
2871 cpu->Cpsr = cpu->Spsr_copy;
2872 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2873 LOAD_NZCVT;
2479 } 2874 }
2875 } else if (inst_cream->S) {
2876 UPDATE_NFLAG(RD);
2877 UPDATE_ZFLAG(RD);
2878 cpu->CFlag = carry;
2879 cpu->VFlag = overflow;
2480 } 2880 }
2481 cpu->Reg[15] += cpu->GetInstructionSize(); 2881 if (inst_cream->Rd == 15) {
2482 INC_PC(sizeof(rsb_inst)); 2882 INC_PC(sizeof(rsc_inst));
2483 FETCH_INST; 2883 goto DISPATCH;
2484 GOTO_NEXT_INST; 2884 }
2485 } 2885 }
2486 RSC_INST: 2886 cpu->Reg[15] += cpu->GetInstructionSize();
2487 { 2887 INC_PC(sizeof(rsc_inst));
2488 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2888 FETCH_INST;
2489 rsc_inst* const inst_cream = (rsc_inst*)inst_base->component; 2889 GOTO_NEXT_INST;
2490 2890}
2491 u32 rn_val = RN; 2891
2492 if (inst_cream->Rn == 15) 2892SADD8_INST:
2493 rn_val += 2 * cpu->GetInstructionSize(); 2893SSUB8_INST:
2494 2894SADD16_INST:
2495 bool carry; 2895SADDSUBX_INST:
2496 bool overflow; 2896SSUBADDX_INST:
2497 RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); 2897SSUB16_INST : {
2498 2898 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2499 if (inst_cream->S && (inst_cream->Rd == 15)) { 2899 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2500 if (CurrentModeHasSPSR) { 2900 const u8 op2 = inst_cream->op2;
2501 cpu->Cpsr = cpu->Spsr_copy; 2901
2502 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 2902 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
2503 LOAD_NZCVT; 2903 const s16 rn_lo = (RN & 0xFFFF);
2504 } 2904 const s16 rn_hi = ((RN >> 16) & 0xFFFF);
2505 } else if (inst_cream->S) { 2905 const s16 rm_lo = (RM & 0xFFFF);
2506 UPDATE_NFLAG(RD); 2906 const s16 rm_hi = ((RM >> 16) & 0xFFFF);
2507 UPDATE_ZFLAG(RD); 2907
2508 cpu->CFlag = carry; 2908 s32 lo_result = 0;
2509 cpu->VFlag = overflow; 2909 s32 hi_result = 0;
2910
2911 // SADD16
2912 if (inst_cream->op2 == 0x00) {
2913 lo_result = (rn_lo + rm_lo);
2914 hi_result = (rn_hi + rm_hi);
2510 } 2915 }
2511 if (inst_cream->Rd == 15) { 2916 // SASX
2512 INC_PC(sizeof(rsc_inst)); 2917 else if (op2 == 0x01) {
2513 goto DISPATCH; 2918 lo_result = (rn_lo - rm_hi);
2919 hi_result = (rn_hi + rm_lo);
2920 }
2921 // SSAX
2922 else if (op2 == 0x02) {
2923 lo_result = (rn_lo + rm_hi);
2924 hi_result = (rn_hi - rm_lo);
2925 }
2926 // SSUB16
2927 else if (op2 == 0x03) {
2928 lo_result = (rn_lo - rm_lo);
2929 hi_result = (rn_hi - rm_hi);
2514 } 2930 }
2515 }
2516 cpu->Reg[15] += cpu->GetInstructionSize();
2517 INC_PC(sizeof(rsc_inst));
2518 FETCH_INST;
2519 GOTO_NEXT_INST;
2520 }
2521
2522 SADD8_INST:
2523 SSUB8_INST:
2524 SADD16_INST:
2525 SADDSUBX_INST:
2526 SSUBADDX_INST:
2527 SSUB16_INST:
2528 {
2529 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2530 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2531 const u8 op2 = inst_cream->op2;
2532
2533 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
2534 const s16 rn_lo = (RN & 0xFFFF);
2535 const s16 rn_hi = ((RN >> 16) & 0xFFFF);
2536 const s16 rm_lo = (RM & 0xFFFF);
2537 const s16 rm_hi = ((RM >> 16) & 0xFFFF);
2538
2539 s32 lo_result = 0;
2540 s32 hi_result = 0;
2541
2542 // SADD16
2543 if (inst_cream->op2 == 0x00) {
2544 lo_result = (rn_lo + rm_lo);
2545 hi_result = (rn_hi + rm_hi);
2546 }
2547 // SASX
2548 else if (op2 == 0x01) {
2549 lo_result = (rn_lo - rm_hi);
2550 hi_result = (rn_hi + rm_lo);
2551 }
2552 // SSAX
2553 else if (op2 == 0x02) {
2554 lo_result = (rn_lo + rm_hi);
2555 hi_result = (rn_hi - rm_lo);
2556 }
2557 // SSUB16
2558 else if (op2 == 0x03) {
2559 lo_result = (rn_lo - rm_lo);
2560 hi_result = (rn_hi - rm_hi);
2561 }
2562 2931
2563 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); 2932 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
2564 2933
2565 if (lo_result >= 0) { 2934 if (lo_result >= 0) {
2566 cpu->Cpsr |= (1 << 16); 2935 cpu->Cpsr |= (1 << 16);
2567 cpu->Cpsr |= (1 << 17); 2936 cpu->Cpsr |= (1 << 17);
2568 } else { 2937 } else {
2569 cpu->Cpsr &= ~(1 << 16); 2938 cpu->Cpsr &= ~(1 << 16);
2570 cpu->Cpsr &= ~(1 << 17); 2939 cpu->Cpsr &= ~(1 << 17);
2571 } 2940 }
2572 2941
2573 if (hi_result >= 0) { 2942 if (hi_result >= 0) {
2574 cpu->Cpsr |= (1 << 18); 2943 cpu->Cpsr |= (1 << 18);
2575 cpu->Cpsr |= (1 << 19); 2944 cpu->Cpsr |= (1 << 19);
2576 } else { 2945 } else {
2577 cpu->Cpsr &= ~(1 << 18); 2946 cpu->Cpsr &= ~(1 << 18);
2578 cpu->Cpsr &= ~(1 << 19); 2947 cpu->Cpsr &= ~(1 << 19);
2579 } 2948 }
2949 } else if (op2 == 0x04 || op2 == 0x07) {
2950 s32 lo_val1, lo_val2;
2951 s32 hi_val1, hi_val2;
2952
2953 // SADD8
2954 if (op2 == 0x04) {
2955 lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF);
2956 lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF);
2957 hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF);
2958 hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF);
2959 }
2960 // SSUB8
2961 else {
2962 lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF);
2963 lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF);
2964 hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF);
2965 hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF);
2580 } 2966 }
2581 else if (op2 == 0x04 || op2 == 0x07) {
2582 s32 lo_val1, lo_val2;
2583 s32 hi_val1, hi_val2;
2584
2585 // SADD8
2586 if (op2 == 0x04) {
2587 lo_val1 = (s32)(s8)(RN & 0xFF) + (s32)(s8)(RM & 0xFF);
2588 lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) + (s32)(s8)((RM >> 8) & 0xFF);
2589 hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) + (s32)(s8)((RM >> 16) & 0xFF);
2590 hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) + (s32)(s8)((RM >> 24) & 0xFF);
2591 }
2592 // SSUB8
2593 else {
2594 lo_val1 = (s32)(s8)(RN & 0xFF) - (s32)(s8)(RM & 0xFF);
2595 lo_val2 = (s32)(s8)((RN >> 8) & 0xFF) - (s32)(s8)((RM >> 8) & 0xFF);
2596 hi_val1 = (s32)(s8)((RN >> 16) & 0xFF) - (s32)(s8)((RM >> 16) & 0xFF);
2597 hi_val2 = (s32)(s8)((RN >> 24) & 0xFF) - (s32)(s8)((RM >> 24) & 0xFF);
2598 }
2599 2967
2600 RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24)); 2968 RD = ((lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) |
2969 ((hi_val2 & 0xFF) << 24));
2601 2970
2602 if (lo_val1 >= 0) 2971 if (lo_val1 >= 0)
2603 cpu->Cpsr |= (1 << 16); 2972 cpu->Cpsr |= (1 << 16);
2604 else 2973 else
2605 cpu->Cpsr &= ~(1 << 16); 2974 cpu->Cpsr &= ~(1 << 16);
2606 2975
2607 if (lo_val2 >= 0) 2976 if (lo_val2 >= 0)
2608 cpu->Cpsr |= (1 << 17); 2977 cpu->Cpsr |= (1 << 17);
2609 else 2978 else
2610 cpu->Cpsr &= ~(1 << 17); 2979 cpu->Cpsr &= ~(1 << 17);
2611 2980
2612 if (hi_val1 >= 0) 2981 if (hi_val1 >= 0)
2613 cpu->Cpsr |= (1 << 18); 2982 cpu->Cpsr |= (1 << 18);
2614 else 2983 else
2615 cpu->Cpsr &= ~(1 << 18); 2984 cpu->Cpsr &= ~(1 << 18);
2616 2985
2617 if (hi_val2 >= 0) 2986 if (hi_val2 >= 0)
2618 cpu->Cpsr |= (1 << 19); 2987 cpu->Cpsr |= (1 << 19);
2619 else 2988 else
2620 cpu->Cpsr &= ~(1 << 19); 2989 cpu->Cpsr &= ~(1 << 19);
2621 }
2622 } 2990 }
2623
2624 cpu->Reg[15] += cpu->GetInstructionSize();
2625 INC_PC(sizeof(generic_arm_inst));
2626 FETCH_INST;
2627 GOTO_NEXT_INST;
2628 } 2991 }
2629 2992
2630 SBC_INST: 2993 cpu->Reg[15] += cpu->GetInstructionSize();
2631 { 2994 INC_PC(sizeof(generic_arm_inst));
2632 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 2995 FETCH_INST;
2633 sbc_inst* const inst_cream = (sbc_inst*)inst_base->component; 2996 GOTO_NEXT_INST;
2997}
2634 2998
2635 u32 rn_val = RN; 2999SBC_INST : {
2636 if (inst_cream->Rn == 15) 3000 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2637 rn_val += 2 * cpu->GetInstructionSize(); 3001 sbc_inst* const inst_cream = (sbc_inst*)inst_base->component;
2638 3002
2639 bool carry; 3003 u32 rn_val = RN;
2640 bool overflow; 3004 if (inst_cream->Rn == 15)
2641 RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); 3005 rn_val += 2 * cpu->GetInstructionSize();
2642 3006
2643 if (inst_cream->S && (inst_cream->Rd == 15)) { 3007 bool carry;
2644 if (CurrentModeHasSPSR) { 3008 bool overflow;
2645 cpu->Cpsr = cpu->Spsr_copy; 3009 RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
2646 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); 3010
2647 LOAD_NZCVT; 3011 if (inst_cream->S && (inst_cream->Rd == 15)) {
2648 } 3012 if (CurrentModeHasSPSR) {
2649 } else if (inst_cream->S) { 3013 cpu->Cpsr = cpu->Spsr_copy;
2650 UPDATE_NFLAG(RD); 3014 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
2651 UPDATE_ZFLAG(RD); 3015 LOAD_NZCVT;
2652 cpu->CFlag = carry;
2653 cpu->VFlag = overflow;
2654 }
2655 if (inst_cream->Rd == 15) {
2656 INC_PC(sizeof(sbc_inst));
2657 goto DISPATCH;
2658 } 3016 }
3017 } else if (inst_cream->S) {
3018 UPDATE_NFLAG(RD);
3019 UPDATE_ZFLAG(RD);
3020 cpu->CFlag = carry;
3021 cpu->VFlag = overflow;
3022 }
3023 if (inst_cream->Rd == 15) {
3024 INC_PC(sizeof(sbc_inst));
3025 goto DISPATCH;
2659 } 3026 }
2660 cpu->Reg[15] += cpu->GetInstructionSize();
2661 INC_PC(sizeof(sbc_inst));
2662 FETCH_INST;
2663 GOTO_NEXT_INST;
2664 } 3027 }
3028 cpu->Reg[15] += cpu->GetInstructionSize();
3029 INC_PC(sizeof(sbc_inst));
3030 FETCH_INST;
3031 GOTO_NEXT_INST;
3032}
2665 3033
2666 SEL_INST: 3034SEL_INST : {
2667 { 3035 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2668 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3036 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2669 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2670 3037
2671 const u32 to = RM; 3038 const u32 to = RM;
2672 const u32 from = RN; 3039 const u32 from = RN;
2673 const u32 cpsr = cpu->Cpsr; 3040 const u32 cpsr = cpu->Cpsr;
2674 3041
2675 u32 result; 3042 u32 result;
2676 if (cpsr & (1 << 16)) 3043 if (cpsr & (1 << 16))
2677 result = from & 0xff; 3044 result = from & 0xff;
2678 else 3045 else
2679 result = to & 0xff; 3046 result = to & 0xff;
2680
2681 if (cpsr & (1 << 17))
2682 result |= from & 0x0000ff00;
2683 else
2684 result |= to & 0x0000ff00;
2685 3047
2686 if (cpsr & (1 << 18)) 3048 if (cpsr & (1 << 17))
2687 result |= from & 0x00ff0000; 3049 result |= from & 0x0000ff00;
2688 else 3050 else
2689 result |= to & 0x00ff0000; 3051 result |= to & 0x0000ff00;
2690 3052
2691 if (cpsr & (1 << 19)) 3053 if (cpsr & (1 << 18))
2692 result |= from & 0xff000000; 3054 result |= from & 0x00ff0000;
2693 else 3055 else
2694 result |= to & 0xff000000; 3056 result |= to & 0x00ff0000;
2695 3057
2696 RD = result; 3058 if (cpsr & (1 << 19))
2697 } 3059 result |= from & 0xff000000;
3060 else
3061 result |= to & 0xff000000;
2698 3062
2699 cpu->Reg[15] += cpu->GetInstructionSize(); 3063 RD = result;
2700 INC_PC(sizeof(generic_arm_inst));
2701 FETCH_INST;
2702 GOTO_NEXT_INST;
2703 } 3064 }
2704 3065
2705 SETEND_INST: 3066 cpu->Reg[15] += cpu->GetInstructionSize();
2706 { 3067 INC_PC(sizeof(generic_arm_inst));
2707 // SETEND is unconditional 3068 FETCH_INST;
2708 setend_inst* const inst_cream = (setend_inst*)inst_base->component; 3069 GOTO_NEXT_INST;
2709 const bool big_endian = (inst_cream->set_bigend == 1); 3070}
2710 3071
2711 if (big_endian) 3072SETEND_INST : {
2712 cpu->Cpsr |= (1 << 9); 3073 // SETEND is unconditional
2713 else 3074 setend_inst* const inst_cream = (setend_inst*)inst_base->component;
2714 cpu->Cpsr &= ~(1 << 9); 3075 const bool big_endian = (inst_cream->set_bigend == 1);
2715 3076
2716 LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE"); 3077 if (big_endian)
3078 cpu->Cpsr |= (1 << 9);
3079 else
3080 cpu->Cpsr &= ~(1 << 9);
2717 3081
2718 cpu->Reg[15] += cpu->GetInstructionSize(); 3082 LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
2719 INC_PC(sizeof(setend_inst));
2720 FETCH_INST;
2721 GOTO_NEXT_INST;
2722 }
2723 3083
2724 SEV_INST: 3084 cpu->Reg[15] += cpu->GetInstructionSize();
2725 { 3085 INC_PC(sizeof(setend_inst));
2726 // Stubbed, as SEV is a hint instruction. 3086 FETCH_INST;
2727 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3087 GOTO_NEXT_INST;
2728 LOG_TRACE(Core_ARM11, "SEV executed."); 3088}
2729 }
2730 3089
2731 cpu->Reg[15] += cpu->GetInstructionSize(); 3090SEV_INST : {
2732 INC_PC_STUB; 3091 // Stubbed, as SEV is a hint instruction.
2733 FETCH_INST; 3092 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2734 GOTO_NEXT_INST; 3093 LOG_TRACE(Core_ARM11, "SEV executed.");
2735 } 3094 }
2736 3095
2737 SHADD8_INST: 3096 cpu->Reg[15] += cpu->GetInstructionSize();
2738 SHADD16_INST: 3097 INC_PC_STUB;
2739 SHADDSUBX_INST: 3098 FETCH_INST;
2740 SHSUB8_INST: 3099 GOTO_NEXT_INST;
2741 SHSUB16_INST: 3100}
2742 SHSUBADDX_INST:
2743 {
2744 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2745 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2746 3101
2747 const u8 op2 = inst_cream->op2; 3102SHADD8_INST:
2748 const u32 rm_val = RM; 3103SHADD16_INST:
2749 const u32 rn_val = RN; 3104SHADDSUBX_INST:
3105SHSUB8_INST:
3106SHSUB16_INST:
3107SHSUBADDX_INST : {
3108 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3109 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
2750 3110
2751 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) { 3111 const u8 op2 = inst_cream->op2;
2752 s32 lo_result = 0; 3112 const u32 rm_val = RM;
2753 s32 hi_result = 0; 3113 const u32 rn_val = RN;
2754 3114
2755 // SHADD16 3115 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
2756 if (op2 == 0x00) { 3116 s32 lo_result = 0;
2757 lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1; 3117 s32 hi_result = 0;
2758 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
2759 }
2760 // SHASX
2761 else if (op2 == 0x01) {
2762 lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
2763 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1;
2764 }
2765 // SHSAX
2766 else if (op2 == 0x02) {
2767 lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
2768 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
2769 }
2770 // SHSUB16
2771 else if (op2 == 0x03) {
2772 lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
2773 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
2774 }
2775 3118
2776 RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16)); 3119 // SHADD16
3120 if (op2 == 0x00) {
3121 lo_result = ((s16)(rn_val & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1;
3122 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
3123 }
3124 // SHASX
3125 else if (op2 == 0x01) {
3126 lo_result = ((s16)(rn_val & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
3127 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) + (s16)(rm_val & 0xFFFF)) >> 1;
3128 }
3129 // SHSAX
3130 else if (op2 == 0x02) {
3131 lo_result = ((s16)(rn_val & 0xFFFF) + (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
3132 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
3133 }
3134 // SHSUB16
3135 else if (op2 == 0x03) {
3136 lo_result = ((s16)(rn_val & 0xFFFF) - (s16)(rm_val & 0xFFFF)) >> 1;
3137 hi_result = ((s16)((rn_val >> 16) & 0xFFFF) - (s16)((rm_val >> 16) & 0xFFFF)) >> 1;
2777 } 3138 }
2778 else if (op2 == 0x04 || op2 == 0x07) {
2779 s16 lo_val1, lo_val2;
2780 s16 hi_val1, hi_val2;
2781
2782 // SHADD8
2783 if (op2 == 0x04) {
2784 lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1;
2785 lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1;
2786 3139
2787 hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1; 3140 RD = ((lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16));
2788 hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1; 3141 } else if (op2 == 0x04 || op2 == 0x07) {
2789 } 3142 s16 lo_val1, lo_val2;
2790 // SHSUB8 3143 s16 hi_val1, hi_val2;
2791 else {
2792 lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1;
2793 lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1;
2794 3144
2795 hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1; 3145 // SHADD8
2796 hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1; 3146 if (op2 == 0x04) {
2797 } 3147 lo_val1 = ((s8)(rn_val & 0xFF) + (s8)(rm_val & 0xFF)) >> 1;
3148 lo_val2 = ((s8)((rn_val >> 8) & 0xFF) + (s8)((rm_val >> 8) & 0xFF)) >> 1;
2798 3149
2799 RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) | ((hi_val2 & 0xFF) << 24); 3150 hi_val1 = ((s8)((rn_val >> 16) & 0xFF) + (s8)((rm_val >> 16) & 0xFF)) >> 1;
3151 hi_val2 = ((s8)((rn_val >> 24) & 0xFF) + (s8)((rm_val >> 24) & 0xFF)) >> 1;
2800 } 3152 }
2801 } 3153 // SHSUB8
2802 3154 else {
2803 cpu->Reg[15] += cpu->GetInstructionSize(); 3155 lo_val1 = ((s8)(rn_val & 0xFF) - (s8)(rm_val & 0xFF)) >> 1;
2804 INC_PC(sizeof(generic_arm_inst)); 3156 lo_val2 = ((s8)((rn_val >> 8) & 0xFF) - (s8)((rm_val >> 8) & 0xFF)) >> 1;
2805 FETCH_INST;
2806 GOTO_NEXT_INST;
2807 }
2808
2809 SMLA_INST:
2810 {
2811 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2812 smla_inst* inst_cream = (smla_inst*)inst_base->component;
2813 s32 operand1, operand2;
2814 if (inst_cream->x == 0)
2815 operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
2816 else
2817 operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
2818 3157
2819 if (inst_cream->y == 0) 3158 hi_val1 = ((s8)((rn_val >> 16) & 0xFF) - (s8)((rm_val >> 16) & 0xFF)) >> 1;
2820 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); 3159 hi_val2 = ((s8)((rn_val >> 24) & 0xFF) - (s8)((rm_val >> 24) & 0xFF)) >> 1;
2821 else 3160 }
2822 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
2823 3161
2824 u32 product = operand1 * operand2; 3162 RD = (lo_val1 & 0xFF) | ((lo_val2 & 0xFF) << 8) | ((hi_val1 & 0xFF) << 16) |
2825 u32 result = product + RN; 3163 ((hi_val2 & 0xFF) << 24);
2826 if (AddOverflow(product, RN, result))
2827 cpu->Cpsr |= (1 << 27);
2828 RD = result;
2829 } 3164 }
2830 cpu->Reg[15] += cpu->GetInstructionSize();
2831 INC_PC(sizeof(smla_inst));
2832 FETCH_INST;
2833 GOTO_NEXT_INST;
2834 } 3165 }
2835 3166
2836 SMLAD_INST: 3167 cpu->Reg[15] += cpu->GetInstructionSize();
2837 SMLSD_INST: 3168 INC_PC(sizeof(generic_arm_inst));
2838 SMUAD_INST: 3169 FETCH_INST;
2839 SMUSD_INST: 3170 GOTO_NEXT_INST;
2840 { 3171}
2841 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3172
2842 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; 3173SMLA_INST : {
2843 const u8 op2 = inst_cream->op2; 3174 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3175 smla_inst* inst_cream = (smla_inst*)inst_base->component;
3176 s32 operand1, operand2;
3177 if (inst_cream->x == 0)
3178 operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
3179 else
3180 operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
2844 3181
2845 u32 rm_val = cpu->Reg[inst_cream->Rm]; 3182 if (inst_cream->y == 0)
2846 const u32 rn_val = cpu->Reg[inst_cream->Rn]; 3183 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
3184 else
3185 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
3186
3187 u32 product = operand1 * operand2;
3188 u32 result = product + RN;
3189 if (AddOverflow(product, RN, result))
3190 cpu->Cpsr |= (1 << 27);
3191 RD = result;
3192 }
3193 cpu->Reg[15] += cpu->GetInstructionSize();
3194 INC_PC(sizeof(smla_inst));
3195 FETCH_INST;
3196 GOTO_NEXT_INST;
3197}
2847 3198
2848 if (inst_cream->m) 3199SMLAD_INST:
2849 rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); 3200SMLSD_INST:
3201SMUAD_INST:
3202SMUSD_INST : {
3203 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3204 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
3205 const u8 op2 = inst_cream->op2;
2850 3206
2851 const s16 rm_lo = (rm_val & 0xFFFF); 3207 u32 rm_val = cpu->Reg[inst_cream->Rm];
2852 const s16 rm_hi = ((rm_val >> 16) & 0xFFFF); 3208 const u32 rn_val = cpu->Reg[inst_cream->Rn];
2853 const s16 rn_lo = (rn_val & 0xFFFF);
2854 const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
2855 3209
2856 const u32 product1 = (rn_lo * rm_lo); 3210 if (inst_cream->m)
2857 const u32 product2 = (rn_hi * rm_hi); 3211 rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16));
2858 3212
2859 // SMUAD and SMLAD 3213 const s16 rm_lo = (rm_val & 0xFFFF);
2860 if (BIT(op2, 1) == 0) { 3214 const s16 rm_hi = ((rm_val >> 16) & 0xFFFF);
2861 u32 rd_val = (product1 + product2); 3215 const s16 rn_lo = (rn_val & 0xFFFF);
3216 const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
2862 3217
2863 if (inst_cream->Ra != 15) { 3218 const u32 product1 = (rn_lo * rm_lo);
2864 rd_val += cpu->Reg[inst_cream->Ra]; 3219 const u32 product2 = (rn_hi * rm_hi);
2865 3220
2866 if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) 3221 // SMUAD and SMLAD
2867 cpu->Cpsr |= (1 << 27); 3222 if (BIT(op2, 1) == 0) {
2868 } 3223 u32 rd_val = (product1 + product2);
2869 3224
2870 RD = rd_val; 3225 if (inst_cream->Ra != 15) {
3226 rd_val += cpu->Reg[inst_cream->Ra];
2871 3227
2872 if (ARMul_AddOverflowQ(product1, product2)) 3228 if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra]))
2873 cpu->Cpsr |= (1 << 27); 3229 cpu->Cpsr |= (1 << 27);
2874 } 3230 }
2875 // SMUSD and SMLSD
2876 else {
2877 u32 rd_val = (product1 - product2);
2878 3231
2879 if (inst_cream->Ra != 15) { 3232 RD = rd_val;
2880 rd_val += cpu->Reg[inst_cream->Ra];
2881 3233
2882 if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) 3234 if (ARMul_AddOverflowQ(product1, product2))
2883 cpu->Cpsr |= (1 << 27); 3235 cpu->Cpsr |= (1 << 27);
2884 } 3236 }
3237 // SMUSD and SMLSD
3238 else {
3239 u32 rd_val = (product1 - product2);
3240
3241 if (inst_cream->Ra != 15) {
3242 rd_val += cpu->Reg[inst_cream->Ra];
2885 3243
2886 RD = rd_val; 3244 if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra]))
3245 cpu->Cpsr |= (1 << 27);
2887 } 3246 }
2888 }
2889 3247
2890 cpu->Reg[15] += cpu->GetInstructionSize(); 3248 RD = rd_val;
2891 INC_PC(sizeof(smlad_inst)); 3249 }
2892 FETCH_INST;
2893 GOTO_NEXT_INST;
2894 } 3250 }
2895 3251
2896 SMLAL_INST: 3252 cpu->Reg[15] += cpu->GetInstructionSize();
2897 { 3253 INC_PC(sizeof(smlad_inst));
2898 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3254 FETCH_INST;
2899 umlal_inst* inst_cream = (umlal_inst*)inst_base->component; 3255 GOTO_NEXT_INST;
2900 long long int rm = RM; 3256}
2901 long long int rs = RS; 3257
2902 if (BIT(rm, 31)) { 3258SMLAL_INST : {
2903 rm |= 0xffffffff00000000LL; 3259 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2904 } 3260 umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
2905 if (BIT(rs, 31)) { 3261 long long int rm = RM;
2906 rs |= 0xffffffff00000000LL; 3262 long long int rs = RS;
2907 } 3263 if (BIT(rm, 31)) {
2908 long long int rst = rm * rs; 3264 rm |= 0xffffffff00000000LL;
2909 long long int rdhi32 = RDHI;
2910 long long int hilo = (rdhi32 << 32) + RDLO;
2911 rst += hilo;
2912 RDLO = BITS(rst, 0, 31);
2913 RDHI = BITS(rst, 32, 63);
2914 if (inst_cream->S) {
2915 cpu->NFlag = BIT(RDHI, 31);
2916 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
2917 }
2918 } 3265 }
2919 cpu->Reg[15] += cpu->GetInstructionSize(); 3266 if (BIT(rs, 31)) {
2920 INC_PC(sizeof(umlal_inst)); 3267 rs |= 0xffffffff00000000LL;
2921 FETCH_INST; 3268 }
2922 GOTO_NEXT_INST; 3269 long long int rst = rm * rs;
2923 } 3270 long long int rdhi32 = RDHI;
2924 3271 long long int hilo = (rdhi32 << 32) + RDLO;
2925 SMLALXY_INST: 3272 rst += hilo;
2926 { 3273 RDLO = BITS(rst, 0, 31);
2927 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3274 RDHI = BITS(rst, 32, 63);
2928 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; 3275 if (inst_cream->S) {
2929 3276 cpu->NFlag = BIT(RDHI, 31);
2930 u64 operand1 = RN; 3277 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
2931 u64 operand2 = RM;
2932
2933 if (inst_cream->x != 0)
2934 operand1 >>= 16;
2935 if (inst_cream->y != 0)
2936 operand2 >>= 16;
2937 operand1 &= 0xFFFF;
2938 if (operand1 & 0x8000)
2939 operand1 -= 65536;
2940 operand2 &= 0xFFFF;
2941 if (operand2 & 0x8000)
2942 operand2 -= 65536;
2943
2944 u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2);
2945 RDLO = (dest & 0xFFFFFFFF);
2946 RDHI = ((dest >> 32) & 0xFFFFFFFF);
2947 } 3278 }
2948
2949 cpu->Reg[15] += cpu->GetInstructionSize();
2950 INC_PC(sizeof(smlalxy_inst));
2951 FETCH_INST;
2952 GOTO_NEXT_INST;
2953 } 3279 }
3280 cpu->Reg[15] += cpu->GetInstructionSize();
3281 INC_PC(sizeof(umlal_inst));
3282 FETCH_INST;
3283 GOTO_NEXT_INST;
3284}
2954 3285
2955 SMLAW_INST: 3286SMLALXY_INST : {
2956 { 3287 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2957 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3288 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
2958 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; 3289
3290 u64 operand1 = RN;
3291 u64 operand2 = RM;
3292
3293 if (inst_cream->x != 0)
3294 operand1 >>= 16;
3295 if (inst_cream->y != 0)
3296 operand2 >>= 16;
3297 operand1 &= 0xFFFF;
3298 if (operand1 & 0x8000)
3299 operand1 -= 65536;
3300 operand2 &= 0xFFFF;
3301 if (operand2 & 0x8000)
3302 operand2 -= 65536;
3303
3304 u64 dest = ((u64)RDHI << 32 | RDLO) + (operand1 * operand2);
3305 RDLO = (dest & 0xFFFFFFFF);
3306 RDHI = ((dest >> 32) & 0xFFFFFFFF);
3307 }
3308
3309 cpu->Reg[15] += cpu->GetInstructionSize();
3310 INC_PC(sizeof(smlalxy_inst));
3311 FETCH_INST;
3312 GOTO_NEXT_INST;
3313}
2959 3314
2960 const u32 rm_val = RM; 3315SMLAW_INST : {
2961 const u32 rn_val = RN; 3316 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2962 const u32 ra_val = cpu->Reg[inst_cream->Ra]; 3317 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
2963 const bool high = (inst_cream->m == 1);
2964 3318
2965 const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF); 3319 const u32 rm_val = RM;
2966 const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16); 3320 const u32 rn_val = RN;
3321 const u32 ra_val = cpu->Reg[inst_cream->Ra];
3322 const bool high = (inst_cream->m == 1);
2967 3323
2968 RD = BITS(result, 16, 47); 3324 const s16 operand2 = (high) ? ((rm_val >> 16) & 0xFFFF) : (rm_val & 0xFFFF);
3325 const s64 result = (s64)(s32)rn_val * (s64)(s32)operand2 + ((s64)(s32)ra_val << 16);
2969 3326
2970 if ((result >> 16) != (s32)RD) 3327 RD = BITS(result, 16, 47);
2971 cpu->Cpsr |= (1 << 27);
2972 }
2973 3328
2974 cpu->Reg[15] += cpu->GetInstructionSize(); 3329 if ((result >> 16) != (s32)RD)
2975 INC_PC(sizeof(smlad_inst)); 3330 cpu->Cpsr |= (1 << 27);
2976 FETCH_INST;
2977 GOTO_NEXT_INST;
2978 } 3331 }
2979 3332
2980 SMLALD_INST: 3333 cpu->Reg[15] += cpu->GetInstructionSize();
2981 SMLSLD_INST: 3334 INC_PC(sizeof(smlad_inst));
2982 { 3335 FETCH_INST;
2983 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3336 GOTO_NEXT_INST;
2984 smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; 3337}
2985 3338
2986 const bool do_swap = (inst_cream->swap == 1); 3339SMLALD_INST:
2987 const u32 rdlo_val = RDLO; 3340SMLSLD_INST : {
2988 const u32 rdhi_val = RDHI; 3341 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
2989 const u32 rn_val = RN; 3342 smlald_inst* const inst_cream = (smlald_inst*)inst_base->component;
2990 u32 rm_val = RM;
2991 3343
2992 if (do_swap) 3344 const bool do_swap = (inst_cream->swap == 1);
2993 rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16)); 3345 const u32 rdlo_val = RDLO;
3346 const u32 rdhi_val = RDHI;
3347 const u32 rn_val = RN;
3348 u32 rm_val = RM;
2994 3349
2995 const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF); 3350 if (do_swap)
2996 const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF); 3351 rm_val = (((rm_val & 0xFFFF) << 16) | (rm_val >> 16));
2997 s64 result;
2998 3352
2999 // SMLALD 3353 const s32 product1 = (s16)(rn_val & 0xFFFF) * (s16)(rm_val & 0xFFFF);
3000 if (BIT(inst_cream->op2, 1) == 0) { 3354 const s32 product2 = (s16)((rn_val >> 16) & 0xFFFF) * (s16)((rm_val >> 16) & 0xFFFF);
3001 result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32)); 3355 s64 result;
3002 }
3003 // SMLSLD
3004 else {
3005 result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32));
3006 }
3007 3356
3008 RDLO = (result & 0xFFFFFFFF); 3357 // SMLALD
3009 RDHI = ((result >> 32) & 0xFFFFFFFF); 3358 if (BIT(inst_cream->op2, 1) == 0) {
3359 result = (product1 + product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32));
3360 }
3361 // SMLSLD
3362 else {
3363 result = (product1 - product2) + (s64)(rdlo_val | ((s64)rdhi_val << 32));
3010 } 3364 }
3011 3365
3012 cpu->Reg[15] += cpu->GetInstructionSize(); 3366 RDLO = (result & 0xFFFFFFFF);
3013 INC_PC(sizeof(smlald_inst)); 3367 RDHI = ((result >> 32) & 0xFFFFFFFF);
3014 FETCH_INST;
3015 GOTO_NEXT_INST;
3016 } 3368 }
3017 3369
3018 SMMLA_INST: 3370 cpu->Reg[15] += cpu->GetInstructionSize();
3019 SMMLS_INST: 3371 INC_PC(sizeof(smlald_inst));
3020 SMMUL_INST: 3372 FETCH_INST;
3021 { 3373 GOTO_NEXT_INST;
3022 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3374}
3023 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
3024
3025 const u32 rm_val = RM;
3026 const u32 rn_val = RN;
3027 const bool do_round = (inst_cream->m == 1);
3028 3375
3029 // Assume SMMUL by default. 3376SMMLA_INST:
3030 s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val; 3377SMMLS_INST:
3378SMMUL_INST : {
3379 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3380 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
3031 3381
3032 if (inst_cream->Ra != 15) { 3382 const u32 rm_val = RM;
3033 const u32 ra_val = cpu->Reg[inst_cream->Ra]; 3383 const u32 rn_val = RN;
3384 const bool do_round = (inst_cream->m == 1);
3034 3385
3035 // SMMLA, otherwise SMMLS 3386 // Assume SMMUL by default.
3036 if (BIT(inst_cream->op2, 1) == 0) 3387 s64 result = (s64)(s32)rn_val * (s64)(s32)rm_val;
3037 result += ((s64)ra_val << 32);
3038 else
3039 result = ((s64)ra_val << 32) - result;
3040 }
3041 3388
3042 if (do_round) 3389 if (inst_cream->Ra != 15) {
3043 result += 0x80000000; 3390 const u32 ra_val = cpu->Reg[inst_cream->Ra];
3044 3391
3045 RD = ((result >> 32) & 0xFFFFFFFF); 3392 // SMMLA, otherwise SMMLS
3393 if (BIT(inst_cream->op2, 1) == 0)
3394 result += ((s64)ra_val << 32);
3395 else
3396 result = ((s64)ra_val << 32) - result;
3046 } 3397 }
3047 3398
3048 cpu->Reg[15] += cpu->GetInstructionSize(); 3399 if (do_round)
3049 INC_PC(sizeof(smlad_inst)); 3400 result += 0x80000000;
3050 FETCH_INST; 3401
3051 GOTO_NEXT_INST; 3402 RD = ((result >> 32) & 0xFFFFFFFF);
3052 } 3403 }
3053 3404
3054 SMUL_INST: 3405 cpu->Reg[15] += cpu->GetInstructionSize();
3055 { 3406 INC_PC(sizeof(smlad_inst));
3056 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3407 FETCH_INST;
3057 smul_inst* inst_cream = (smul_inst*)inst_base->component; 3408 GOTO_NEXT_INST;
3058 u32 operand1, operand2; 3409}
3059 if (inst_cream->x == 0)
3060 operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
3061 else
3062 operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
3063 3410
3064 if (inst_cream->y == 0) 3411SMUL_INST : {
3065 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15); 3412 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3066 else 3413 smul_inst* inst_cream = (smul_inst*)inst_base->component;
3067 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31); 3414 u32 operand1, operand2;
3068 RD = operand1 * operand2; 3415 if (inst_cream->x == 0)
3416 operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
3417 else
3418 operand1 = (BIT(RM, 31)) ? (BITS(RM, 16, 31) | 0xffff0000) : BITS(RM, 16, 31);
3419
3420 if (inst_cream->y == 0)
3421 operand2 = (BIT(RS, 15)) ? (BITS(RS, 0, 15) | 0xffff0000) : BITS(RS, 0, 15);
3422 else
3423 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
3424 RD = operand1 * operand2;
3425 }
3426 cpu->Reg[15] += cpu->GetInstructionSize();
3427 INC_PC(sizeof(smul_inst));
3428 FETCH_INST;
3429 GOTO_NEXT_INST;
3430}
3431SMULL_INST : {
3432 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3433 umull_inst* inst_cream = (umull_inst*)inst_base->component;
3434 s64 rm = RM;
3435 s64 rs = RS;
3436 if (BIT(rm, 31)) {
3437 rm |= 0xffffffff00000000LL;
3069 } 3438 }
3070 cpu->Reg[15] += cpu->GetInstructionSize(); 3439 if (BIT(rs, 31)) {
3071 INC_PC(sizeof(smul_inst)); 3440 rs |= 0xffffffff00000000LL;
3072 FETCH_INST; 3441 }
3073 GOTO_NEXT_INST; 3442 s64 rst = rm * rs;
3074 } 3443 RDHI = BITS(rst, 32, 63);
3075 SMULL_INST: 3444 RDLO = BITS(rst, 0, 31);
3076 {
3077 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3078 umull_inst* inst_cream = (umull_inst*)inst_base->component;
3079 s64 rm = RM;
3080 s64 rs = RS;
3081 if (BIT(rm, 31)) {
3082 rm |= 0xffffffff00000000LL;
3083 }
3084 if (BIT(rs, 31)) {
3085 rs |= 0xffffffff00000000LL;
3086 }
3087 s64 rst = rm * rs;
3088 RDHI = BITS(rst, 32, 63);
3089 RDLO = BITS(rst, 0, 31);
3090 3445
3091 if (inst_cream->S) { 3446 if (inst_cream->S) {
3092 cpu->NFlag = BIT(RDHI, 31); 3447 cpu->NFlag = BIT(RDHI, 31);
3093 cpu->ZFlag = (RDHI == 0 && RDLO == 0); 3448 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
3094 }
3095 } 3449 }
3096 cpu->Reg[15] += cpu->GetInstructionSize();
3097 INC_PC(sizeof(umull_inst));
3098 FETCH_INST;
3099 GOTO_NEXT_INST;
3100 } 3450 }
3451 cpu->Reg[15] += cpu->GetInstructionSize();
3452 INC_PC(sizeof(umull_inst));
3453 FETCH_INST;
3454 GOTO_NEXT_INST;
3455}
3101 3456
3102 SMULW_INST: 3457SMULW_INST : {
3103 { 3458 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3104 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3459 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
3105 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
3106 3460
3107 s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); 3461 s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF);
3108 3462
3109 s64 result = (s64)rm * (s64)(s32)RN; 3463 s64 result = (s64)rm * (s64)(s32)RN;
3110 RD = BITS(result, 16, 47); 3464 RD = BITS(result, 16, 47);
3111 }
3112 cpu->Reg[15] += cpu->GetInstructionSize();
3113 INC_PC(sizeof(smlad_inst));
3114 FETCH_INST;
3115 GOTO_NEXT_INST;
3116 } 3465 }
3466 cpu->Reg[15] += cpu->GetInstructionSize();
3467 INC_PC(sizeof(smlad_inst));
3468 FETCH_INST;
3469 GOTO_NEXT_INST;
3470}
3117 3471
3118 SRS_INST: 3472SRS_INST : {
3119 { 3473 // SRS is unconditional
3120 // SRS is unconditional 3474 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
3121 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
3122 3475
3123 u32 address = 0; 3476 u32 address = 0;
3124 inst_cream->get_addr(cpu, inst_cream->inst, address); 3477 inst_cream->get_addr(cpu, inst_cream->inst, address);
3125 3478
3126 cpu->WriteMemory32(address + 0, cpu->Reg[14]); 3479 cpu->WriteMemory32(address + 0, cpu->Reg[14]);
3127 cpu->WriteMemory32(address + 4, cpu->Spsr_copy); 3480 cpu->WriteMemory32(address + 4, cpu->Spsr_copy);
3128 3481
3129 cpu->Reg[15] += cpu->GetInstructionSize(); 3482 cpu->Reg[15] += cpu->GetInstructionSize();
3130 INC_PC(sizeof(ldst_inst)); 3483 INC_PC(sizeof(ldst_inst));
3131 FETCH_INST; 3484 FETCH_INST;
3132 GOTO_NEXT_INST; 3485 GOTO_NEXT_INST;
3133 } 3486}
3134
3135 SSAT_INST:
3136 {
3137 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3138 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
3139 3487
3140 u8 shift_type = inst_cream->shift_type; 3488SSAT_INST : {
3141 u8 shift_amount = inst_cream->imm5; 3489 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3142 u32 rn_val = RN; 3490 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
3143 3491
3144 // 32-bit ASR is encoded as an amount of 0. 3492 u8 shift_type = inst_cream->shift_type;
3145 if (shift_type == 1 && shift_amount == 0) 3493 u8 shift_amount = inst_cream->imm5;
3146 shift_amount = 31; 3494 u32 rn_val = RN;
3147 3495
3148 if (shift_type == 0) 3496 // 32-bit ASR is encoded as an amount of 0.
3149 rn_val <<= shift_amount; 3497 if (shift_type == 1 && shift_amount == 0)
3150 else if (shift_type == 1) 3498 shift_amount = 31;
3151 rn_val = ((s32)rn_val >> shift_amount);
3152 3499
3153 bool saturated = false; 3500 if (shift_type == 0)
3154 rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated); 3501 rn_val <<= shift_amount;
3502 else if (shift_type == 1)
3503 rn_val = ((s32)rn_val >> shift_amount);
3155 3504
3156 if (saturated) 3505 bool saturated = false;
3157 cpu->Cpsr |= (1 << 27); 3506 rn_val = ARMul_SignedSatQ(rn_val, inst_cream->sat_imm, &saturated);
3158 3507
3159 RD = rn_val; 3508 if (saturated)
3160 } 3509 cpu->Cpsr |= (1 << 27);
3161 3510
3162 cpu->Reg[15] += cpu->GetInstructionSize(); 3511 RD = rn_val;
3163 INC_PC(sizeof(ssat_inst));
3164 FETCH_INST;
3165 GOTO_NEXT_INST;
3166 } 3512 }
3167 3513
3168 SSAT16_INST: 3514 cpu->Reg[15] += cpu->GetInstructionSize();
3169 { 3515 INC_PC(sizeof(ssat_inst));
3170 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3516 FETCH_INST;
3171 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; 3517 GOTO_NEXT_INST;
3172 const u8 saturate_to = inst_cream->sat_imm; 3518}
3173 3519
3174 bool sat1 = false; 3520SSAT16_INST : {
3175 bool sat2 = false; 3521 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3522 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
3523 const u8 saturate_to = inst_cream->sat_imm;
3176 3524
3177 RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | 3525 bool sat1 = false;
3178 ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; 3526 bool sat2 = false;
3179 3527
3180 if (sat1 || sat2) 3528 RD = (ARMul_SignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) |
3181 cpu->Cpsr |= (1 << 27); 3529 ARMul_SignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16;
3182 }
3183 3530
3184 cpu->Reg[15] += cpu->GetInstructionSize(); 3531 if (sat1 || sat2)
3185 INC_PC(sizeof(ssat_inst)); 3532 cpu->Cpsr |= (1 << 27);
3186 FETCH_INST; 3533 }
3187 GOTO_NEXT_INST;
3188 }
3189
3190 STC_INST:
3191 {
3192 // Instruction not implemented
3193 //LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
3194 cpu->Reg[15] += cpu->GetInstructionSize();
3195 INC_PC(sizeof(stc_inst));
3196 FETCH_INST;
3197 GOTO_NEXT_INST;
3198 }
3199 STM_INST:
3200 {
3201 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3202 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3203 unsigned int inst = inst_cream->inst;
3204
3205 unsigned int Rn = BITS(inst, 16, 19);
3206 unsigned int old_RN = cpu->Reg[Rn];
3207
3208 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3209 if (BIT(inst_cream->inst, 22) == 1) {
3210 for (int i = 0; i < 13; i++) {
3211 if (BIT(inst_cream->inst, i)) {
3212 cpu->WriteMemory32(addr, cpu->Reg[i]);
3213 addr += 4;
3214 }
3215 }
3216 if (BIT(inst_cream->inst, 13)) {
3217 if (cpu->Mode == USER32MODE)
3218 cpu->WriteMemory32(addr, cpu->Reg[13]);
3219 else
3220 cpu->WriteMemory32(addr, cpu->Reg_usr[0]);
3221 3534
3535 cpu->Reg[15] += cpu->GetInstructionSize();
3536 INC_PC(sizeof(ssat_inst));
3537 FETCH_INST;
3538 GOTO_NEXT_INST;
3539}
3540
3541STC_INST : {
3542 // Instruction not implemented
3543 // LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
3544 cpu->Reg[15] += cpu->GetInstructionSize();
3545 INC_PC(sizeof(stc_inst));
3546 FETCH_INST;
3547 GOTO_NEXT_INST;
3548}
3549STM_INST : {
3550 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3551 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3552 unsigned int inst = inst_cream->inst;
3553
3554 unsigned int Rn = BITS(inst, 16, 19);
3555 unsigned int old_RN = cpu->Reg[Rn];
3556
3557 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3558 if (BIT(inst_cream->inst, 22) == 1) {
3559 for (int i = 0; i < 13; i++) {
3560 if (BIT(inst_cream->inst, i)) {
3561 cpu->WriteMemory32(addr, cpu->Reg[i]);
3222 addr += 4; 3562 addr += 4;
3223 } 3563 }
3224 if (BIT(inst_cream->inst, 14)) { 3564 }
3225 if (cpu->Mode == USER32MODE) 3565 if (BIT(inst_cream->inst, 13)) {
3226 cpu->WriteMemory32(addr, cpu->Reg[14]); 3566 if (cpu->Mode == USER32MODE)
3567 cpu->WriteMemory32(addr, cpu->Reg[13]);
3568 else
3569 cpu->WriteMemory32(addr, cpu->Reg_usr[0]);
3570
3571 addr += 4;
3572 }
3573 if (BIT(inst_cream->inst, 14)) {
3574 if (cpu->Mode == USER32MODE)
3575 cpu->WriteMemory32(addr, cpu->Reg[14]);
3576 else
3577 cpu->WriteMemory32(addr, cpu->Reg_usr[1]);
3578
3579 addr += 4;
3580 }
3581 if (BIT(inst_cream->inst, 15)) {
3582 cpu->WriteMemory32(addr, cpu->Reg[15] + 8);
3583 }
3584 } else {
3585 for (int i = 0; i < 15; i++) {
3586 if (BIT(inst_cream->inst, i)) {
3587 if (i == Rn)
3588 cpu->WriteMemory32(addr, old_RN);
3227 else 3589 else
3228 cpu->WriteMemory32(addr, cpu->Reg_usr[1]); 3590 cpu->WriteMemory32(addr, cpu->Reg[i]);
3229 3591
3230 addr += 4; 3592 addr += 4;
3231 } 3593 }
3232 if (BIT(inst_cream->inst, 15)) { 3594 }
3233 cpu->WriteMemory32(addr, cpu->Reg[15] + 8);
3234 }
3235 } else {
3236 for (int i = 0; i < 15; i++) {
3237 if (BIT(inst_cream->inst, i)) {
3238 if (i == Rn)
3239 cpu->WriteMemory32(addr, old_RN);
3240 else
3241 cpu->WriteMemory32(addr, cpu->Reg[i]);
3242
3243 addr += 4;
3244 }
3245 }
3246 3595
3247 // Check PC reg 3596 // Check PC reg
3248 if (BIT(inst_cream->inst, 15)) { 3597 if (BIT(inst_cream->inst, 15)) {
3249 cpu->WriteMemory32(addr, cpu->Reg[15] + 8); 3598 cpu->WriteMemory32(addr, cpu->Reg[15] + 8);
3250 }
3251 } 3599 }
3252 } 3600 }
3253 cpu->Reg[15] += cpu->GetInstructionSize();
3254 INC_PC(sizeof(ldst_inst));
3255 FETCH_INST;
3256 GOTO_NEXT_INST;
3257 } 3601 }
3258 SXTB_INST: 3602 cpu->Reg[15] += cpu->GetInstructionSize();
3259 { 3603 INC_PC(sizeof(ldst_inst));
3260 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3604 FETCH_INST;
3261 sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component; 3605 GOTO_NEXT_INST;
3606}
3607SXTB_INST : {
3608 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3609 sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
3262 3610
3263 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate); 3611 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate);
3264 if (BIT(operand2, 7)) { 3612 if (BIT(operand2, 7)) {
3265 operand2 |= 0xffffff00; 3613 operand2 |= 0xffffff00;
3266 } else { 3614 } else {
3267 operand2 &= 0xff; 3615 operand2 &= 0xff;
3268 }
3269 RD = operand2;
3270 } 3616 }
3271 cpu->Reg[15] += cpu->GetInstructionSize(); 3617 RD = operand2;
3272 INC_PC(sizeof(sxtb_inst));
3273 FETCH_INST;
3274 GOTO_NEXT_INST;
3275 } 3618 }
3276 STR_INST: 3619 cpu->Reg[15] += cpu->GetInstructionSize();
3277 { 3620 INC_PC(sizeof(sxtb_inst));
3278 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3621 FETCH_INST;
3279 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 3622 GOTO_NEXT_INST;
3280 inst_cream->get_addr(cpu, inst_cream->inst, addr); 3623}
3624STR_INST : {
3625 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3626 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3627 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3281 3628
3282 unsigned int reg = BITS(inst_cream->inst, 12, 15); 3629 unsigned int reg = BITS(inst_cream->inst, 12, 15);
3283 unsigned int value = cpu->Reg[reg]; 3630 unsigned int value = cpu->Reg[reg];
3284 3631
3285 if (reg == 15) 3632 if (reg == 15)
3286 value += 2 * cpu->GetInstructionSize(); 3633 value += 2 * cpu->GetInstructionSize();
3287 3634
3288 cpu->WriteMemory32(addr, value); 3635 cpu->WriteMemory32(addr, value);
3289 }
3290 cpu->Reg[15] += cpu->GetInstructionSize();
3291 INC_PC(sizeof(ldst_inst));
3292 FETCH_INST;
3293 GOTO_NEXT_INST;
3294 }
3295 UXTB_INST:
3296 {
3297 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3298 uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component;
3299 RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
3300 }
3301 cpu->Reg[15] += cpu->GetInstructionSize();
3302 INC_PC(sizeof(uxtb_inst));
3303 FETCH_INST;
3304 GOTO_NEXT_INST;
3305 }
3306 UXTAB_INST:
3307 {
3308 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3309 uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component;
3310
3311 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
3312 RD = RN + operand2;
3313 }
3314 cpu->Reg[15] += cpu->GetInstructionSize();
3315 INC_PC(sizeof(uxtab_inst));
3316 FETCH_INST;
3317 GOTO_NEXT_INST;
3318 }
3319 STRB_INST:
3320 {
3321 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3322 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3323 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3324 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
3325 cpu->WriteMemory8(addr, value);
3326 }
3327 cpu->Reg[15] += cpu->GetInstructionSize();
3328 INC_PC(sizeof(ldst_inst));
3329 FETCH_INST;
3330 GOTO_NEXT_INST;
3331 } 3636 }
3332 STRBT_INST: 3637 cpu->Reg[15] += cpu->GetInstructionSize();
3333 { 3638 INC_PC(sizeof(ldst_inst));
3334 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3639 FETCH_INST;
3335 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 3640 GOTO_NEXT_INST;
3336 inst_cream->get_addr(cpu, inst_cream->inst, addr); 3641}
3642UXTB_INST : {
3643 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3644 uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component;
3645 RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
3646 }
3647 cpu->Reg[15] += cpu->GetInstructionSize();
3648 INC_PC(sizeof(uxtb_inst));
3649 FETCH_INST;
3650 GOTO_NEXT_INST;
3651}
3652UXTAB_INST : {
3653 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3654 uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component;
3337 3655
3338 const u32 previous_mode = cpu->Mode; 3656 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
3339 const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 3657 RD = RN + operand2;
3658 }
3659 cpu->Reg[15] += cpu->GetInstructionSize();
3660 INC_PC(sizeof(uxtab_inst));
3661 FETCH_INST;
3662 GOTO_NEXT_INST;
3663}
3664STRB_INST : {
3665 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3666 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3667 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3668 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
3669 cpu->WriteMemory8(addr, value);
3670 }
3671 cpu->Reg[15] += cpu->GetInstructionSize();
3672 INC_PC(sizeof(ldst_inst));
3673 FETCH_INST;
3674 GOTO_NEXT_INST;
3675}
3676STRBT_INST : {
3677 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3678 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3679 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3340 3680
3341 cpu->ChangePrivilegeMode(USER32MODE); 3681 const u32 previous_mode = cpu->Mode;
3342 cpu->WriteMemory8(addr, value); 3682 const u32 value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
3343 cpu->ChangePrivilegeMode(previous_mode);
3344 }
3345 cpu->Reg[15] += cpu->GetInstructionSize();
3346 INC_PC(sizeof(ldst_inst));
3347 FETCH_INST;
3348 GOTO_NEXT_INST;
3349 }
3350 STRD_INST:
3351 {
3352 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3353 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3354 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3355
3356 // The 3DS doesn't have the Large Physical Access Extension (LPAE)
3357 // so STRD wouldn't store these as a single write.
3358 cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);
3359 cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);
3360 }
3361 cpu->Reg[15] += cpu->GetInstructionSize();
3362 INC_PC(sizeof(ldst_inst));
3363 FETCH_INST;
3364 GOTO_NEXT_INST;
3365 }
3366 STREX_INST:
3367 {
3368 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3369 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3370 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3371
3372 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3373 cpu->UnsetExclusiveMemoryAddress();
3374 cpu->WriteMemory32(write_addr, RM);
3375 RD = 0;
3376 } else {
3377 // Failed to write due to mutex access
3378 RD = 1;
3379 }
3380 }
3381 cpu->Reg[15] += cpu->GetInstructionSize();
3382 INC_PC(sizeof(generic_arm_inst));
3383 FETCH_INST;
3384 GOTO_NEXT_INST;
3385 }
3386 STREXB_INST:
3387 {
3388 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3389 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3390 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3391
3392 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3393 cpu->UnsetExclusiveMemoryAddress();
3394 cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]);
3395 RD = 0;
3396 } else {
3397 // Failed to write due to mutex access
3398 RD = 1;
3399 }
3400 }
3401 cpu->Reg[15] += cpu->GetInstructionSize();
3402 INC_PC(sizeof(generic_arm_inst));
3403 FETCH_INST;
3404 GOTO_NEXT_INST;
3405 }
3406 STREXD_INST:
3407 {
3408 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3409 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3410 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3411
3412 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3413 cpu->UnsetExclusiveMemoryAddress();
3414
3415 const u32 rt = cpu->Reg[inst_cream->Rm + 0];
3416 const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
3417 u64 value;
3418
3419 if (cpu->InBigEndianMode())
3420 value = (((u64)rt << 32) | rt2);
3421 else
3422 value = (((u64)rt2 << 32) | rt);
3423 3683
3424 cpu->WriteMemory64(write_addr, value); 3684 cpu->ChangePrivilegeMode(USER32MODE);
3425 RD = 0; 3685 cpu->WriteMemory8(addr, value);
3426 } 3686 cpu->ChangePrivilegeMode(previous_mode);
3427 else { 3687 }
3428 // Failed to write due to mutex access 3688 cpu->Reg[15] += cpu->GetInstructionSize();
3429 RD = 1; 3689 INC_PC(sizeof(ldst_inst));
3430 } 3690 FETCH_INST;
3431 } 3691 GOTO_NEXT_INST;
3432 cpu->Reg[15] += cpu->GetInstructionSize(); 3692}
3433 INC_PC(sizeof(generic_arm_inst)); 3693STRD_INST : {
3434 FETCH_INST; 3694 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3435 GOTO_NEXT_INST; 3695 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3436 } 3696 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3437 STREXH_INST: 3697
3438 { 3698 // The 3DS doesn't have the Large Physical Access Extension (LPAE)
3439 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3699 // so STRD wouldn't store these as a single write.
3440 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component; 3700 cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);
3441 unsigned int write_addr = cpu->Reg[inst_cream->Rn]; 3701 cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);
3442 3702 }
3443 if (cpu->IsExclusiveMemoryAccess(write_addr)) { 3703 cpu->Reg[15] += cpu->GetInstructionSize();
3444 cpu->UnsetExclusiveMemoryAddress(); 3704 INC_PC(sizeof(ldst_inst));
3445 cpu->WriteMemory16(write_addr, RM); 3705 FETCH_INST;
3446 RD = 0; 3706 GOTO_NEXT_INST;
3447 } else { 3707}
3448 // Failed to write due to mutex access 3708STREX_INST : {
3449 RD = 1; 3709 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3450 } 3710 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3711 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3712
3713 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3714 cpu->UnsetExclusiveMemoryAddress();
3715 cpu->WriteMemory32(write_addr, RM);
3716 RD = 0;
3717 } else {
3718 // Failed to write due to mutex access
3719 RD = 1;
3451 } 3720 }
3452 cpu->Reg[15] += cpu->GetInstructionSize(); 3721 }
3453 INC_PC(sizeof(generic_arm_inst)); 3722 cpu->Reg[15] += cpu->GetInstructionSize();
3454 FETCH_INST; 3723 INC_PC(sizeof(generic_arm_inst));
3455 GOTO_NEXT_INST; 3724 FETCH_INST;
3456 } 3725 GOTO_NEXT_INST;
3457 STRH_INST: 3726}
3458 { 3727STREXB_INST : {
3459 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3728 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3460 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 3729 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3461 inst_cream->get_addr(cpu, inst_cream->inst, addr); 3730 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3462 3731
3463 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; 3732 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3464 cpu->WriteMemory16(addr, value); 3733 cpu->UnsetExclusiveMemoryAddress();
3734 cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]);
3735 RD = 0;
3736 } else {
3737 // Failed to write due to mutex access
3738 RD = 1;
3465 } 3739 }
3466 cpu->Reg[15] += cpu->GetInstructionSize();
3467 INC_PC(sizeof(ldst_inst));
3468 FETCH_INST;
3469 GOTO_NEXT_INST;
3470 } 3740 }
3471 STRT_INST: 3741 cpu->Reg[15] += cpu->GetInstructionSize();
3472 { 3742 INC_PC(sizeof(generic_arm_inst));
3473 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3743 FETCH_INST;
3474 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 3744 GOTO_NEXT_INST;
3475 inst_cream->get_addr(cpu, inst_cream->inst, addr); 3745}
3746STREXD_INST : {
3747 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3748 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3749 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3476 3750
3477 const u32 previous_mode = cpu->Mode; 3751 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3478 const u32 rt_index = BITS(inst_cream->inst, 12, 15); 3752 cpu->UnsetExclusiveMemoryAddress();
3479 3753
3480 u32 value = cpu->Reg[rt_index]; 3754 const u32 rt = cpu->Reg[inst_cream->Rm + 0];
3481 if (rt_index == 15) 3755 const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
3482 value += 2 * cpu->GetInstructionSize(); 3756 u64 value;
3483 3757
3484 cpu->ChangePrivilegeMode(USER32MODE); 3758 if (cpu->InBigEndianMode())
3485 cpu->WriteMemory32(addr, value); 3759 value = (((u64)rt << 32) | rt2);
3486 cpu->ChangePrivilegeMode(previous_mode); 3760 else
3761 value = (((u64)rt2 << 32) | rt);
3762
3763 cpu->WriteMemory64(write_addr, value);
3764 RD = 0;
3765 } else {
3766 // Failed to write due to mutex access
3767 RD = 1;
3487 } 3768 }
3488 cpu->Reg[15] += cpu->GetInstructionSize();
3489 INC_PC(sizeof(ldst_inst));
3490 FETCH_INST;
3491 GOTO_NEXT_INST;
3492 } 3769 }
3493 SUB_INST: 3770 cpu->Reg[15] += cpu->GetInstructionSize();
3494 { 3771 INC_PC(sizeof(generic_arm_inst));
3495 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3772 FETCH_INST;
3496 sub_inst* const inst_cream = (sub_inst*)inst_base->component; 3773 GOTO_NEXT_INST;
3774}
3775STREXH_INST : {
3776 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3777 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
3778 unsigned int write_addr = cpu->Reg[inst_cream->Rn];
3779
3780 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
3781 cpu->UnsetExclusiveMemoryAddress();
3782 cpu->WriteMemory16(write_addr, RM);
3783 RD = 0;
3784 } else {
3785 // Failed to write due to mutex access
3786 RD = 1;
3787 }
3788 }
3789 cpu->Reg[15] += cpu->GetInstructionSize();
3790 INC_PC(sizeof(generic_arm_inst));
3791 FETCH_INST;
3792 GOTO_NEXT_INST;
3793}
3794STRH_INST : {
3795 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3796 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3797 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3497 3798
3498 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn); 3799 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
3800 cpu->WriteMemory16(addr, value);
3801 }
3802 cpu->Reg[15] += cpu->GetInstructionSize();
3803 INC_PC(sizeof(ldst_inst));
3804 FETCH_INST;
3805 GOTO_NEXT_INST;
3806}
3807STRT_INST : {
3808 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3809 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
3810 inst_cream->get_addr(cpu, inst_cream->inst, addr);
3499 3811
3500 bool carry; 3812 const u32 previous_mode = cpu->Mode;
3501 bool overflow; 3813 const u32 rt_index = BITS(inst_cream->inst, 12, 15);
3502 RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
3503 3814
3504 if (inst_cream->S && (inst_cream->Rd == 15)) { 3815 u32 value = cpu->Reg[rt_index];
3505 if (CurrentModeHasSPSR) { 3816 if (rt_index == 15)
3506 cpu->Cpsr = cpu->Spsr_copy; 3817 value += 2 * cpu->GetInstructionSize();
3507 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
3508 LOAD_NZCVT;
3509 }
3510 } else if (inst_cream->S) {
3511 UPDATE_NFLAG(RD);
3512 UPDATE_ZFLAG(RD);
3513 cpu->CFlag = carry;
3514 cpu->VFlag = overflow;
3515 }
3516 if (inst_cream->Rd == 15) {
3517 INC_PC(sizeof(sub_inst));
3518 goto DISPATCH;
3519 }
3520 }
3521 cpu->Reg[15] += cpu->GetInstructionSize();
3522 INC_PC(sizeof(sub_inst));
3523 FETCH_INST;
3524 GOTO_NEXT_INST;
3525 }
3526 SWI_INST:
3527 {
3528 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3529 swi_inst* const inst_cream = (swi_inst*)inst_base->component;
3530 SVC::CallSVC(inst_cream->num & 0xFFFF);
3531 }
3532 3818
3533 cpu->Reg[15] += cpu->GetInstructionSize(); 3819 cpu->ChangePrivilegeMode(USER32MODE);
3534 INC_PC(sizeof(swi_inst)); 3820 cpu->WriteMemory32(addr, value);
3535 FETCH_INST; 3821 cpu->ChangePrivilegeMode(previous_mode);
3536 GOTO_NEXT_INST;
3537 } 3822 }
3538 SWP_INST: 3823 cpu->Reg[15] += cpu->GetInstructionSize();
3539 { 3824 INC_PC(sizeof(ldst_inst));
3540 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3825 FETCH_INST;
3541 swp_inst* inst_cream = (swp_inst*)inst_base->component; 3826 GOTO_NEXT_INST;
3827}
3828SUB_INST : {
3829 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3830 sub_inst* const inst_cream = (sub_inst*)inst_base->component;
3542 3831
3543 addr = RN; 3832 u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
3544 unsigned int value = cpu->ReadMemory32(addr);
3545 cpu->WriteMemory32(addr, RM);
3546 3833
3547 RD = value; 3834 bool carry;
3835 bool overflow;
3836 RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
3837
3838 if (inst_cream->S && (inst_cream->Rd == 15)) {
3839 if (CurrentModeHasSPSR) {
3840 cpu->Cpsr = cpu->Spsr_copy;
3841 cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
3842 LOAD_NZCVT;
3843 }
3844 } else if (inst_cream->S) {
3845 UPDATE_NFLAG(RD);
3846 UPDATE_ZFLAG(RD);
3847 cpu->CFlag = carry;
3848 cpu->VFlag = overflow;
3548 } 3849 }
3549 cpu->Reg[15] += cpu->GetInstructionSize(); 3850 if (inst_cream->Rd == 15) {
3550 INC_PC(sizeof(swp_inst)); 3851 INC_PC(sizeof(sub_inst));
3551 FETCH_INST; 3852 goto DISPATCH;
3552 GOTO_NEXT_INST;
3553 }
3554 SWPB_INST:
3555 {
3556 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3557 swp_inst* inst_cream = (swp_inst*)inst_base->component;
3558 addr = RN;
3559 unsigned int value = cpu->ReadMemory8(addr);
3560 cpu->WriteMemory8(addr, (RM & 0xFF));
3561 RD = value;
3562 } 3853 }
3563 cpu->Reg[15] += cpu->GetInstructionSize();
3564 INC_PC(sizeof(swp_inst));
3565 FETCH_INST;
3566 GOTO_NEXT_INST;
3567 } 3854 }
3568 SXTAB_INST: 3855 cpu->Reg[15] += cpu->GetInstructionSize();
3569 { 3856 INC_PC(sizeof(sub_inst));
3570 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3857 FETCH_INST;
3571 sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component; 3858 GOTO_NEXT_INST;
3859}
3860SWI_INST : {
3861 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3862 swi_inst* const inst_cream = (swi_inst*)inst_base->component;
3863 SVC::CallSVC(inst_cream->num & 0xFFFF);
3864 }
3572 3865
3573 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff; 3866 cpu->Reg[15] += cpu->GetInstructionSize();
3867 INC_PC(sizeof(swi_inst));
3868 FETCH_INST;
3869 GOTO_NEXT_INST;
3870}
3871SWP_INST : {
3872 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3873 swp_inst* inst_cream = (swp_inst*)inst_base->component;
3574 3874
3575 // Sign extend for byte 3875 addr = RN;
3576 operand2 = (0x80 & operand2)? (0xFFFFFF00 | operand2):operand2; 3876 unsigned int value = cpu->ReadMemory32(addr);
3577 RD = RN + operand2; 3877 cpu->WriteMemory32(addr, RM);
3578 }
3579 cpu->Reg[15] += cpu->GetInstructionSize();
3580 INC_PC(sizeof(uxtab_inst));
3581 FETCH_INST;
3582 GOTO_NEXT_INST;
3583 }
3584
3585 SXTAB16_INST:
3586 SXTB16_INST:
3587 {
3588 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3589 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
3590
3591 const u8 rotation = inst_cream->rotate * 8;
3592 u32 rm_val = RM;
3593 u32 rn_val = RN;
3594
3595 if (rotation)
3596 rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
3597
3598 // SXTB16
3599 if (inst_cream->Rn == 15) {
3600 u32 lo = (u32)(s8)rm_val;
3601 u32 hi = (u32)(s8)(rm_val >> 16);
3602 RD = (lo | (hi << 16));
3603 }
3604 // SXTAB16
3605 else {
3606 u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF);
3607 u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF);
3608 RD = (lo | (hi << 16));
3609 }
3610 }
3611 3878
3612 cpu->Reg[15] += cpu->GetInstructionSize(); 3879 RD = value;
3613 INC_PC(sizeof(sxtab_inst));
3614 FETCH_INST;
3615 GOTO_NEXT_INST;
3616 } 3880 }
3881 cpu->Reg[15] += cpu->GetInstructionSize();
3882 INC_PC(sizeof(swp_inst));
3883 FETCH_INST;
3884 GOTO_NEXT_INST;
3885}
3886SWPB_INST : {
3887 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3888 swp_inst* inst_cream = (swp_inst*)inst_base->component;
3889 addr = RN;
3890 unsigned int value = cpu->ReadMemory8(addr);
3891 cpu->WriteMemory8(addr, (RM & 0xFF));
3892 RD = value;
3893 }
3894 cpu->Reg[15] += cpu->GetInstructionSize();
3895 INC_PC(sizeof(swp_inst));
3896 FETCH_INST;
3897 GOTO_NEXT_INST;
3898}
3899SXTAB_INST : {
3900 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3901 sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component;
3617 3902
3618 SXTAH_INST: 3903 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
3619 {
3620 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3621 sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
3622 3904
3623 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff; 3905 // Sign extend for byte
3624 // Sign extend for half 3906 operand2 = (0x80 & operand2) ? (0xFFFFFF00 | operand2) : operand2;
3625 operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2; 3907 RD = RN + operand2;
3626 RD = RN + operand2;
3627 }
3628 cpu->Reg[15] += cpu->GetInstructionSize();
3629 INC_PC(sizeof(sxtah_inst));
3630 FETCH_INST;
3631 GOTO_NEXT_INST;
3632 } 3908 }
3909 cpu->Reg[15] += cpu->GetInstructionSize();
3910 INC_PC(sizeof(uxtab_inst));
3911 FETCH_INST;
3912 GOTO_NEXT_INST;
3913}
3633 3914
3634 TEQ_INST: 3915SXTAB16_INST:
3635 { 3916SXTB16_INST : {
3636 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 3917 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3637 teq_inst* const inst_cream = (teq_inst*)inst_base->component; 3918 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
3638
3639 u32 lop = RN;
3640 u32 rop = SHIFTER_OPERAND;
3641 3919
3642 if (inst_cream->Rn == 15) 3920 const u8 rotation = inst_cream->rotate * 8;
3643 lop += cpu->GetInstructionSize() * 2; 3921 u32 rm_val = RM;
3922 u32 rn_val = RN;
3644 3923
3645 u32 result = lop ^ rop; 3924 if (rotation)
3925 rm_val = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
3646 3926
3647 UPDATE_NFLAG(result); 3927 // SXTB16
3648 UPDATE_ZFLAG(result); 3928 if (inst_cream->Rn == 15) {
3649 UPDATE_CFLAG_WITH_SC; 3929 u32 lo = (u32)(s8)rm_val;
3930 u32 hi = (u32)(s8)(rm_val >> 16);
3931 RD = (lo | (hi << 16));
3932 }
3933 // SXTAB16
3934 else {
3935 u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF);
3936 u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF);
3937 RD = (lo | (hi << 16));
3650 } 3938 }
3651 cpu->Reg[15] += cpu->GetInstructionSize();
3652 INC_PC(sizeof(teq_inst));
3653 FETCH_INST;
3654 GOTO_NEXT_INST;
3655 } 3939 }
3656 TST_INST:
3657 {
3658 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3659 tst_inst* const inst_cream = (tst_inst*)inst_base->component;
3660 3940
3661 u32 lop = RN; 3941 cpu->Reg[15] += cpu->GetInstructionSize();
3662 u32 rop = SHIFTER_OPERAND; 3942 INC_PC(sizeof(sxtab_inst));
3663 3943 FETCH_INST;
3664 if (inst_cream->Rn == 15) 3944 GOTO_NEXT_INST;
3665 lop += cpu->GetInstructionSize() * 2; 3945}
3666 3946
3667 u32 result = lop & rop; 3947SXTAH_INST : {
3948 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3949 sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
3668 3950
3669 UPDATE_NFLAG(result); 3951 unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
3670 UPDATE_ZFLAG(result); 3952 // Sign extend for half
3671 UPDATE_CFLAG_WITH_SC; 3953 operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2;
3672 } 3954 RD = RN + operand2;
3673 cpu->Reg[15] += cpu->GetInstructionSize(); 3955 }
3674 INC_PC(sizeof(tst_inst)); 3956 cpu->Reg[15] += cpu->GetInstructionSize();
3675 FETCH_INST; 3957 INC_PC(sizeof(sxtah_inst));
3676 GOTO_NEXT_INST; 3958 FETCH_INST;
3677 } 3959 GOTO_NEXT_INST;
3678 3960}
3679 UADD8_INST:
3680 UADD16_INST:
3681 UADDSUBX_INST:
3682 USUB8_INST:
3683 USUB16_INST:
3684 USUBADDX_INST:
3685 {
3686 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3687 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
3688
3689 const u8 op2 = inst_cream->op2;
3690 const u32 rm_val = RM;
3691 const u32 rn_val = RN;
3692 3961
3693 s32 lo_result = 0; 3962TEQ_INST : {
3694 s32 hi_result = 0; 3963 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3964 teq_inst* const inst_cream = (teq_inst*)inst_base->component;
3695 3965
3696 // UADD16 3966 u32 lop = RN;
3697 if (op2 == 0x00) { 3967 u32 rop = SHIFTER_OPERAND;
3698 lo_result = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
3699 hi_result = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
3700
3701 if (lo_result & 0xFFFF0000) {
3702 cpu->Cpsr |= (1 << 16);
3703 cpu->Cpsr |= (1 << 17);
3704 } else {
3705 cpu->Cpsr &= ~(1 << 16);
3706 cpu->Cpsr &= ~(1 << 17);
3707 }
3708 3968
3709 if (hi_result & 0xFFFF0000) { 3969 if (inst_cream->Rn == 15)
3710 cpu->Cpsr |= (1 << 18); 3970 lop += cpu->GetInstructionSize() * 2;
3711 cpu->Cpsr |= (1 << 19);
3712 } else {
3713 cpu->Cpsr &= ~(1 << 18);
3714 cpu->Cpsr &= ~(1 << 19);
3715 }
3716 }
3717 // UASX
3718 else if (op2 == 0x01) {
3719 lo_result = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
3720 hi_result = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
3721
3722 if (lo_result >= 0) {
3723 cpu->Cpsr |= (1 << 16);
3724 cpu->Cpsr |= (1 << 17);
3725 } else {
3726 cpu->Cpsr &= ~(1 << 16);
3727 cpu->Cpsr &= ~(1 << 17);
3728 }
3729 3971
3730 if (hi_result >= 0x10000) { 3972 u32 result = lop ^ rop;
3731 cpu->Cpsr |= (1 << 18);
3732 cpu->Cpsr |= (1 << 19);
3733 } else {
3734 cpu->Cpsr &= ~(1 << 18);
3735 cpu->Cpsr &= ~(1 << 19);
3736 }
3737 }
3738 // USAX
3739 else if (op2 == 0x02) {
3740 lo_result = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
3741 hi_result = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
3742
3743 if (lo_result >= 0x10000) {
3744 cpu->Cpsr |= (1 << 16);
3745 cpu->Cpsr |= (1 << 17);
3746 } else {
3747 cpu->Cpsr &= ~(1 << 16);
3748 cpu->Cpsr &= ~(1 << 17);
3749 }
3750 3973
3751 if (hi_result >= 0) { 3974 UPDATE_NFLAG(result);
3752 cpu->Cpsr |= (1 << 18); 3975 UPDATE_ZFLAG(result);
3753 cpu->Cpsr |= (1 << 19); 3976 UPDATE_CFLAG_WITH_SC;
3754 } else { 3977 }
3755 cpu->Cpsr &= ~(1 << 18); 3978 cpu->Reg[15] += cpu->GetInstructionSize();
3756 cpu->Cpsr &= ~(1 << 19); 3979 INC_PC(sizeof(teq_inst));
3757 } 3980 FETCH_INST;
3758 } 3981 GOTO_NEXT_INST;
3759 // USUB16 3982}
3760 else if (op2 == 0x03) { 3983TST_INST : {
3761 lo_result = (rn_val & 0xFFFF) - (rm_val & 0xFFFF); 3984 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3762 hi_result = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF); 3985 tst_inst* const inst_cream = (tst_inst*)inst_base->component;
3763
3764 if ((lo_result & 0xFFFF0000) == 0) {
3765 cpu->Cpsr |= (1 << 16);
3766 cpu->Cpsr |= (1 << 17);
3767 } else {
3768 cpu->Cpsr &= ~(1 << 16);
3769 cpu->Cpsr &= ~(1 << 17);
3770 }
3771 3986
3772 if ((hi_result & 0xFFFF0000) == 0) { 3987 u32 lop = RN;
3773 cpu->Cpsr |= (1 << 18); 3988 u32 rop = SHIFTER_OPERAND;
3774 cpu->Cpsr |= (1 << 19);
3775 } else {
3776 cpu->Cpsr &= ~(1 << 18);
3777 cpu->Cpsr &= ~(1 << 19);
3778 }
3779 }
3780 // UADD8
3781 else if (op2 == 0x04) {
3782 s16 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
3783 s16 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
3784 s16 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
3785 s16 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
3786
3787 if (sum1 >= 0x100)
3788 cpu->Cpsr |= (1 << 16);
3789 else
3790 cpu->Cpsr &= ~(1 << 16);
3791 3989
3792 if (sum2 >= 0x100) 3990 if (inst_cream->Rn == 15)
3793 cpu->Cpsr |= (1 << 17); 3991 lop += cpu->GetInstructionSize() * 2;
3794 else
3795 cpu->Cpsr &= ~(1 << 17);
3796 3992
3797 if (sum3 >= 0x100) 3993 u32 result = lop & rop;
3798 cpu->Cpsr |= (1 << 18);
3799 else
3800 cpu->Cpsr &= ~(1 << 18);
3801 3994
3802 if (sum4 >= 0x100) 3995 UPDATE_NFLAG(result);
3803 cpu->Cpsr |= (1 << 19); 3996 UPDATE_ZFLAG(result);
3804 else 3997 UPDATE_CFLAG_WITH_SC;
3805 cpu->Cpsr &= ~(1 << 19); 3998 }
3999 cpu->Reg[15] += cpu->GetInstructionSize();
4000 INC_PC(sizeof(tst_inst));
4001 FETCH_INST;
4002 GOTO_NEXT_INST;
4003}
3806 4004
3807 lo_result = ((sum1 & 0xFF) | (sum2 & 0xFF) << 8); 4005UADD8_INST:
3808 hi_result = ((sum3 & 0xFF) | (sum4 & 0xFF) << 8); 4006UADD16_INST:
4007UADDSUBX_INST:
4008USUB8_INST:
4009USUB16_INST:
4010USUBADDX_INST : {
4011 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4012 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
4013
4014 const u8 op2 = inst_cream->op2;
4015 const u32 rm_val = RM;
4016 const u32 rn_val = RN;
4017
4018 s32 lo_result = 0;
4019 s32 hi_result = 0;
4020
4021 // UADD16
4022 if (op2 == 0x00) {
4023 lo_result = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
4024 hi_result = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
4025
4026 if (lo_result & 0xFFFF0000) {
4027 cpu->Cpsr |= (1 << 16);
4028 cpu->Cpsr |= (1 << 17);
4029 } else {
4030 cpu->Cpsr &= ~(1 << 16);
4031 cpu->Cpsr &= ~(1 << 17);
3809 } 4032 }
3810 // USUB8
3811 else if (op2 == 0x07) {
3812 s16 diff1 = (rn_val & 0xFF) - (rm_val & 0xFF);
3813 s16 diff2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
3814 s16 diff3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
3815 s16 diff4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
3816
3817 if (diff1 >= 0)
3818 cpu->Cpsr |= (1 << 16);
3819 else
3820 cpu->Cpsr &= ~(1 << 16);
3821 4033
3822 if (diff2 >= 0) 4034 if (hi_result & 0xFFFF0000) {
3823 cpu->Cpsr |= (1 << 17); 4035 cpu->Cpsr |= (1 << 18);
3824 else 4036 cpu->Cpsr |= (1 << 19);
3825 cpu->Cpsr &= ~(1 << 17); 4037 } else {
3826 4038 cpu->Cpsr &= ~(1 << 18);
3827 if (diff3 >= 0) 4039 cpu->Cpsr &= ~(1 << 19);
3828 cpu->Cpsr |= (1 << 18);
3829 else
3830 cpu->Cpsr &= ~(1 << 18);
3831
3832 if (diff4 >= 0)
3833 cpu->Cpsr |= (1 << 19);
3834 else
3835 cpu->Cpsr &= ~(1 << 19);
3836
3837 lo_result = (diff1 & 0xFF) | ((diff2 & 0xFF) << 8);
3838 hi_result = (diff3 & 0xFF) | ((diff4 & 0xFF) << 8);
3839 } 4040 }
3840
3841 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
3842 } 4041 }
4042 // UASX
4043 else if (op2 == 0x01) {
4044 lo_result = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
4045 hi_result = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
4046
4047 if (lo_result >= 0) {
4048 cpu->Cpsr |= (1 << 16);
4049 cpu->Cpsr |= (1 << 17);
4050 } else {
4051 cpu->Cpsr &= ~(1 << 16);
4052 cpu->Cpsr &= ~(1 << 17);
4053 }
3843 4054
3844 cpu->Reg[15] += cpu->GetInstructionSize(); 4055 if (hi_result >= 0x10000) {
3845 INC_PC(sizeof(generic_arm_inst)); 4056 cpu->Cpsr |= (1 << 18);
3846 FETCH_INST; 4057 cpu->Cpsr |= (1 << 19);
3847 GOTO_NEXT_INST; 4058 } else {
3848 } 4059 cpu->Cpsr &= ~(1 << 18);
3849 4060 cpu->Cpsr &= ~(1 << 19);
3850 UHADD8_INST: 4061 }
3851 UHADD16_INST: 4062 }
3852 UHADDSUBX_INST: 4063 // USAX
3853 UHSUBADDX_INST: 4064 else if (op2 == 0x02) {
3854 UHSUB8_INST: 4065 lo_result = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
3855 UHSUB16_INST: 4066 hi_result = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
3856 { 4067
3857 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4068 if (lo_result >= 0x10000) {
3858 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 4069 cpu->Cpsr |= (1 << 16);
3859 const u32 rm_val = RM; 4070 cpu->Cpsr |= (1 << 17);
3860 const u32 rn_val = RN; 4071 } else {
3861 const u8 op2 = inst_cream->op2; 4072 cpu->Cpsr &= ~(1 << 16);
3862 4073 cpu->Cpsr &= ~(1 << 17);
3863 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03)
3864 {
3865 u32 lo_val = 0;
3866 u32 hi_val = 0;
3867
3868 // UHADD16
3869 if (op2 == 0x00) {
3870 lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
3871 hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
3872 }
3873 // UHASX
3874 else if (op2 == 0x01) {
3875 lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
3876 hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
3877 }
3878 // UHSAX
3879 else if (op2 == 0x02) {
3880 lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
3881 hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
3882 }
3883 // UHSUB16
3884 else if (op2 == 0x03) {
3885 lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF);
3886 hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
3887 }
3888
3889 lo_val >>= 1;
3890 hi_val >>= 1;
3891
3892 RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16);
3893 } 4074 }
3894 else if (op2 == 0x04 || op2 == 0x07) {
3895 u32 sum1;
3896 u32 sum2;
3897 u32 sum3;
3898 u32 sum4;
3899
3900 // UHADD8
3901 if (op2 == 0x04) {
3902 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
3903 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
3904 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
3905 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
3906 }
3907 // UHSUB8
3908 else {
3909 sum1 = (rn_val & 0xFF) - (rm_val & 0xFF);
3910 sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
3911 sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
3912 sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
3913 }
3914 4075
3915 sum1 >>= 1; 4076 if (hi_result >= 0) {
3916 sum2 >>= 1; 4077 cpu->Cpsr |= (1 << 18);
3917 sum3 >>= 1; 4078 cpu->Cpsr |= (1 << 19);
3918 sum4 >>= 1; 4079 } else {
4080 cpu->Cpsr &= ~(1 << 18);
4081 cpu->Cpsr &= ~(1 << 19);
4082 }
4083 }
4084 // USUB16
4085 else if (op2 == 0x03) {
4086 lo_result = (rn_val & 0xFFFF) - (rm_val & 0xFFFF);
4087 hi_result = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
4088
4089 if ((lo_result & 0xFFFF0000) == 0) {
4090 cpu->Cpsr |= (1 << 16);
4091 cpu->Cpsr |= (1 << 17);
4092 } else {
4093 cpu->Cpsr &= ~(1 << 16);
4094 cpu->Cpsr &= ~(1 << 17);
4095 }
3919 4096
3920 RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) | ((sum4 & 0xFF) << 24); 4097 if ((hi_result & 0xFFFF0000) == 0) {
4098 cpu->Cpsr |= (1 << 18);
4099 cpu->Cpsr |= (1 << 19);
4100 } else {
4101 cpu->Cpsr &= ~(1 << 18);
4102 cpu->Cpsr &= ~(1 << 19);
3921 } 4103 }
3922 } 4104 }
4105 // UADD8
4106 else if (op2 == 0x04) {
4107 s16 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
4108 s16 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
4109 s16 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
4110 s16 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
4111
4112 if (sum1 >= 0x100)
4113 cpu->Cpsr |= (1 << 16);
4114 else
4115 cpu->Cpsr &= ~(1 << 16);
3923 4116
3924 cpu->Reg[15] += cpu->GetInstructionSize(); 4117 if (sum2 >= 0x100)
3925 INC_PC(sizeof(generic_arm_inst)); 4118 cpu->Cpsr |= (1 << 17);
3926 FETCH_INST; 4119 else
3927 GOTO_NEXT_INST; 4120 cpu->Cpsr &= ~(1 << 17);
3928 }
3929 4121
3930 UMAAL_INST: 4122 if (sum3 >= 0x100)
3931 { 4123 cpu->Cpsr |= (1 << 18);
3932 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4124 else
3933 umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; 4125 cpu->Cpsr &= ~(1 << 18);
3934 const u64 rm = RM;
3935 const u64 rn = RN;
3936 const u64 rd_lo = RDLO;
3937 const u64 rd_hi = RDHI;
3938 const u64 result = (rm * rn) + rd_lo + rd_hi;
3939 4126
3940 RDLO = (result & 0xFFFFFFFF); 4127 if (sum4 >= 0x100)
3941 RDHI = ((result >> 32) & 0xFFFFFFFF); 4128 cpu->Cpsr |= (1 << 19);
3942 } 4129 else
3943 cpu->Reg[15] += cpu->GetInstructionSize(); 4130 cpu->Cpsr &= ~(1 << 19);
3944 INC_PC(sizeof(umaal_inst)); 4131
3945 FETCH_INST; 4132 lo_result = ((sum1 & 0xFF) | (sum2 & 0xFF) << 8);
3946 GOTO_NEXT_INST; 4133 hi_result = ((sum3 & 0xFF) | (sum4 & 0xFF) << 8);
3947 }
3948 UMLAL_INST:
3949 {
3950 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3951 umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
3952 unsigned long long int rm = RM;
3953 unsigned long long int rs = RS;
3954 unsigned long long int rst = rm * rs;
3955 unsigned long long int add = ((unsigned long long) RDHI)<<32;
3956 add += RDLO;
3957 rst += add;
3958 RDLO = BITS(rst, 0, 31);
3959 RDHI = BITS(rst, 32, 63);
3960
3961 if (inst_cream->S) {
3962 cpu->NFlag = BIT(RDHI, 31);
3963 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
3964 }
3965 }
3966 cpu->Reg[15] += cpu->GetInstructionSize();
3967 INC_PC(sizeof(umlal_inst));
3968 FETCH_INST;
3969 GOTO_NEXT_INST;
3970 }
3971 UMULL_INST:
3972 {
3973 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
3974 umull_inst* inst_cream = (umull_inst*)inst_base->component;
3975 unsigned long long int rm = RM;
3976 unsigned long long int rs = RS;
3977 unsigned long long int rst = rm * rs;
3978 RDHI = BITS(rst, 32, 63);
3979 RDLO = BITS(rst, 0, 31);
3980
3981 if (inst_cream->S) {
3982 cpu->NFlag = BIT(RDHI, 31);
3983 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
3984 }
3985 } 4134 }
3986 cpu->Reg[15] += cpu->GetInstructionSize(); 4135 // USUB8
3987 INC_PC(sizeof(umull_inst)); 4136 else if (op2 == 0x07) {
3988 FETCH_INST; 4137 s16 diff1 = (rn_val & 0xFF) - (rm_val & 0xFF);
3989 GOTO_NEXT_INST; 4138 s16 diff2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
3990 } 4139 s16 diff3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
3991 B_2_THUMB: 4140 s16 diff4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
3992 { 4141
3993 b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component; 4142 if (diff1 >= 0)
3994 cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; 4143 cpu->Cpsr |= (1 << 16);
3995 INC_PC(sizeof(b_2_thumb)); 4144 else
3996 goto DISPATCH; 4145 cpu->Cpsr &= ~(1 << 16);
3997 }
3998 B_COND_THUMB:
3999 {
4000 b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component;
4001 4146
4002 if(CondPassed(cpu, inst_cream->cond)) 4147 if (diff2 >= 0)
4003 cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm; 4148 cpu->Cpsr |= (1 << 17);
4004 else 4149 else
4005 cpu->Reg[15] += 2; 4150 cpu->Cpsr &= ~(1 << 17);
4006 4151
4007 INC_PC(sizeof(b_cond_thumb)); 4152 if (diff3 >= 0)
4008 goto DISPATCH; 4153 cpu->Cpsr |= (1 << 18);
4009 } 4154 else
4010 BL_1_THUMB: 4155 cpu->Cpsr &= ~(1 << 18);
4011 {
4012 bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component;
4013 cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm;
4014 cpu->Reg[15] += cpu->GetInstructionSize();
4015 INC_PC(sizeof(bl_1_thumb));
4016 FETCH_INST;
4017 GOTO_NEXT_INST;
4018 }
4019 BL_2_THUMB:
4020 {
4021 bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component;
4022 int tmp = ((cpu->Reg[15] + 2) | 1);
4023 cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm);
4024 cpu->Reg[14] = tmp;
4025 INC_PC(sizeof(bl_2_thumb));
4026 goto DISPATCH;
4027 }
4028 BLX_1_THUMB:
4029 {
4030 // BLX 1 for armv5t and above
4031 u32 tmp = cpu->Reg[15];
4032 blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component;
4033 cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC;
4034 cpu->Reg[14] = ((tmp + 2) | 1);
4035 cpu->TFlag = 0;
4036 INC_PC(sizeof(blx_1_thumb));
4037 goto DISPATCH;
4038 }
4039 4156
4040 UQADD8_INST: 4157 if (diff4 >= 0)
4041 UQADD16_INST: 4158 cpu->Cpsr |= (1 << 19);
4042 UQADDSUBX_INST: 4159 else
4043 UQSUB8_INST: 4160 cpu->Cpsr &= ~(1 << 19);
4044 UQSUB16_INST:
4045 UQSUBADDX_INST:
4046 {
4047 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4048 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
4049 4161
4050 const u8 op2 = inst_cream->op2; 4162 lo_result = (diff1 & 0xFF) | ((diff2 & 0xFF) << 8);
4051 const u32 rm_val = RM; 4163 hi_result = (diff3 & 0xFF) | ((diff4 & 0xFF) << 8);
4052 const u32 rn_val = RN; 4164 }
4053 4165
4054 u16 lo_val = 0; 4166 RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
4055 u16 hi_val = 0; 4167 }
4056 4168
4057 // UQADD16 4169 cpu->Reg[15] += cpu->GetInstructionSize();
4170 INC_PC(sizeof(generic_arm_inst));
4171 FETCH_INST;
4172 GOTO_NEXT_INST;
4173}
4174
4175UHADD8_INST:
4176UHADD16_INST:
4177UHADDSUBX_INST:
4178UHSUBADDX_INST:
4179UHSUB8_INST:
4180UHSUB16_INST : {
4181 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4182 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
4183 const u32 rm_val = RM;
4184 const u32 rn_val = RN;
4185 const u8 op2 = inst_cream->op2;
4186
4187 if (op2 == 0x00 || op2 == 0x01 || op2 == 0x02 || op2 == 0x03) {
4188 u32 lo_val = 0;
4189 u32 hi_val = 0;
4190
4191 // UHADD16
4058 if (op2 == 0x00) { 4192 if (op2 == 0x00) {
4059 lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF); 4193 lo_val = (rn_val & 0xFFFF) + (rm_val & 0xFFFF);
4060 hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); 4194 hi_val = ((rn_val >> 16) & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
4061 } 4195 }
4062 // UQASX 4196 // UHASX
4063 else if (op2 == 0x01) { 4197 else if (op2 == 0x01) {
4064 lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); 4198 lo_val = (rn_val & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
4065 hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); 4199 hi_val = ((rn_val >> 16) & 0xFFFF) + (rm_val & 0xFFFF);
4066 } 4200 }
4067 // UQSAX 4201 // UHSAX
4068 else if (op2 == 0x02) { 4202 else if (op2 == 0x02) {
4069 lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF); 4203 lo_val = (rn_val & 0xFFFF) + ((rm_val >> 16) & 0xFFFF);
4070 hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF); 4204 hi_val = ((rn_val >> 16) & 0xFFFF) - (rm_val & 0xFFFF);
4071 } 4205 }
4072 // UQSUB16 4206 // UHSUB16
4073 else if (op2 == 0x03) { 4207 else if (op2 == 0x03) {
4074 lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF); 4208 lo_val = (rn_val & 0xFFFF) - (rm_val & 0xFFFF);
4075 hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF); 4209 hi_val = ((rn_val >> 16) & 0xFFFF) - ((rm_val >> 16) & 0xFFFF);
4076 } 4210 }
4077 // UQADD8 4211
4078 else if (op2 == 0x04) { 4212 lo_val >>= 1;
4079 lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) | 4213 hi_val >>= 1;
4080 ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8; 4214
4081 hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) | 4215 RD = (lo_val & 0xFFFF) | ((hi_val & 0xFFFF) << 16);
4082 ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8; 4216 } else if (op2 == 0x04 || op2 == 0x07) {
4217 u32 sum1;
4218 u32 sum2;
4219 u32 sum3;
4220 u32 sum4;
4221
4222 // UHADD8
4223 if (op2 == 0x04) {
4224 sum1 = (rn_val & 0xFF) + (rm_val & 0xFF);
4225 sum2 = ((rn_val >> 8) & 0xFF) + ((rm_val >> 8) & 0xFF);
4226 sum3 = ((rn_val >> 16) & 0xFF) + ((rm_val >> 16) & 0xFF);
4227 sum4 = ((rn_val >> 24) & 0xFF) + ((rm_val >> 24) & 0xFF);
4083 } 4228 }
4084 // UQSUB8 4229 // UHSUB8
4085 else { 4230 else {
4086 lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) | 4231 sum1 = (rn_val & 0xFF) - (rm_val & 0xFF);
4087 ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8; 4232 sum2 = ((rn_val >> 8) & 0xFF) - ((rm_val >> 8) & 0xFF);
4088 hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) | 4233 sum3 = ((rn_val >> 16) & 0xFF) - ((rm_val >> 16) & 0xFF);
4089 ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8; 4234 sum4 = ((rn_val >> 24) & 0xFF) - ((rm_val >> 24) & 0xFF);
4090 } 4235 }
4091 4236
4092 RD = ((lo_val & 0xFFFF) | hi_val << 16); 4237 sum1 >>= 1;
4238 sum2 >>= 1;
4239 sum3 >>= 1;
4240 sum4 >>= 1;
4241
4242 RD = (sum1 & 0xFF) | ((sum2 & 0xFF) << 8) | ((sum3 & 0xFF) << 16) |
4243 ((sum4 & 0xFF) << 24);
4093 } 4244 }
4245 }
4246
4247 cpu->Reg[15] += cpu->GetInstructionSize();
4248 INC_PC(sizeof(generic_arm_inst));
4249 FETCH_INST;
4250 GOTO_NEXT_INST;
4251}
4094 4252
4095 cpu->Reg[15] += cpu->GetInstructionSize(); 4253UMAAL_INST : {
4096 INC_PC(sizeof(generic_arm_inst)); 4254 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4097 FETCH_INST; 4255 umaal_inst* const inst_cream = (umaal_inst*)inst_base->component;
4098 GOTO_NEXT_INST; 4256 const u64 rm = RM;
4257 const u64 rn = RN;
4258 const u64 rd_lo = RDLO;
4259 const u64 rd_hi = RDHI;
4260 const u64 result = (rm * rn) + rd_lo + rd_hi;
4261
4262 RDLO = (result & 0xFFFFFFFF);
4263 RDHI = ((result >> 32) & 0xFFFFFFFF);
4264 }
4265 cpu->Reg[15] += cpu->GetInstructionSize();
4266 INC_PC(sizeof(umaal_inst));
4267 FETCH_INST;
4268 GOTO_NEXT_INST;
4269}
4270UMLAL_INST : {
4271 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4272 umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
4273 unsigned long long int rm = RM;
4274 unsigned long long int rs = RS;
4275 unsigned long long int rst = rm * rs;
4276 unsigned long long int add = ((unsigned long long)RDHI) << 32;
4277 add += RDLO;
4278 rst += add;
4279 RDLO = BITS(rst, 0, 31);
4280 RDHI = BITS(rst, 32, 63);
4281
4282 if (inst_cream->S) {
4283 cpu->NFlag = BIT(RDHI, 31);
4284 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
4285 }
4286 }
4287 cpu->Reg[15] += cpu->GetInstructionSize();
4288 INC_PC(sizeof(umlal_inst));
4289 FETCH_INST;
4290 GOTO_NEXT_INST;
4291}
4292UMULL_INST : {
4293 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4294 umull_inst* inst_cream = (umull_inst*)inst_base->component;
4295 unsigned long long int rm = RM;
4296 unsigned long long int rs = RS;
4297 unsigned long long int rst = rm * rs;
4298 RDHI = BITS(rst, 32, 63);
4299 RDLO = BITS(rst, 0, 31);
4300
4301 if (inst_cream->S) {
4302 cpu->NFlag = BIT(RDHI, 31);
4303 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
4304 }
4099 } 4305 }
4306 cpu->Reg[15] += cpu->GetInstructionSize();
4307 INC_PC(sizeof(umull_inst));
4308 FETCH_INST;
4309 GOTO_NEXT_INST;
4310}
4311B_2_THUMB : {
4312 b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component;
4313 cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm;
4314 INC_PC(sizeof(b_2_thumb));
4315 goto DISPATCH;
4316}
4317B_COND_THUMB : {
4318 b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component;
4100 4319
4101 USAD8_INST: 4320 if (CondPassed(cpu, inst_cream->cond))
4102 USADA8_INST: 4321 cpu->Reg[15] = cpu->Reg[15] + 4 + inst_cream->imm;
4103 { 4322 else
4104 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4323 cpu->Reg[15] += 2;
4105 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
4106 4324
4107 const u8 ra_idx = inst_cream->Ra; 4325 INC_PC(sizeof(b_cond_thumb));
4108 const u32 rm_val = RM; 4326 goto DISPATCH;
4109 const u32 rn_val = RN; 4327}
4328BL_1_THUMB : {
4329 bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component;
4330 cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm;
4331 cpu->Reg[15] += cpu->GetInstructionSize();
4332 INC_PC(sizeof(bl_1_thumb));
4333 FETCH_INST;
4334 GOTO_NEXT_INST;
4335}
4336BL_2_THUMB : {
4337 bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component;
4338 int tmp = ((cpu->Reg[15] + 2) | 1);
4339 cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm);
4340 cpu->Reg[14] = tmp;
4341 INC_PC(sizeof(bl_2_thumb));
4342 goto DISPATCH;
4343}
4344BLX_1_THUMB : {
4345 // BLX 1 for armv5t and above
4346 u32 tmp = cpu->Reg[15];
4347 blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component;
4348 cpu->Reg[15] = (cpu->Reg[14] + inst_cream->imm) & 0xFFFFFFFC;
4349 cpu->Reg[14] = ((tmp + 2) | 1);
4350 cpu->TFlag = 0;
4351 INC_PC(sizeof(blx_1_thumb));
4352 goto DISPATCH;
4353}
4110 4354
4111 const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF); 4355UQADD8_INST:
4112 const u8 diff2 = ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF); 4356UQADD16_INST:
4113 const u8 diff3 = ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF); 4357UQADDSUBX_INST:
4114 const u8 diff4 = ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF); 4358UQSUB8_INST:
4359UQSUB16_INST:
4360UQSUBADDX_INST : {
4361 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4362 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
4363
4364 const u8 op2 = inst_cream->op2;
4365 const u32 rm_val = RM;
4366 const u32 rn_val = RN;
4367
4368 u16 lo_val = 0;
4369 u16 hi_val = 0;
4370
4371 // UQADD16
4372 if (op2 == 0x00) {
4373 lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, rm_val & 0xFFFF);
4374 hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
4375 }
4376 // UQASX
4377 else if (op2 == 0x01) {
4378 lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
4379 hi_val = ARMul_UnsignedSaturatedAdd16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
4380 }
4381 // UQSAX
4382 else if (op2 == 0x02) {
4383 lo_val = ARMul_UnsignedSaturatedAdd16(rn_val & 0xFFFF, (rm_val >> 16) & 0xFFFF);
4384 hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, rm_val & 0xFFFF);
4385 }
4386 // UQSUB16
4387 else if (op2 == 0x03) {
4388 lo_val = ARMul_UnsignedSaturatedSub16(rn_val & 0xFFFF, rm_val & 0xFFFF);
4389 hi_val = ARMul_UnsignedSaturatedSub16((rn_val >> 16) & 0xFFFF, (rm_val >> 16) & 0xFFFF);
4390 }
4391 // UQADD8
4392 else if (op2 == 0x04) {
4393 lo_val = ARMul_UnsignedSaturatedAdd8(rn_val, rm_val) |
4394 ARMul_UnsignedSaturatedAdd8(rn_val >> 8, rm_val >> 8) << 8;
4395 hi_val = ARMul_UnsignedSaturatedAdd8(rn_val >> 16, rm_val >> 16) |
4396 ARMul_UnsignedSaturatedAdd8(rn_val >> 24, rm_val >> 24) << 8;
4397 }
4398 // UQSUB8
4399 else {
4400 lo_val = ARMul_UnsignedSaturatedSub8(rn_val, rm_val) |
4401 ARMul_UnsignedSaturatedSub8(rn_val >> 8, rm_val >> 8) << 8;
4402 hi_val = ARMul_UnsignedSaturatedSub8(rn_val >> 16, rm_val >> 16) |
4403 ARMul_UnsignedSaturatedSub8(rn_val >> 24, rm_val >> 24) << 8;
4404 }
4405
4406 RD = ((lo_val & 0xFFFF) | hi_val << 16);
4407 }
4115 4408
4116 u32 finalDif = (diff1 + diff2 + diff3 + diff4); 4409 cpu->Reg[15] += cpu->GetInstructionSize();
4410 INC_PC(sizeof(generic_arm_inst));
4411 FETCH_INST;
4412 GOTO_NEXT_INST;
4413}
4117 4414
4118 // Op is USADA8 if true. 4415USAD8_INST:
4119 if (ra_idx != 15) 4416USADA8_INST : {
4120 finalDif += cpu->Reg[ra_idx]; 4417 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4418 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
4121 4419
4122 RD = finalDif; 4420 const u8 ra_idx = inst_cream->Ra;
4123 } 4421 const u32 rm_val = RM;
4422 const u32 rn_val = RN;
4423
4424 const u8 diff1 = ARMul_UnsignedAbsoluteDifference(rn_val & 0xFF, rm_val & 0xFF);
4425 const u8 diff2 =
4426 ARMul_UnsignedAbsoluteDifference((rn_val >> 8) & 0xFF, (rm_val >> 8) & 0xFF);
4427 const u8 diff3 =
4428 ARMul_UnsignedAbsoluteDifference((rn_val >> 16) & 0xFF, (rm_val >> 16) & 0xFF);
4429 const u8 diff4 =
4430 ARMul_UnsignedAbsoluteDifference((rn_val >> 24) & 0xFF, (rm_val >> 24) & 0xFF);
4124 4431
4125 cpu->Reg[15] += cpu->GetInstructionSize(); 4432 u32 finalDif = (diff1 + diff2 + diff3 + diff4);
4126 INC_PC(sizeof(generic_arm_inst)); 4433
4127 FETCH_INST; 4434 // Op is USADA8 if true.
4128 GOTO_NEXT_INST; 4435 if (ra_idx != 15)
4436 finalDif += cpu->Reg[ra_idx];
4437
4438 RD = finalDif;
4129 } 4439 }
4130 4440
4131 USAT_INST: 4441 cpu->Reg[15] += cpu->GetInstructionSize();
4132 { 4442 INC_PC(sizeof(generic_arm_inst));
4133 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4443 FETCH_INST;
4134 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; 4444 GOTO_NEXT_INST;
4445}
4135 4446
4136 u8 shift_type = inst_cream->shift_type; 4447USAT_INST : {
4137 u8 shift_amount = inst_cream->imm5; 4448 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4138 u32 rn_val = RN; 4449 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
4139 4450
4140 // 32-bit ASR is encoded as an amount of 0. 4451 u8 shift_type = inst_cream->shift_type;
4141 if (shift_type == 1 && shift_amount == 0) 4452 u8 shift_amount = inst_cream->imm5;
4142 shift_amount = 31; 4453 u32 rn_val = RN;
4143 4454
4144 if (shift_type == 0) 4455 // 32-bit ASR is encoded as an amount of 0.
4145 rn_val <<= shift_amount; 4456 if (shift_type == 1 && shift_amount == 0)
4146 else if (shift_type == 1) 4457 shift_amount = 31;
4147 rn_val = ((s32)rn_val >> shift_amount);
4148 4458
4149 bool saturated = false; 4459 if (shift_type == 0)
4150 rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated); 4460 rn_val <<= shift_amount;
4461 else if (shift_type == 1)
4462 rn_val = ((s32)rn_val >> shift_amount);
4151 4463
4152 if (saturated) 4464 bool saturated = false;
4153 cpu->Cpsr |= (1 << 27); 4465 rn_val = ARMul_UnsignedSatQ(rn_val, inst_cream->sat_imm, &saturated);
4154 4466
4155 RD = rn_val; 4467 if (saturated)
4156 } 4468 cpu->Cpsr |= (1 << 27);
4157 4469
4158 cpu->Reg[15] += cpu->GetInstructionSize(); 4470 RD = rn_val;
4159 INC_PC(sizeof(ssat_inst));
4160 FETCH_INST;
4161 GOTO_NEXT_INST;
4162 } 4471 }
4163 4472
4164 USAT16_INST: 4473 cpu->Reg[15] += cpu->GetInstructionSize();
4165 { 4474 INC_PC(sizeof(ssat_inst));
4166 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4475 FETCH_INST;
4167 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; 4476 GOTO_NEXT_INST;
4168 const u8 saturate_to = inst_cream->sat_imm; 4477}
4169 4478
4170 bool sat1 = false; 4479USAT16_INST : {
4171 bool sat2 = false; 4480 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4481 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
4482 const u8 saturate_to = inst_cream->sat_imm;
4172 4483
4173 RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) | 4484 bool sat1 = false;
4174 ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16; 4485 bool sat2 = false;
4175 4486
4176 if (sat1 || sat2) 4487 RD = (ARMul_UnsignedSatQ((s16)RN, saturate_to, &sat1) & 0xFFFF) |
4177 cpu->Cpsr |= (1 << 27); 4488 ARMul_UnsignedSatQ((s32)RN >> 16, saturate_to, &sat2) << 16;
4178 }
4179 4489
4180 cpu->Reg[15] += cpu->GetInstructionSize(); 4490 if (sat1 || sat2)
4181 INC_PC(sizeof(ssat_inst)); 4491 cpu->Cpsr |= (1 << 27);
4182 FETCH_INST;
4183 GOTO_NEXT_INST;
4184 } 4492 }
4185 4493
4186 UXTAB16_INST: 4494 cpu->Reg[15] += cpu->GetInstructionSize();
4187 UXTB16_INST: 4495 INC_PC(sizeof(ssat_inst));
4188 { 4496 FETCH_INST;
4189 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4497 GOTO_NEXT_INST;
4190 uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; 4498}
4191 4499
4192 const u8 rn_idx = inst_cream->Rn; 4500UXTAB16_INST:
4193 const u32 rm_val = RM; 4501UXTB16_INST : {
4194 const u32 rotation = inst_cream->rotate * 8; 4502 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4195 const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation)); 4503 uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component;
4196 4504
4197 // UXTB16, otherwise UXTAB16 4505 const u8 rn_idx = inst_cream->Rn;
4198 if (rn_idx == 15) { 4506 const u32 rm_val = RM;
4199 RD = rotated_rm & 0x00FF00FF; 4507 const u32 rotation = inst_cream->rotate * 8;
4200 } else { 4508 const u32 rotated_rm = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
4201 const u32 rn_val = RN;
4202 const u8 lo_rotated = (rotated_rm & 0xFF);
4203 const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated;
4204 const u8 hi_rotated = (rotated_rm >> 16) & 0xFF;
4205 const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated;
4206 4509
4207 RD = ((hi_result << 16) | (lo_result & 0xFFFF)); 4510 // UXTB16, otherwise UXTAB16
4208 } 4511 if (rn_idx == 15) {
4209 } 4512 RD = rotated_rm & 0x00FF00FF;
4513 } else {
4514 const u32 rn_val = RN;
4515 const u8 lo_rotated = (rotated_rm & 0xFF);
4516 const u16 lo_result = (rn_val & 0xFFFF) + (u16)lo_rotated;
4517 const u8 hi_rotated = (rotated_rm >> 16) & 0xFF;
4518 const u16 hi_result = (rn_val >> 16) + (u16)hi_rotated;
4210 4519
4211 cpu->Reg[15] += cpu->GetInstructionSize(); 4520 RD = ((hi_result << 16) | (lo_result & 0xFFFF));
4212 INC_PC(sizeof(uxtab_inst)); 4521 }
4213 FETCH_INST;
4214 GOTO_NEXT_INST;
4215 } 4522 }
4216 4523
4217 WFE_INST: 4524 cpu->Reg[15] += cpu->GetInstructionSize();
4218 { 4525 INC_PC(sizeof(uxtab_inst));
4219 // Stubbed, as WFE is a hint instruction. 4526 FETCH_INST;
4220 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4527 GOTO_NEXT_INST;
4221 LOG_TRACE(Core_ARM11, "WFE executed."); 4528}
4222 }
4223 4529
4224 cpu->Reg[15] += cpu->GetInstructionSize(); 4530WFE_INST : {
4225 INC_PC_STUB; 4531 // Stubbed, as WFE is a hint instruction.
4226 FETCH_INST; 4532 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4227 GOTO_NEXT_INST; 4533 LOG_TRACE(Core_ARM11, "WFE executed.");
4228 } 4534 }
4229 4535
4230 WFI_INST: 4536 cpu->Reg[15] += cpu->GetInstructionSize();
4231 { 4537 INC_PC_STUB;
4232 // Stubbed, as WFI is a hint instruction. 4538 FETCH_INST;
4233 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4539 GOTO_NEXT_INST;
4234 LOG_TRACE(Core_ARM11, "WFI executed."); 4540}
4235 }
4236 4541
4237 cpu->Reg[15] += cpu->GetInstructionSize(); 4542WFI_INST : {
4238 INC_PC_STUB; 4543 // Stubbed, as WFI is a hint instruction.
4239 FETCH_INST; 4544 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4240 GOTO_NEXT_INST; 4545 LOG_TRACE(Core_ARM11, "WFI executed.");
4241 } 4546 }
4242 4547
4243 YIELD_INST: 4548 cpu->Reg[15] += cpu->GetInstructionSize();
4244 { 4549 INC_PC_STUB;
4245 // Stubbed, as YIELD is a hint instruction. 4550 FETCH_INST;
4246 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4551 GOTO_NEXT_INST;
4247 LOG_TRACE(Core_ARM11, "YIELD executed."); 4552}
4248 }
4249 4553
4250 cpu->Reg[15] += cpu->GetInstructionSize(); 4554YIELD_INST : {
4251 INC_PC_STUB; 4555 // Stubbed, as YIELD is a hint instruction.
4252 FETCH_INST; 4556 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4253 GOTO_NEXT_INST; 4557 LOG_TRACE(Core_ARM11, "YIELD executed.");
4254 } 4558 }
4255 4559
4256 #define VFP_INTERPRETER_IMPL 4560 cpu->Reg[15] += cpu->GetInstructionSize();
4257 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 4561 INC_PC_STUB;
4258 #undef VFP_INTERPRETER_IMPL 4562 FETCH_INST;
4563 GOTO_NEXT_INST;
4564}
4259 4565
4260 END: 4566#define VFP_INTERPRETER_IMPL
4261 { 4567#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
4262 SAVE_NZCVT; 4568#undef VFP_INTERPRETER_IMPL
4263 cpu->NumInstrsToExecute = 0; 4569
4264 return num_instrs; 4570END : {
4265 } 4571 SAVE_NZCVT;
4266 INIT_INST_LENGTH: 4572 cpu->NumInstrsToExecute = 0;
4267 { 4573 return num_instrs;
4268 cpu->NumInstrsToExecute = 0; 4574}
4269 return num_instrs; 4575INIT_INST_LENGTH : {
4270 } 4576 cpu->NumInstrsToExecute = 0;
4577 return num_instrs;
4578}
4271} 4579}
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index 3576370d1..2a3dd0f53 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -21,50 +21,48 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
21 *ainstr = 0xDEADC0DE; // Debugging to catch non updates 21 *ainstr = 0xDEADC0DE; // Debugging to catch non updates
22 22
23 switch ((tinstr & 0xF800) >> 11) { 23 switch ((tinstr & 0xF800) >> 11) {
24 case 0: // LSL 24 case 0: // LSL
25 case 1: // LSR 25 case 1: // LSR
26 case 2: // ASR 26 case 2: // ASR
27 *ainstr = 0xE1B00000 // base opcode 27 *ainstr = 0xE1B00000 // base opcode
28 | ((tinstr & 0x1800) >> (11 - 5)) // shift type 28 | ((tinstr & 0x1800) >> (11 - 5)) // shift type
29 |((tinstr & 0x07C0) << (7 - 6)) // imm5 29 | ((tinstr & 0x07C0) << (7 - 6)) // imm5
30 |((tinstr & 0x0038) >> 3) // Rs 30 | ((tinstr & 0x0038) >> 3) // Rs
31 |((tinstr & 0x0007) << 12); // Rd 31 | ((tinstr & 0x0007) << 12); // Rd
32 break; 32 break;
33 33
34 case 3: // ADD/SUB 34 case 3: // ADD/SUB
35 { 35 {
36 static const u32 subset[4] = { 36 static const u32 subset[4] = {
37 0xE0900000, // ADDS Rd,Rs,Rn 37 0xE0900000, // ADDS Rd,Rs,Rn
38 0xE0500000, // SUBS Rd,Rs,Rn 38 0xE0500000, // SUBS Rd,Rs,Rn
39 0xE2900000, // ADDS Rd,Rs,#imm3 39 0xE2900000, // ADDS Rd,Rs,#imm3
40 0xE2500000 // SUBS Rd,Rs,#imm3 40 0xE2500000 // SUBS Rd,Rs,#imm3
41 }; 41 };
42 // It is quicker indexing into a table, than performing switch or conditionals: 42 // It is quicker indexing into a table, than performing switch or conditionals:
43 *ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode 43 *ainstr = subset[(tinstr & 0x0600) >> 9] // base opcode
44 |((tinstr & 0x01C0) >> 6) // Rn or imm3 44 | ((tinstr & 0x01C0) >> 6) // Rn or imm3
45 |((tinstr & 0x0038) << (16 - 3)) // Rs 45 | ((tinstr & 0x0038) << (16 - 3)) // Rs
46 |((tinstr & 0x0007) << (12 - 0)); // Rd 46 | ((tinstr & 0x0007) << (12 - 0)); // Rd
47 } 47 } break;
48 break;
49 48
50 case 4: // MOV 49 case 4: // MOV
51 case 5: // CMP 50 case 5: // CMP
52 case 6: // ADD 51 case 6: // ADD
53 case 7: // SUB 52 case 7: // SUB
54 { 53 {
55 static const u32 subset[4] = { 54 static const u32 subset[4] = {
56 0xE3B00000, // MOVS Rd,#imm8 55 0xE3B00000, // MOVS Rd,#imm8
57 0xE3500000, // CMP Rd,#imm8 56 0xE3500000, // CMP Rd,#imm8
58 0xE2900000, // ADDS Rd,Rd,#imm8 57 0xE2900000, // ADDS Rd,Rd,#imm8
59 0xE2500000, // SUBS Rd,Rd,#imm8 58 0xE2500000, // SUBS Rd,Rd,#imm8
60 }; 59 };
61 60
62 *ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode 61 *ainstr = subset[(tinstr & 0x1800) >> 11] // base opcode
63 |((tinstr & 0x00FF) >> 0) // imm8 62 | ((tinstr & 0x00FF) >> 0) // imm8
64 |((tinstr & 0x0700) << (16 - 8)) // Rn 63 | ((tinstr & 0x0700) << (16 - 8)) // Rn
65 |((tinstr & 0x0700) << (12 - 8)); // Rd 64 | ((tinstr & 0x0700) << (12 - 8)); // Rd
66 } 65 } break;
67 break;
68 66
69 case 8: // Arithmetic and high register transfers 67 case 8: // Arithmetic and high register transfers
70 68
@@ -73,56 +71,51 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
73 // large subset 71 // large subset
74 72
75 if ((tinstr & (1 << 10)) == 0) { 73 if ((tinstr & (1 << 10)) == 0) {
76 enum otype { 74 enum otype { t_norm, t_shift, t_neg, t_mul };
77 t_norm,
78 t_shift,
79 t_neg,
80 t_mul
81 };
82 75
83 static const struct { 76 static const struct {
84 u32 opcode; 77 u32 opcode;
85 otype type; 78 otype type;
86 } subset[16] = { 79 } subset[16] = {
87 { 0xE0100000, t_norm }, // ANDS Rd,Rd,Rs 80 {0xE0100000, t_norm}, // ANDS Rd,Rd,Rs
88 { 0xE0300000, t_norm }, // EORS Rd,Rd,Rs 81 {0xE0300000, t_norm}, // EORS Rd,Rd,Rs
89 { 0xE1B00010, t_shift }, // MOVS Rd,Rd,LSL Rs 82 {0xE1B00010, t_shift}, // MOVS Rd,Rd,LSL Rs
90 { 0xE1B00030, t_shift }, // MOVS Rd,Rd,LSR Rs 83 {0xE1B00030, t_shift}, // MOVS Rd,Rd,LSR Rs
91 { 0xE1B00050, t_shift }, // MOVS Rd,Rd,ASR Rs 84 {0xE1B00050, t_shift}, // MOVS Rd,Rd,ASR Rs
92 { 0xE0B00000, t_norm }, // ADCS Rd,Rd,Rs 85 {0xE0B00000, t_norm}, // ADCS Rd,Rd,Rs
93 { 0xE0D00000, t_norm }, // SBCS Rd,Rd,Rs 86 {0xE0D00000, t_norm}, // SBCS Rd,Rd,Rs
94 { 0xE1B00070, t_shift }, // MOVS Rd,Rd,ROR Rs 87 {0xE1B00070, t_shift}, // MOVS Rd,Rd,ROR Rs
95 { 0xE1100000, t_norm }, // TST Rd,Rs 88 {0xE1100000, t_norm}, // TST Rd,Rs
96 { 0xE2700000, t_neg }, // RSBS Rd,Rs,#0 89 {0xE2700000, t_neg}, // RSBS Rd,Rs,#0
97 { 0xE1500000, t_norm }, // CMP Rd,Rs 90 {0xE1500000, t_norm}, // CMP Rd,Rs
98 { 0xE1700000, t_norm }, // CMN Rd,Rs 91 {0xE1700000, t_norm}, // CMN Rd,Rs
99 { 0xE1900000, t_norm }, // ORRS Rd,Rd,Rs 92 {0xE1900000, t_norm}, // ORRS Rd,Rd,Rs
100 { 0xE0100090, t_mul }, // MULS Rd,Rd,Rs 93 {0xE0100090, t_mul}, // MULS Rd,Rd,Rs
101 { 0xE1D00000, t_norm }, // BICS Rd,Rd,Rs 94 {0xE1D00000, t_norm}, // BICS Rd,Rd,Rs
102 { 0xE1F00000, t_norm } // MVNS Rd,Rs 95 {0xE1F00000, t_norm} // MVNS Rd,Rs
103 }; 96 };
104 97
105 *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base 98 *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; // base
106 99
107 switch (subset[(tinstr & 0x03C0) >> 6].type) { 100 switch (subset[(tinstr & 0x03C0) >> 6].type) {
108 case t_norm: 101 case t_norm:
109 *ainstr |= ((tinstr & 0x0007) << 16) // Rn 102 *ainstr |= ((tinstr & 0x0007) << 16) // Rn
110 |((tinstr & 0x0007) << 12) // Rd 103 | ((tinstr & 0x0007) << 12) // Rd
111 |((tinstr & 0x0038) >> 3); // Rs 104 | ((tinstr & 0x0038) >> 3); // Rs
112 break; 105 break;
113 case t_shift: 106 case t_shift:
114 *ainstr |= ((tinstr & 0x0007) << 12) // Rd 107 *ainstr |= ((tinstr & 0x0007) << 12) // Rd
115 |((tinstr & 0x0007) >> 0) // Rm 108 | ((tinstr & 0x0007) >> 0) // Rm
116 |((tinstr & 0x0038) << (8 - 3)); // Rs 109 | ((tinstr & 0x0038) << (8 - 3)); // Rs
117 break; 110 break;
118 case t_neg: 111 case t_neg:
119 *ainstr |= ((tinstr & 0x0007) << 12) // Rd 112 *ainstr |= ((tinstr & 0x0007) << 12) // Rd
120 |((tinstr & 0x0038) << (16 - 3)); // Rn 113 | ((tinstr & 0x0038) << (16 - 3)); // Rn
121 break; 114 break;
122 case t_mul: 115 case t_mul:
123 *ainstr |= ((tinstr & 0x0007) << 16) // Rd 116 *ainstr |= ((tinstr & 0x0007) << 16) // Rd
124 |((tinstr & 0x0007) << 8) // Rs 117 | ((tinstr & 0x0007) << 8) // Rs
125 |((tinstr & 0x0038) >> 3); // Rm 118 | ((tinstr & 0x0038) >> 3); // Rm
126 break; 119 break;
127 } 120 }
128 } else { 121 } else {
@@ -133,109 +126,106 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
133 Rd += 8; 126 Rd += 8;
134 127
135 switch ((tinstr & 0x03C0) >> 6) { 128 switch ((tinstr & 0x03C0) >> 6) {
136 case 0x0: // ADD Rd,Rd,Rs 129 case 0x0: // ADD Rd,Rd,Rs
137 case 0x1: // ADD Rd,Rd,Hs 130 case 0x1: // ADD Rd,Rd,Hs
138 case 0x2: // ADD Hd,Hd,Rs 131 case 0x2: // ADD Hd,Hd,Rs
139 case 0x3: // ADD Hd,Hd,Hs 132 case 0x3: // ADD Hd,Hd,Hs
140 *ainstr = 0xE0800000 // base 133 *ainstr = 0xE0800000 // base
141 | (Rd << 16) // Rn 134 | (Rd << 16) // Rn
142 |(Rd << 12) // Rd 135 | (Rd << 12) // Rd
143 |(Rs << 0); // Rm 136 | (Rs << 0); // Rm
144 break; 137 break;
145 case 0x4: // CMP Rd,Rs 138 case 0x4: // CMP Rd,Rs
146 case 0x5: // CMP Rd,Hs 139 case 0x5: // CMP Rd,Hs
147 case 0x6: // CMP Hd,Rs 140 case 0x6: // CMP Hd,Rs
148 case 0x7: // CMP Hd,Hs 141 case 0x7: // CMP Hd,Hs
149 *ainstr = 0xE1500000 // base 142 *ainstr = 0xE1500000 // base
150 | (Rd << 16) // Rn 143 | (Rd << 16) // Rn
151 |(Rs << 0); // Rm 144 | (Rs << 0); // Rm
152 break; 145 break;
153 case 0x8: // MOV Rd,Rs 146 case 0x8: // MOV Rd,Rs
154 case 0x9: // MOV Rd,Hs 147 case 0x9: // MOV Rd,Hs
155 case 0xA: // MOV Hd,Rs 148 case 0xA: // MOV Hd,Rs
156 case 0xB: // MOV Hd,Hs 149 case 0xB: // MOV Hd,Hs
157 *ainstr = 0xE1A00000 // base 150 *ainstr = 0xE1A00000 // base
158 |(Rd << 12) // Rd 151 | (Rd << 12) // Rd
159 |(Rs << 0); // Rm 152 | (Rs << 0); // Rm
160 break; 153 break;
161 case 0xC: // BX Rs 154 case 0xC: // BX Rs
162 case 0xD: // BX Hs 155 case 0xD: // BX Hs
163 *ainstr = 0xE12FFF10 // base 156 *ainstr = 0xE12FFF10 // base
164 | ((tinstr & 0x0078) >> 3); // Rd 157 | ((tinstr & 0x0078) >> 3); // Rd
165 break; 158 break;
166 case 0xE: // BLX 159 case 0xE: // BLX
167 case 0xF: // BLX 160 case 0xF: // BLX
168 *ainstr = 0xE1200030 // base 161 *ainstr = 0xE1200030 // base
169 | (Rs << 0); // Rm 162 | (Rs << 0); // Rm
170 break; 163 break;
171 } 164 }
172 } 165 }
173 break; 166 break;
174 167
175 case 9: // LDR Rd,[PC,#imm8] 168 case 9: // LDR Rd,[PC,#imm8]
176 *ainstr = 0xE59F0000 // base 169 *ainstr = 0xE59F0000 // base
177 | ((tinstr & 0x0700) << (12 - 8)) // Rd 170 | ((tinstr & 0x0700) << (12 - 8)) // Rd
178 |((tinstr & 0x00FF) << (2 - 0)); // off8 171 | ((tinstr & 0x00FF) << (2 - 0)); // off8
179 break; 172 break;
180 173
181 case 10: 174 case 10:
182 case 11: 175 case 11: {
183 { 176 static const u32 subset[8] = {
184 static const u32 subset[8] = { 177 0xE7800000, // STR Rd,[Rb,Ro]
185 0xE7800000, // STR Rd,[Rb,Ro] 178 0xE18000B0, // STRH Rd,[Rb,Ro]
186 0xE18000B0, // STRH Rd,[Rb,Ro] 179 0xE7C00000, // STRB Rd,[Rb,Ro]
187 0xE7C00000, // STRB Rd,[Rb,Ro] 180 0xE19000D0, // LDRSB Rd,[Rb,Ro]
188 0xE19000D0, // LDRSB Rd,[Rb,Ro] 181 0xE7900000, // LDR Rd,[Rb,Ro]
189 0xE7900000, // LDR Rd,[Rb,Ro] 182 0xE19000B0, // LDRH Rd,[Rb,Ro]
190 0xE19000B0, // LDRH Rd,[Rb,Ro] 183 0xE7D00000, // LDRB Rd,[Rb,Ro]
191 0xE7D00000, // LDRB Rd,[Rb,Ro] 184 0xE19000F0 // LDRSH Rd,[Rb,Ro]
192 0xE19000F0 // LDRSH Rd,[Rb,Ro] 185 };
193 }; 186
194 187 *ainstr = subset[(tinstr & 0xE00) >> 9] // base
195 *ainstr = subset[(tinstr & 0xE00) >> 9] // base 188 | ((tinstr & 0x0007) << (12 - 0)) // Rd
196 |((tinstr & 0x0007) << (12 - 0)) // Rd 189 | ((tinstr & 0x0038) << (16 - 3)) // Rb
197 |((tinstr & 0x0038) << (16 - 3)) // Rb 190 | ((tinstr & 0x01C0) >> 6); // Ro
198 |((tinstr & 0x01C0) >> 6); // Ro 191 } break;
199 }
200 break;
201 192
202 case 12: // STR Rd,[Rb,#imm5] 193 case 12: // STR Rd,[Rb,#imm5]
203 case 13: // LDR Rd,[Rb,#imm5] 194 case 13: // LDR Rd,[Rb,#imm5]
204 case 14: // STRB Rd,[Rb,#imm5] 195 case 14: // STRB Rd,[Rb,#imm5]
205 case 15: // LDRB Rd,[Rb,#imm5] 196 case 15: // LDRB Rd,[Rb,#imm5]
206 { 197 {
207 static const u32 subset[4] = { 198 static const u32 subset[4] = {
208 0xE5800000, // STR Rd,[Rb,#imm5] 199 0xE5800000, // STR Rd,[Rb,#imm5]
209 0xE5900000, // LDR Rd,[Rb,#imm5] 200 0xE5900000, // LDR Rd,[Rb,#imm5]
210 0xE5C00000, // STRB Rd,[Rb,#imm5] 201 0xE5C00000, // STRB Rd,[Rb,#imm5]
211 0xE5D00000 // LDRB Rd,[Rb,#imm5] 202 0xE5D00000 // LDRB Rd,[Rb,#imm5]
212 }; 203 };
213 // The offset range defends on whether we are transferring a byte or word value: 204 // The offset range defends on whether we are transferring a byte or word value:
214 *ainstr = subset[(tinstr & 0x1800) >> 11] // base 205 *ainstr = subset[(tinstr & 0x1800) >> 11] // base
215 |((tinstr & 0x0007) << (12 - 0)) // Rd 206 | ((tinstr & 0x0007) << (12 - 0)) // Rd
216 |((tinstr & 0x0038) << (16 - 3)) // Rb 207 | ((tinstr & 0x0038) << (16 - 3)) // Rb
217 |((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5 208 | ((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); // off5
218 } 209 } break;
210
211 case 16: // STRH Rd,[Rb,#imm5]
212 case 17: // LDRH Rd,[Rb,#imm5]
213 *ainstr = ((tinstr & (1 << 11)) // base
214 ? 0xE1D000B0 // LDRH
215 : 0xE1C000B0) // STRH
216 | ((tinstr & 0x0007) << (12 - 0)) // Rd
217 | ((tinstr & 0x0038) << (16 - 3)) // Rb
218 | ((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble
219 | ((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble
219 break; 220 break;
220 221
221 case 16: // STRH Rd,[Rb,#imm5] 222 case 18: // STR Rd,[SP,#imm8]
222 case 17: // LDRH Rd,[Rb,#imm5] 223 case 19: // LDR Rd,[SP,#imm8]
223 *ainstr = ((tinstr & (1 << 11)) // base 224 *ainstr = ((tinstr & (1 << 11)) // base
224 ? 0xE1D000B0 // LDRH 225 ? 0xE59D0000 // LDR
225 : 0xE1C000B0) // STRH 226 : 0xE58D0000) // STR
226 |((tinstr & 0x0007) << (12 - 0)) // Rd 227 | ((tinstr & 0x0700) << (12 - 8)) // Rd
227 |((tinstr & 0x0038) << (16 - 3)) // Rb 228 | ((tinstr & 0x00FF) << 2); // off8
228 |((tinstr & 0x01C0) >> (6 - 1)) // off5, low nibble
229 |((tinstr & 0x0600) >> (9 - 8)); // off5, high nibble
230 break;
231
232 case 18: // STR Rd,[SP,#imm8]
233 case 19: // LDR Rd,[SP,#imm8]
234 *ainstr = ((tinstr & (1 << 11)) // base
235 ? 0xE59D0000 // LDR
236 : 0xE58D0000) // STR
237 |((tinstr & 0x0700) << (12 - 8)) // Rd
238 |((tinstr & 0x00FF) << 2); // off8
239 break; 229 break;
240 230
241 case 20: // ADD Rd,PC,#imm8 231 case 20: // ADD Rd,PC,#imm8
@@ -246,14 +236,15 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
246 // NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the 236 // NOTE: The PC value used here should by word aligned. We encode shift-left-by-2 in the
247 // rotate immediate field, so no shift of off8 is needed. 237 // rotate immediate field, so no shift of off8 is needed.
248 238
249 *ainstr = 0xE28F0F00 // base 239 *ainstr = 0xE28F0F00 // base
250 | ((tinstr & 0x0700) << (12 - 8)) // Rd 240 | ((tinstr & 0x0700) << (12 - 8)) // Rd
251 |(tinstr & 0x00FF); // off8 241 | (tinstr & 0x00FF); // off8
252 } else { 242 } else {
253 // We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is needed. 243 // We encode shift-left-by-2 in the rotate immediate field, so no shift of off8 is
254 *ainstr = 0xE28D0F00 // base 244 // needed.
255 | ((tinstr & 0x0700) << (12 - 8)) // Rd 245 *ainstr = 0xE28D0F00 // base
256 |(tinstr & 0x00FF); // off8 246 | ((tinstr & 0x0700) << (12 - 8)) // Rd
247 | (tinstr & 0x00FF); // off8
257 } 248 }
258 break; 249 break;
259 250
@@ -261,15 +252,15 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
261 case 23: 252 case 23:
262 if ((tinstr & 0x0F00) == 0x0000) { 253 if ((tinstr & 0x0F00) == 0x0000) {
263 // NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30): 254 // NOTE: The instruction contains a shift left of 2 equivalent (implemented as ROR #30):
264 *ainstr = ((tinstr & (1 << 7)) // base 255 *ainstr = ((tinstr & (1 << 7)) // base
265 ? 0xE24DDF00 // SUB 256 ? 0xE24DDF00 // SUB
266 : 0xE28DDF00) // ADD 257 : 0xE28DDF00) // ADD
267 |(tinstr & 0x007F); // off7 258 | (tinstr & 0x007F); // off7
268 } else if ((tinstr & 0x0F00) == 0x0e00) { 259 } else if ((tinstr & 0x0F00) == 0x0e00) {
269 // BKPT 260 // BKPT
270 *ainstr = 0xEF000000 // base 261 *ainstr = 0xEF000000 // base
271 | BITS(tinstr, 0, 3) // imm4 field; 262 | BITS(tinstr, 0, 3) // imm4 field;
272 | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12 263 | (BITS(tinstr, 4, 7) << 8); // beginning 4 bits of imm12
273 } else if ((tinstr & 0x0F00) == 0x0200) { 264 } else if ((tinstr & 0x0F00) == 0x0200) {
274 static const u32 subset[4] = { 265 static const u32 subset[4] = {
275 0xE6BF0070, // SXTH 266 0xE6BF0070, // SXTH
@@ -278,21 +269,21 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
278 0xE6EF0070, // UXTB 269 0xE6EF0070, // UXTB
279 }; 270 };
280 271
281 *ainstr = subset[BITS(tinstr, 6, 7)] // base 272 *ainstr = subset[BITS(tinstr, 6, 7)] // base
282 | (BITS(tinstr, 0, 2) << 12) // Rd 273 | (BITS(tinstr, 0, 2) << 12) // Rd
283 | BITS(tinstr, 3, 5); // Rm 274 | BITS(tinstr, 3, 5); // Rm
284 } else if ((tinstr & 0x0F00) == 0x600) { 275 } else if ((tinstr & 0x0F00) == 0x600) {
285 if (BIT(tinstr, 5) == 0) { 276 if (BIT(tinstr, 5) == 0) {
286 // SETEND 277 // SETEND
287 *ainstr = 0xF1010000 // base 278 *ainstr = 0xF1010000 // base
288 | (BIT(tinstr, 3) << 9); // endian specifier 279 | (BIT(tinstr, 3) << 9); // endian specifier
289 } else { 280 } else {
290 // CPS 281 // CPS
291 *ainstr = 0xF1080000 // base 282 *ainstr = 0xF1080000 // base
292 | (BIT(tinstr, 0) << 6) // fiq bit 283 | (BIT(tinstr, 0) << 6) // fiq bit
293 | (BIT(tinstr, 1) << 7) // irq bit 284 | (BIT(tinstr, 1) << 7) // irq bit
294 | (BIT(tinstr, 2) << 8) // abort bit 285 | (BIT(tinstr, 2) << 8) // abort bit
295 | (BIT(tinstr, 4) << 18); // enable bit 286 | (BIT(tinstr, 4) << 18); // enable bit
296 } 287 }
297 } else if ((tinstr & 0x0F00) == 0x0a00) { 288 } else if ((tinstr & 0x0F00) == 0x0a00) {
298 static const u32 subset[4] = { 289 static const u32 subset[4] = {
@@ -307,9 +298,9 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
307 if (subset_index == 2) { 298 if (subset_index == 2) {
308 valid = ThumbDecodeStatus::UNDEFINED; 299 valid = ThumbDecodeStatus::UNDEFINED;
309 } else { 300 } else {
310 *ainstr = subset[subset_index] // base 301 *ainstr = subset[subset_index] // base
311 | (BITS(tinstr, 0, 2) << 12) // Rd 302 | (BITS(tinstr, 0, 2) << 12) // Rd
312 | BITS(tinstr, 3, 5); // Rm 303 | BITS(tinstr, 3, 5); // Rm
313 } 304 }
314 } else { 305 } else {
315 static const u32 subset[4] = { 306 static const u32 subset[4] = {
@@ -319,14 +310,13 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
319 0xE8BD8000 // LDMIA sp!,{rlist,pc} 310 0xE8BD8000 // LDMIA sp!,{rlist,pc}
320 }; 311 };
321 *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] // base 312 *ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] // base
322 |(tinstr & 0x00FF); // mask8 313 | (tinstr & 0x00FF); // mask8
323 } 314 }
324 break; 315 break;
325 316
326 case 24: // STMIA 317 case 24: // STMIA
327 case 25: // LDMIA 318 case 25: // LDMIA
328 if (tinstr & (1 << 11)) 319 if (tinstr & (1 << 11)) {
329 {
330 unsigned int base = 0xE8900000; 320 unsigned int base = 0xE8900000;
331 unsigned int rn = BITS(tinstr, 8, 10); 321 unsigned int rn = BITS(tinstr, 8, 10);
332 322
@@ -334,15 +324,13 @@ ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u3
334 if ((tinstr & (1 << rn)) == 0) 324 if ((tinstr & (1 << rn)) == 0)
335 base |= (1 << 21); 325 base |= (1 << 21);
336 326
337 *ainstr = base // base (LDMIA) 327 *ainstr = base // base (LDMIA)
338 | (rn << 16) // Rn 328 | (rn << 16) // Rn
339 | (tinstr & 0x00FF); // Register list 329 | (tinstr & 0x00FF); // Register list
340 } 330 } else {
341 else 331 *ainstr = 0xE8A00000 // base (STMIA)
342 { 332 | (BITS(tinstr, 8, 10) << 16) // Rn
343 *ainstr = 0xE8A00000 // base (STMIA) 333 | (tinstr & 0x00FF); // Register list
344 | (BITS(tinstr, 8, 10) << 16) // Rn
345 | (tinstr & 0x00FF); // Register list
346 } 334 }
347 break; 335 break;
348 336
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h
index c1be3c735..231e48aa4 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.h
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.h
@@ -29,9 +29,9 @@
29#include "common/common_types.h" 29#include "common/common_types.h"
30 30
31enum class ThumbDecodeStatus { 31enum class ThumbDecodeStatus {
32 UNDEFINED, // Undefined Thumb instruction 32 UNDEFINED, // Undefined Thumb instruction
33 DECODED, // Instruction decoded to ARM equivalent 33 DECODED, // Instruction decoded to ARM equivalent
34 BRANCH, // Thumb branch (already processed) 34 BRANCH, // Thumb branch (already processed)
35 UNINITIALIZED, 35 UNINITIALIZED,
36}; 36};
37 37
diff --git a/src/core/arm/dyncom/arm_dyncom_trans.cpp b/src/core/arm/dyncom/arm_dyncom_trans.cpp
index 00b42c246..780638638 100644
--- a/src/core/arm/dyncom/arm_dyncom_trans.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_trans.cpp
@@ -1,8 +1,6 @@
1#include <cstdlib> 1#include <cstdlib>
2
3#include "common/assert.h" 2#include "common/assert.h"
4#include "common/common_types.h" 3#include "common/common_types.h"
5
6#include "core/arm/dyncom/arm_dyncom_interpreter.h" 4#include "core/arm/dyncom/arm_dyncom_interpreter.h"
7#include "core/arm/dyncom/arm_dyncom_trans.h" 5#include "core/arm/dyncom/arm_dyncom_trans.h"
8#include "core/arm/skyeye_common/armstate.h" 6#include "core/arm/skyeye_common/armstate.h"
@@ -19,24 +17,23 @@ static void* AllocBuffer(size_t size) {
19 return static_cast<void*>(&trans_cache_buf[start]); 17 return static_cast<void*>(&trans_cache_buf[start]);
20} 18}
21 19
22#define glue(x, y) x ## y 20#define glue(x, y) x##y
23#define INTERPRETER_TRANSLATE(s) glue(InterpreterTranslate_, s) 21#define INTERPRETER_TRANSLATE(s) glue(InterpreterTranslate_, s)
24 22
25shtop_fp_t GetShifterOp(unsigned int inst); 23shtop_fp_t GetShifterOp(unsigned int inst);
26get_addr_fp_t GetAddressingOp(unsigned int inst); 24get_addr_fp_t GetAddressingOp(unsigned int inst);
27get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst); 25get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst);
28 26
29static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) 27static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index) {
30{ 28 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst));
31 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(adc_inst)); 29 adc_inst* inst_cream = (adc_inst*)inst_base->component;
32 adc_inst *inst_cream = (adc_inst *)inst_base->component;
33 30
34 inst_base->cond = BITS(inst, 28, 31); 31 inst_base->cond = BITS(inst, 28, 31);
35 inst_base->idx = index; 32 inst_base->idx = index;
36 inst_base->br = TransExtData::NON_BRANCH; 33 inst_base->br = TransExtData::NON_BRANCH;
37 34
38 inst_cream->I = BIT(inst, 25); 35 inst_cream->I = BIT(inst, 25);
39 inst_cream->S = BIT(inst, 20); 36 inst_cream->S = BIT(inst, 20);
40 inst_cream->Rn = BITS(inst, 16, 19); 37 inst_cream->Rn = BITS(inst, 16, 19);
41 inst_cream->Rd = BITS(inst, 12, 15); 38 inst_cream->Rd = BITS(inst, 12, 15);
42 inst_cream->shifter_operand = BITS(inst, 0, 11); 39 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -47,17 +44,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(adc)(unsigned int inst, int index)
47 44
48 return inst_base; 45 return inst_base;
49} 46}
50static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) 47static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index) {
51{ 48 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst));
52 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(add_inst)); 49 add_inst* inst_cream = (add_inst*)inst_base->component;
53 add_inst *inst_cream = (add_inst *)inst_base->component;
54 50
55 inst_base->cond = BITS(inst, 28, 31); 51 inst_base->cond = BITS(inst, 28, 31);
56 inst_base->idx = index; 52 inst_base->idx = index;
57 inst_base->br = TransExtData::NON_BRANCH; 53 inst_base->br = TransExtData::NON_BRANCH;
58 54
59 inst_cream->I = BIT(inst, 25); 55 inst_cream->I = BIT(inst, 25);
60 inst_cream->S = BIT(inst, 20); 56 inst_cream->S = BIT(inst, 20);
61 inst_cream->Rn = BITS(inst, 16, 19); 57 inst_cream->Rn = BITS(inst, 16, 19);
62 inst_cream->Rd = BITS(inst, 12, 15); 58 inst_cream->Rd = BITS(inst, 12, 15);
63 inst_cream->shifter_operand = BITS(inst, 0, 11); 59 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -68,17 +64,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(add)(unsigned int inst, int index)
68 64
69 return inst_base; 65 return inst_base;
70} 66}
71static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) 67static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index) {
72{ 68 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst));
73 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(and_inst)); 69 and_inst* inst_cream = (and_inst*)inst_base->component;
74 and_inst *inst_cream = (and_inst *)inst_base->component;
75 70
76 inst_base->cond = BITS(inst, 28, 31); 71 inst_base->cond = BITS(inst, 28, 31);
77 inst_base->idx = index; 72 inst_base->idx = index;
78 inst_base->br = TransExtData::NON_BRANCH; 73 inst_base->br = TransExtData::NON_BRANCH;
79 74
80 inst_cream->I = BIT(inst, 25); 75 inst_cream->I = BIT(inst, 25);
81 inst_cream->S = BIT(inst, 20); 76 inst_cream->S = BIT(inst, 20);
82 inst_cream->Rn = BITS(inst, 16, 19); 77 inst_cream->Rn = BITS(inst, 16, 19);
83 inst_cream->Rd = BITS(inst, 12, 15); 78 inst_cream->Rd = BITS(inst, 12, 15);
84 inst_cream->shifter_operand = BITS(inst, 0, 11); 79 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -89,37 +84,35 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(and)(unsigned int inst, int index)
89 84
90 return inst_base; 85 return inst_base;
91} 86}
92static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) 87static ARM_INST_PTR INTERPRETER_TRANSLATE(bbl)(unsigned int inst, int index) {
93{ 88#define POSBRANCH ((inst & 0x7fffff) << 2)
94 #define POSBRANCH ((inst & 0x7fffff) << 2) 89#define NEGBRANCH ((0xff000000 | (inst & 0xffffff)) << 2)
95 #define NEGBRANCH ((0xff000000 |(inst & 0xffffff)) << 2)
96 90
97 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst)); 91 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bbl_inst));
98 bbl_inst *inst_cream = (bbl_inst *)inst_base->component; 92 bbl_inst* inst_cream = (bbl_inst*)inst_base->component;
99 93
100 inst_base->cond = BITS(inst, 28, 31); 94 inst_base->cond = BITS(inst, 28, 31);
101 inst_base->idx = index; 95 inst_base->idx = index;
102 inst_base->br = TransExtData::DIRECT_BRANCH; 96 inst_base->br = TransExtData::DIRECT_BRANCH;
103 97
104 if (BIT(inst, 24)) 98 if (BIT(inst, 24))
105 inst_base->br = TransExtData::CALL; 99 inst_base->br = TransExtData::CALL;
106 100
107 inst_cream->L = BIT(inst, 24); 101 inst_cream->L = BIT(inst, 24);
108 inst_cream->signed_immed_24 = BIT(inst, 23) ? NEGBRANCH : POSBRANCH; 102 inst_cream->signed_immed_24 = BIT(inst, 23) ? NEGBRANCH : POSBRANCH;
109 103
110 return inst_base; 104 return inst_base;
111} 105}
112static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) 106static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index) {
113{ 107 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst));
114 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bic_inst)); 108 bic_inst* inst_cream = (bic_inst*)inst_base->component;
115 bic_inst *inst_cream = (bic_inst *)inst_base->component;
116 109
117 inst_base->cond = BITS(inst, 28, 31); 110 inst_base->cond = BITS(inst, 28, 31);
118 inst_base->idx = index; 111 inst_base->idx = index;
119 inst_base->br = TransExtData::NON_BRANCH; 112 inst_base->br = TransExtData::NON_BRANCH;
120 113
121 inst_cream->I = BIT(inst, 25); 114 inst_cream->I = BIT(inst, 25);
122 inst_cream->S = BIT(inst, 20); 115 inst_cream->S = BIT(inst, 20);
123 inst_cream->Rn = BITS(inst, 16, 19); 116 inst_cream->Rn = BITS(inst, 16, 19);
124 inst_cream->Rd = BITS(inst, 12, 15); 117 inst_cream->Rd = BITS(inst, 12, 15);
125 inst_cream->shifter_operand = BITS(inst, 0, 11); 118 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -130,28 +123,26 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index)
130 return inst_base; 123 return inst_base;
131} 124}
132 125
133static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) 126static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) {
134{
135 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst)); 127 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst));
136 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component; 128 bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
137 129
138 inst_base->cond = BITS(inst, 28, 31); 130 inst_base->cond = BITS(inst, 28, 31);
139 inst_base->idx = index; 131 inst_base->idx = index;
140 inst_base->br = TransExtData::NON_BRANCH; 132 inst_base->br = TransExtData::NON_BRANCH;
141 133
142 inst_cream->imm = (BITS(inst, 8, 19) << 4) | BITS(inst, 0, 3); 134 inst_cream->imm = (BITS(inst, 8, 19) << 4) | BITS(inst, 0, 3);
143 135
144 return inst_base; 136 return inst_base;
145} 137}
146 138
147static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) 139static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) {
148{ 140 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst));
149 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst)); 141 blx_inst* inst_cream = (blx_inst*)inst_base->component;
150 blx_inst *inst_cream = (blx_inst *)inst_base->component;
151 142
152 inst_base->cond = BITS(inst, 28, 31); 143 inst_base->cond = BITS(inst, 28, 31);
153 inst_base->idx = index; 144 inst_base->idx = index;
154 inst_base->br = TransExtData::INDIRECT_BRANCH; 145 inst_base->br = TransExtData::INDIRECT_BRANCH;
155 146
156 inst_cream->inst = inst; 147 inst_cream->inst = inst;
157 if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) { 148 if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
@@ -162,36 +153,34 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index)
162 153
163 return inst_base; 154 return inst_base;
164} 155}
165static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) 156static ARM_INST_PTR INTERPRETER_TRANSLATE(bx)(unsigned int inst, int index) {
166{ 157 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst));
167 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bx_inst)); 158 bx_inst* inst_cream = (bx_inst*)inst_base->component;
168 bx_inst *inst_cream = (bx_inst *)inst_base->component;
169 159
170 inst_base->cond = BITS(inst, 28, 31); 160 inst_base->cond = BITS(inst, 28, 31);
171 inst_base->idx = index; 161 inst_base->idx = index;
172 inst_base->br = TransExtData::INDIRECT_BRANCH; 162 inst_base->br = TransExtData::INDIRECT_BRANCH;
173 163
174 inst_cream->Rm = BITS(inst, 0, 3); 164 inst_cream->Rm = BITS(inst, 0, 3);
175 165
176 return inst_base; 166 return inst_base;
177} 167}
178static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) 168static ARM_INST_PTR INTERPRETER_TRANSLATE(bxj)(unsigned int inst, int index) {
179{
180 return INTERPRETER_TRANSLATE(bx)(inst, index); 169 return INTERPRETER_TRANSLATE(bx)(inst, index);
181} 170}
182 171
183static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) { 172static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
184 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst)); 173 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cdp_inst));
185 cdp_inst *inst_cream = (cdp_inst *)inst_base->component; 174 cdp_inst* inst_cream = (cdp_inst*)inst_base->component;
186 175
187 inst_base->cond = BITS(inst, 28, 31); 176 inst_base->cond = BITS(inst, 28, 31);
188 inst_base->idx = index; 177 inst_base->idx = index;
189 inst_base->br = TransExtData::NON_BRANCH; 178 inst_base->br = TransExtData::NON_BRANCH;
190 179
191 inst_cream->CRm = BITS(inst, 0, 3); 180 inst_cream->CRm = BITS(inst, 0, 3);
192 inst_cream->CRd = BITS(inst, 12, 15); 181 inst_cream->CRd = BITS(inst, 12, 15);
193 inst_cream->CRn = BITS(inst, 16, 19); 182 inst_cream->CRn = BITS(inst, 16, 19);
194 inst_cream->cp_num = BITS(inst, 8, 11); 183 inst_cream->cp_num = BITS(inst, 8, 11);
195 inst_cream->opcode_2 = BITS(inst, 5, 7); 184 inst_cream->opcode_2 = BITS(inst, 5, 7);
196 inst_cream->opcode_1 = BITS(inst, 20, 23); 185 inst_cream->opcode_1 = BITS(inst, 20, 23);
197 inst_cream->inst = inst; 186 inst_cream->inst = inst;
@@ -199,91 +188,85 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cdp)(unsigned int inst, int index) {
199 LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index); 188 LOG_TRACE(Core_ARM11, "inst %x index %x", inst, index);
200 return inst_base; 189 return inst_base;
201} 190}
202static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) 191static ARM_INST_PTR INTERPRETER_TRANSLATE(clrex)(unsigned int inst, int index) {
203{ 192 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst));
204 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clrex_inst));
205 inst_base->cond = BITS(inst, 28, 31); 193 inst_base->cond = BITS(inst, 28, 31);
206 inst_base->idx = index; 194 inst_base->idx = index;
207 inst_base->br = TransExtData::NON_BRANCH; 195 inst_base->br = TransExtData::NON_BRANCH;
208 196
209 return inst_base; 197 return inst_base;
210} 198}
211static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) 199static ARM_INST_PTR INTERPRETER_TRANSLATE(clz)(unsigned int inst, int index) {
212{ 200 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst));
213 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(clz_inst)); 201 clz_inst* inst_cream = (clz_inst*)inst_base->component;
214 clz_inst *inst_cream = (clz_inst *)inst_base->component;
215 202
216 inst_base->cond = BITS(inst, 28, 31); 203 inst_base->cond = BITS(inst, 28, 31);
217 inst_base->idx = index; 204 inst_base->idx = index;
218 inst_base->br = TransExtData::NON_BRANCH; 205 inst_base->br = TransExtData::NON_BRANCH;
219 206
220 inst_cream->Rm = BITS(inst, 0, 3); 207 inst_cream->Rm = BITS(inst, 0, 3);
221 inst_cream->Rd = BITS(inst, 12, 15); 208 inst_cream->Rd = BITS(inst, 12, 15);
222 209
223 return inst_base; 210 return inst_base;
224} 211}
225static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) 212static ARM_INST_PTR INTERPRETER_TRANSLATE(cmn)(unsigned int inst, int index) {
226{ 213 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst));
227 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmn_inst)); 214 cmn_inst* inst_cream = (cmn_inst*)inst_base->component;
228 cmn_inst *inst_cream = (cmn_inst *)inst_base->component;
229 215
230 inst_base->cond = BITS(inst, 28, 31); 216 inst_base->cond = BITS(inst, 28, 31);
231 inst_base->idx = index; 217 inst_base->idx = index;
232 inst_base->br = TransExtData::NON_BRANCH; 218 inst_base->br = TransExtData::NON_BRANCH;
233 219
234 inst_cream->I = BIT(inst, 25); 220 inst_cream->I = BIT(inst, 25);
235 inst_cream->Rn = BITS(inst, 16, 19); 221 inst_cream->Rn = BITS(inst, 16, 19);
236 inst_cream->shifter_operand = BITS(inst, 0, 11); 222 inst_cream->shifter_operand = BITS(inst, 0, 11);
237 inst_cream->shtop_func = GetShifterOp(inst); 223 inst_cream->shtop_func = GetShifterOp(inst);
238 224
239 return inst_base; 225 return inst_base;
240} 226}
241static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) 227static ARM_INST_PTR INTERPRETER_TRANSLATE(cmp)(unsigned int inst, int index) {
242{ 228 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst));
243 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cmp_inst)); 229 cmp_inst* inst_cream = (cmp_inst*)inst_base->component;
244 cmp_inst *inst_cream = (cmp_inst *)inst_base->component;
245 230
246 inst_base->cond = BITS(inst, 28, 31); 231 inst_base->cond = BITS(inst, 28, 31);
247 inst_base->idx = index; 232 inst_base->idx = index;
248 inst_base->br = TransExtData::NON_BRANCH; 233 inst_base->br = TransExtData::NON_BRANCH;
249 234
250 inst_cream->I = BIT(inst, 25); 235 inst_cream->I = BIT(inst, 25);
251 inst_cream->Rn = BITS(inst, 16, 19); 236 inst_cream->Rn = BITS(inst, 16, 19);
252 inst_cream->shifter_operand = BITS(inst, 0, 11); 237 inst_cream->shifter_operand = BITS(inst, 0, 11);
253 inst_cream->shtop_func = GetShifterOp(inst); 238 inst_cream->shtop_func = GetShifterOp(inst);
254 239
255 return inst_base; 240 return inst_base;
256} 241}
257static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) 242static ARM_INST_PTR INTERPRETER_TRANSLATE(cps)(unsigned int inst, int index) {
258{ 243 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst));
259 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(cps_inst)); 244 cps_inst* inst_cream = (cps_inst*)inst_base->component;
260 cps_inst *inst_cream = (cps_inst *)inst_base->component;
261 245
262 inst_base->cond = BITS(inst, 28, 31); 246 inst_base->cond = BITS(inst, 28, 31);
263 inst_base->idx = index; 247 inst_base->idx = index;
264 inst_base->br = TransExtData::NON_BRANCH; 248 inst_base->br = TransExtData::NON_BRANCH;
265 249
266 inst_cream->imod0 = BIT(inst, 18); 250 inst_cream->imod0 = BIT(inst, 18);
267 inst_cream->imod1 = BIT(inst, 19); 251 inst_cream->imod1 = BIT(inst, 19);
268 inst_cream->mmod = BIT(inst, 17); 252 inst_cream->mmod = BIT(inst, 17);
269 inst_cream->A = BIT(inst, 8); 253 inst_cream->A = BIT(inst, 8);
270 inst_cream->I = BIT(inst, 7); 254 inst_cream->I = BIT(inst, 7);
271 inst_cream->F = BIT(inst, 6); 255 inst_cream->F = BIT(inst, 6);
272 inst_cream->mode = BITS(inst, 0, 4); 256 inst_cream->mode = BITS(inst, 0, 4);
273 257
274 return inst_base; 258 return inst_base;
275} 259}
276static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) 260static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index) {
277{ 261 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst));
278 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); 262 mov_inst* inst_cream = (mov_inst*)inst_base->component;
279 mov_inst *inst_cream = (mov_inst *)inst_base->component;
280 263
281 inst_base->cond = BITS(inst, 28, 31); 264 inst_base->cond = BITS(inst, 28, 31);
282 inst_base->idx = index; 265 inst_base->idx = index;
283 inst_base->br = TransExtData::NON_BRANCH; 266 inst_base->br = TransExtData::NON_BRANCH;
284 267
285 inst_cream->I = BIT(inst, 25); 268 inst_cream->I = BIT(inst, 25);
286 inst_cream->S = BIT(inst, 20); 269 inst_cream->S = BIT(inst, 20);
287 inst_cream->Rd = BITS(inst, 12, 15); 270 inst_cream->Rd = BITS(inst, 12, 15);
288 inst_cream->shifter_operand = BITS(inst, 0, 11); 271 inst_cream->shifter_operand = BITS(inst, 0, 11);
289 inst_cream->shtop_func = GetShifterOp(inst); 272 inst_cream->shtop_func = GetShifterOp(inst);
@@ -293,17 +276,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(cpy)(unsigned int inst, int index)
293 } 276 }
294 return inst_base; 277 return inst_base;
295} 278}
296static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) 279static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index) {
297{ 280 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst));
298 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(eor_inst)); 281 eor_inst* inst_cream = (eor_inst*)inst_base->component;
299 eor_inst *inst_cream = (eor_inst *)inst_base->component;
300 282
301 inst_base->cond = BITS(inst, 28, 31); 283 inst_base->cond = BITS(inst, 28, 31);
302 inst_base->idx = index; 284 inst_base->idx = index;
303 inst_base->br = TransExtData::NON_BRANCH; 285 inst_base->br = TransExtData::NON_BRANCH;
304 286
305 inst_cream->I = BIT(inst, 25); 287 inst_cream->I = BIT(inst, 25);
306 inst_cream->S = BIT(inst, 20); 288 inst_cream->S = BIT(inst, 20);
307 inst_cream->Rn = BITS(inst, 16, 19); 289 inst_cream->Rn = BITS(inst, 16, 19);
308 inst_cream->Rd = BITS(inst, 12, 15); 290 inst_cream->Rd = BITS(inst, 12, 15);
309 inst_cream->shifter_operand = BITS(inst, 0, 11); 291 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -314,23 +296,21 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(eor)(unsigned int inst, int index)
314 296
315 return inst_base; 297 return inst_base;
316} 298}
317static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) 299static ARM_INST_PTR INTERPRETER_TRANSLATE(ldc)(unsigned int inst, int index) {
318{ 300 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst));
319 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldc_inst));
320 inst_base->cond = BITS(inst, 28, 31); 301 inst_base->cond = BITS(inst, 28, 31);
321 inst_base->idx = index; 302 inst_base->idx = index;
322 inst_base->br = TransExtData::NON_BRANCH; 303 inst_base->br = TransExtData::NON_BRANCH;
323 304
324 return inst_base; 305 return inst_base;
325} 306}
326static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) 307static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index) {
327{ 308 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
328 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 309 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
329 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
330 310
331 inst_base->cond = BITS(inst, 28, 31); 311 inst_base->cond = BITS(inst, 28, 31);
332 inst_base->idx = index; 312 inst_base->idx = index;
333 inst_base->br = TransExtData::NON_BRANCH; 313 inst_base->br = TransExtData::NON_BRANCH;
334 314
335 inst_cream->inst = inst; 315 inst_cream->inst = inst;
336 inst_cream->get_addr = GetAddressingOp(inst); 316 inst_cream->get_addr = GetAddressingOp(inst);
@@ -340,29 +320,27 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldm)(unsigned int inst, int index)
340 } 320 }
341 return inst_base; 321 return inst_base;
342} 322}
343static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) 323static ARM_INST_PTR INTERPRETER_TRANSLATE(sxth)(unsigned int inst, int index) {
344{ 324 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst));
345 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); 325 sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
346 sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component;
347 326
348 inst_base->cond = BITS(inst, 28, 31); 327 inst_base->cond = BITS(inst, 28, 31);
349 inst_base->idx = index; 328 inst_base->idx = index;
350 inst_base->br = TransExtData::NON_BRANCH; 329 inst_base->br = TransExtData::NON_BRANCH;
351 330
352 inst_cream->Rd = BITS(inst, 12, 15); 331 inst_cream->Rd = BITS(inst, 12, 15);
353 inst_cream->Rm = BITS(inst, 0, 3); 332 inst_cream->Rm = BITS(inst, 0, 3);
354 inst_cream->rotate = BITS(inst, 10, 11); 333 inst_cream->rotate = BITS(inst, 10, 11);
355 334
356 return inst_base; 335 return inst_base;
357} 336}
358static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) 337static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index) {
359{ 338 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
360 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 339 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
361 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
362 340
363 inst_base->cond = BITS(inst, 28, 31); 341 inst_base->cond = BITS(inst, 28, 31);
364 inst_base->idx = index; 342 inst_base->idx = index;
365 inst_base->br = TransExtData::NON_BRANCH; 343 inst_base->br = TransExtData::NON_BRANCH;
366 344
367 inst_cream->inst = inst; 345 inst_cream->inst = inst;
368 inst_cream->get_addr = GetAddressingOp(inst); 346 inst_cream->get_addr = GetAddressingOp(inst);
@@ -373,14 +351,13 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldr)(unsigned int inst, int index)
373 return inst_base; 351 return inst_base;
374} 352}
375 353
376static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) 354static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index) {
377{ 355 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
378 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 356 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
379 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
380 357
381 inst_base->cond = BITS(inst, 28, 31); 358 inst_base->cond = BITS(inst, 28, 31);
382 inst_base->idx = index; 359 inst_base->idx = index;
383 inst_base->br = TransExtData::NON_BRANCH; 360 inst_base->br = TransExtData::NON_BRANCH;
384 361
385 inst_cream->inst = inst; 362 inst_cream->inst = inst;
386 inst_cream->get_addr = GetAddressingOp(inst); 363 inst_cream->get_addr = GetAddressingOp(inst);
@@ -391,155 +368,143 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrcond)(unsigned int inst, int index)
391 return inst_base; 368 return inst_base;
392} 369}
393 370
394static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) 371static ARM_INST_PTR INTERPRETER_TRANSLATE(uxth)(unsigned int inst, int index) {
395{ 372 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst));
396 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); 373 uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
397 uxth_inst *inst_cream = (uxth_inst *)inst_base->component;
398 374
399 inst_base->cond = BITS(inst, 28, 31); 375 inst_base->cond = BITS(inst, 28, 31);
400 inst_base->idx = index; 376 inst_base->idx = index;
401 inst_base->br = TransExtData::NON_BRANCH; 377 inst_base->br = TransExtData::NON_BRANCH;
402 378
403 inst_cream->Rd = BITS(inst, 12, 15); 379 inst_cream->Rd = BITS(inst, 12, 15);
404 inst_cream->rotate = BITS(inst, 10, 11); 380 inst_cream->rotate = BITS(inst, 10, 11);
405 inst_cream->Rm = BITS(inst, 0, 3); 381 inst_cream->Rm = BITS(inst, 0, 3);
406 382
407 return inst_base; 383 return inst_base;
408} 384}
409static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) 385static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtah)(unsigned int inst, int index) {
410{ 386 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst));
411 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtah_inst)); 387 uxtah_inst* inst_cream = (uxtah_inst*)inst_base->component;
412 uxtah_inst *inst_cream = (uxtah_inst *)inst_base->component;
413 388
414 inst_base->cond = BITS(inst, 28, 31); 389 inst_base->cond = BITS(inst, 28, 31);
415 inst_base->idx = index; 390 inst_base->idx = index;
416 inst_base->br = TransExtData::NON_BRANCH; 391 inst_base->br = TransExtData::NON_BRANCH;
417 392
418 inst_cream->Rn = BITS(inst, 16, 19); 393 inst_cream->Rn = BITS(inst, 16, 19);
419 inst_cream->Rd = BITS(inst, 12, 15); 394 inst_cream->Rd = BITS(inst, 12, 15);
420 inst_cream->rotate = BITS(inst, 10, 11); 395 inst_cream->rotate = BITS(inst, 10, 11);
421 inst_cream->Rm = BITS(inst, 0, 3); 396 inst_cream->Rm = BITS(inst, 0, 3);
422 397
423 return inst_base; 398 return inst_base;
424} 399}
425static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) 400static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) {
426{ 401 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
427 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 402 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
428 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
429 403
430 inst_base->cond = BITS(inst, 28, 31); 404 inst_base->cond = BITS(inst, 28, 31);
431 inst_base->idx = index; 405 inst_base->idx = index;
432 inst_base->br = TransExtData::NON_BRANCH; 406 inst_base->br = TransExtData::NON_BRANCH;
433 407
434 inst_cream->inst = inst; 408 inst_cream->inst = inst;
435 inst_cream->get_addr = GetAddressingOp(inst); 409 inst_cream->get_addr = GetAddressingOp(inst);
436 410
437 return inst_base; 411 return inst_base;
438} 412}
439static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) 413static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) {
440{
441 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 414 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
442 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 415 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
443 416
444 inst_base->cond = BITS(inst, 28, 31); 417 inst_base->cond = BITS(inst, 28, 31);
445 inst_base->idx = index; 418 inst_base->idx = index;
446 inst_base->br = TransExtData::NON_BRANCH; 419 inst_base->br = TransExtData::NON_BRANCH;
447 420
448 inst_cream->inst = inst; 421 inst_cream->inst = inst;
449 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); 422 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
450 423
451 return inst_base; 424 return inst_base;
452} 425}
453static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) 426static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) {
454{ 427 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
455 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 428 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
456 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
457 429
458 inst_base->cond = BITS(inst, 28, 31); 430 inst_base->cond = BITS(inst, 28, 31);
459 inst_base->idx = index; 431 inst_base->idx = index;
460 inst_base->br = TransExtData::NON_BRANCH; 432 inst_base->br = TransExtData::NON_BRANCH;
461 433
462 inst_cream->inst = inst; 434 inst_cream->inst = inst;
463 inst_cream->get_addr = GetAddressingOp(inst); 435 inst_cream->get_addr = GetAddressingOp(inst);
464 436
465 return inst_base; 437 return inst_base;
466} 438}
467static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) 439static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrex)(unsigned int inst, int index) {
468{ 440 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
469 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 441 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
470 generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component;
471 442
472 inst_base->cond = BITS(inst, 28, 31); 443 inst_base->cond = BITS(inst, 28, 31);
473 inst_base->idx = index; 444 inst_base->idx = index;
474 inst_base->br = (BITS(inst, 12, 15) == 15) ? TransExtData::INDIRECT_BRANCH : TransExtData::NON_BRANCH; // Branch if dest is R15 445 inst_base->br = (BITS(inst, 12, 15) == 15) ? TransExtData::INDIRECT_BRANCH
446 : TransExtData::NON_BRANCH; // Branch if dest is R15
475 447
476 inst_cream->Rn = BITS(inst, 16, 19); 448 inst_cream->Rn = BITS(inst, 16, 19);
477 inst_cream->Rd = BITS(inst, 12, 15); 449 inst_cream->Rd = BITS(inst, 12, 15);
478 450
479 return inst_base; 451 return inst_base;
480} 452}
481static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) 453static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexb)(unsigned int inst, int index) {
482{
483 return INTERPRETER_TRANSLATE(ldrex)(inst, index); 454 return INTERPRETER_TRANSLATE(ldrex)(inst, index);
484} 455}
485static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) 456static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexh)(unsigned int inst, int index) {
486{
487 return INTERPRETER_TRANSLATE(ldrex)(inst, index); 457 return INTERPRETER_TRANSLATE(ldrex)(inst, index);
488} 458}
489static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) 459static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrexd)(unsigned int inst, int index) {
490{
491 return INTERPRETER_TRANSLATE(ldrex)(inst, index); 460 return INTERPRETER_TRANSLATE(ldrex)(inst, index);
492} 461}
493static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) 462static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) {
494{ 463 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
495 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 464 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
496 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
497 465
498 inst_base->cond = BITS(inst, 28, 31); 466 inst_base->cond = BITS(inst, 28, 31);
499 inst_base->idx = index; 467 inst_base->idx = index;
500 inst_base->br = TransExtData::NON_BRANCH; 468 inst_base->br = TransExtData::NON_BRANCH;
501 469
502 inst_cream->inst = inst; 470 inst_cream->inst = inst;
503 inst_cream->get_addr = GetAddressingOp(inst); 471 inst_cream->get_addr = GetAddressingOp(inst);
504 472
505 return inst_base; 473 return inst_base;
506} 474}
507static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) 475static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) {
508{ 476 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
509 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 477 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
510 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
511 478
512 inst_base->cond = BITS(inst, 28, 31); 479 inst_base->cond = BITS(inst, 28, 31);
513 inst_base->idx = index; 480 inst_base->idx = index;
514 inst_base->br = TransExtData::NON_BRANCH; 481 inst_base->br = TransExtData::NON_BRANCH;
515 482
516 inst_cream->inst = inst; 483 inst_cream->inst = inst;
517 inst_cream->get_addr = GetAddressingOp(inst); 484 inst_cream->get_addr = GetAddressingOp(inst);
518 485
519 return inst_base; 486 return inst_base;
520} 487}
521static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) 488static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) {
522{ 489 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
523 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 490 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
524 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
525 491
526 inst_base->cond = BITS(inst, 28, 31); 492 inst_base->cond = BITS(inst, 28, 31);
527 inst_base->idx = index; 493 inst_base->idx = index;
528 inst_base->br = TransExtData::NON_BRANCH; 494 inst_base->br = TransExtData::NON_BRANCH;
529 495
530 inst_cream->inst = inst; 496 inst_cream->inst = inst;
531 inst_cream->get_addr = GetAddressingOp(inst); 497 inst_cream->get_addr = GetAddressingOp(inst);
532 498
533 return inst_base; 499 return inst_base;
534} 500}
535static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) 501static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) {
536{
537 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 502 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
538 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 503 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
539 504
540 inst_base->cond = BITS(inst, 28, 31); 505 inst_base->cond = BITS(inst, 28, 31);
541 inst_base->idx = index; 506 inst_base->idx = index;
542 inst_base->br = TransExtData::NON_BRANCH; 507 inst_base->br = TransExtData::NON_BRANCH;
543 508
544 inst_cream->inst = inst; 509 inst_cream->inst = inst;
545 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); 510 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
@@ -549,70 +514,66 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
549 } 514 }
550 return inst_base; 515 return inst_base;
551} 516}
552static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) 517static ARM_INST_PTR INTERPRETER_TRANSLATE(mcr)(unsigned int inst, int index) {
553{ 518 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst));
554 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mcr_inst)); 519 mcr_inst* inst_cream = (mcr_inst*)inst_base->component;
555 mcr_inst *inst_cream = (mcr_inst *)inst_base->component;
556 inst_base->cond = BITS(inst, 28, 31); 520 inst_base->cond = BITS(inst, 28, 31);
557 inst_base->idx = index; 521 inst_base->idx = index;
558 inst_base->br = TransExtData::NON_BRANCH; 522 inst_base->br = TransExtData::NON_BRANCH;
559 523
560 inst_cream->crn = BITS(inst, 16, 19); 524 inst_cream->crn = BITS(inst, 16, 19);
561 inst_cream->crm = BITS(inst, 0, 3); 525 inst_cream->crm = BITS(inst, 0, 3);
562 inst_cream->opcode_1 = BITS(inst, 21, 23); 526 inst_cream->opcode_1 = BITS(inst, 21, 23);
563 inst_cream->opcode_2 = BITS(inst, 5, 7); 527 inst_cream->opcode_2 = BITS(inst, 5, 7);
564 inst_cream->Rd = BITS(inst, 12, 15); 528 inst_cream->Rd = BITS(inst, 12, 15);
565 inst_cream->cp_num = BITS(inst, 8, 11); 529 inst_cream->cp_num = BITS(inst, 8, 11);
566 inst_cream->inst = inst; 530 inst_cream->inst = inst;
567 return inst_base; 531 return inst_base;
568} 532}
569 533
570static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) 534static ARM_INST_PTR INTERPRETER_TRANSLATE(mcrr)(unsigned int inst, int index) {
571{
572 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcrr_inst)); 535 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mcrr_inst));
573 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component; 536 mcrr_inst* const inst_cream = (mcrr_inst*)inst_base->component;
574 537
575 inst_base->cond = BITS(inst, 28, 31); 538 inst_base->cond = BITS(inst, 28, 31);
576 inst_base->idx = index; 539 inst_base->idx = index;
577 inst_base->br = TransExtData::NON_BRANCH; 540 inst_base->br = TransExtData::NON_BRANCH;
578 541
579 inst_cream->crm = BITS(inst, 0, 3); 542 inst_cream->crm = BITS(inst, 0, 3);
580 inst_cream->opcode_1 = BITS(inst, 4, 7); 543 inst_cream->opcode_1 = BITS(inst, 4, 7);
581 inst_cream->cp_num = BITS(inst, 8, 11); 544 inst_cream->cp_num = BITS(inst, 8, 11);
582 inst_cream->rt = BITS(inst, 12, 15); 545 inst_cream->rt = BITS(inst, 12, 15);
583 inst_cream->rt2 = BITS(inst, 16, 19); 546 inst_cream->rt2 = BITS(inst, 16, 19);
584 547
585 return inst_base; 548 return inst_base;
586} 549}
587 550
588static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) 551static ARM_INST_PTR INTERPRETER_TRANSLATE(mla)(unsigned int inst, int index) {
589{ 552 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst));
590 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mla_inst)); 553 mla_inst* inst_cream = (mla_inst*)inst_base->component;
591 mla_inst *inst_cream = (mla_inst *)inst_base->component;
592 554
593 inst_base->cond = BITS(inst, 28, 31); 555 inst_base->cond = BITS(inst, 28, 31);
594 inst_base->idx = index; 556 inst_base->idx = index;
595 inst_base->br = TransExtData::NON_BRANCH; 557 inst_base->br = TransExtData::NON_BRANCH;
596 558
597 inst_cream->S = BIT(inst, 20); 559 inst_cream->S = BIT(inst, 20);
598 inst_cream->Rn = BITS(inst, 12, 15); 560 inst_cream->Rn = BITS(inst, 12, 15);
599 inst_cream->Rd = BITS(inst, 16, 19); 561 inst_cream->Rd = BITS(inst, 16, 19);
600 inst_cream->Rs = BITS(inst, 8, 11); 562 inst_cream->Rs = BITS(inst, 8, 11);
601 inst_cream->Rm = BITS(inst, 0, 3); 563 inst_cream->Rm = BITS(inst, 0, 3);
602 564
603 return inst_base; 565 return inst_base;
604} 566}
605static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) 567static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index) {
606{ 568 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst));
607 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mov_inst)); 569 mov_inst* inst_cream = (mov_inst*)inst_base->component;
608 mov_inst *inst_cream = (mov_inst *)inst_base->component;
609 570
610 inst_base->cond = BITS(inst, 28, 31); 571 inst_base->cond = BITS(inst, 28, 31);
611 inst_base->idx = index; 572 inst_base->idx = index;
612 inst_base->br = TransExtData::NON_BRANCH; 573 inst_base->br = TransExtData::NON_BRANCH;
613 574
614 inst_cream->I = BIT(inst, 25); 575 inst_cream->I = BIT(inst, 25);
615 inst_cream->S = BIT(inst, 20); 576 inst_cream->S = BIT(inst, 20);
616 inst_cream->Rd = BITS(inst, 12, 15); 577 inst_cream->Rd = BITS(inst, 12, 15);
617 inst_cream->shifter_operand = BITS(inst, 0, 11); 578 inst_cream->shifter_operand = BITS(inst, 0, 11);
618 inst_cream->shtop_func = GetShifterOp(inst); 579 inst_cream->shtop_func = GetShifterOp(inst);
@@ -622,85 +583,79 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mov)(unsigned int inst, int index)
622 } 583 }
623 return inst_base; 584 return inst_base;
624} 585}
625static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) 586static ARM_INST_PTR INTERPRETER_TRANSLATE(mrc)(unsigned int inst, int index) {
626{ 587 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst));
627 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrc_inst)); 588 mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
628 mrc_inst *inst_cream = (mrc_inst *)inst_base->component;
629 inst_base->cond = BITS(inst, 28, 31); 589 inst_base->cond = BITS(inst, 28, 31);
630 inst_base->idx = index; 590 inst_base->idx = index;
631 inst_base->br = TransExtData::NON_BRANCH; 591 inst_base->br = TransExtData::NON_BRANCH;
632 592
633 inst_cream->crn = BITS(inst, 16, 19); 593 inst_cream->crn = BITS(inst, 16, 19);
634 inst_cream->crm = BITS(inst, 0, 3); 594 inst_cream->crm = BITS(inst, 0, 3);
635 inst_cream->opcode_1 = BITS(inst, 21, 23); 595 inst_cream->opcode_1 = BITS(inst, 21, 23);
636 inst_cream->opcode_2 = BITS(inst, 5, 7); 596 inst_cream->opcode_2 = BITS(inst, 5, 7);
637 inst_cream->Rd = BITS(inst, 12, 15); 597 inst_cream->Rd = BITS(inst, 12, 15);
638 inst_cream->cp_num = BITS(inst, 8, 11); 598 inst_cream->cp_num = BITS(inst, 8, 11);
639 inst_cream->inst = inst; 599 inst_cream->inst = inst;
640 return inst_base; 600 return inst_base;
641} 601}
642 602
643static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) 603static ARM_INST_PTR INTERPRETER_TRANSLATE(mrrc)(unsigned int inst, int index) {
644{
645 return INTERPRETER_TRANSLATE(mcrr)(inst, index); 604 return INTERPRETER_TRANSLATE(mcrr)(inst, index);
646} 605}
647 606
648static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) 607static ARM_INST_PTR INTERPRETER_TRANSLATE(mrs)(unsigned int inst, int index) {
649{ 608 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst));
650 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mrs_inst)); 609 mrs_inst* inst_cream = (mrs_inst*)inst_base->component;
651 mrs_inst *inst_cream = (mrs_inst *)inst_base->component;
652 610
653 inst_base->cond = BITS(inst, 28, 31); 611 inst_base->cond = BITS(inst, 28, 31);
654 inst_base->idx = index; 612 inst_base->idx = index;
655 inst_base->br = TransExtData::NON_BRANCH; 613 inst_base->br = TransExtData::NON_BRANCH;
656 614
657 inst_cream->Rd = BITS(inst, 12, 15); 615 inst_cream->Rd = BITS(inst, 12, 15);
658 inst_cream->R = BIT(inst, 22); 616 inst_cream->R = BIT(inst, 22);
659 617
660 return inst_base; 618 return inst_base;
661} 619}
662static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) 620static ARM_INST_PTR INTERPRETER_TRANSLATE(msr)(unsigned int inst, int index) {
663{ 621 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst));
664 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(msr_inst)); 622 msr_inst* inst_cream = (msr_inst*)inst_base->component;
665 msr_inst *inst_cream = (msr_inst *)inst_base->component;
666 623
667 inst_base->cond = BITS(inst, 28, 31); 624 inst_base->cond = BITS(inst, 28, 31);
668 inst_base->idx = index; 625 inst_base->idx = index;
669 inst_base->br = TransExtData::NON_BRANCH; 626 inst_base->br = TransExtData::NON_BRANCH;
670 627
671 inst_cream->field_mask = BITS(inst, 16, 19); 628 inst_cream->field_mask = BITS(inst, 16, 19);
672 inst_cream->R = BIT(inst, 22); 629 inst_cream->R = BIT(inst, 22);
673 inst_cream->inst = inst; 630 inst_cream->inst = inst;
674 631
675 return inst_base; 632 return inst_base;
676} 633}
677static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) 634static ARM_INST_PTR INTERPRETER_TRANSLATE(mul)(unsigned int inst, int index) {
678{ 635 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst));
679 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mul_inst)); 636 mul_inst* inst_cream = (mul_inst*)inst_base->component;
680 mul_inst *inst_cream = (mul_inst *)inst_base->component;
681 637
682 inst_base->cond = BITS(inst, 28, 31); 638 inst_base->cond = BITS(inst, 28, 31);
683 inst_base->idx = index; 639 inst_base->idx = index;
684 inst_base->br = TransExtData::NON_BRANCH; 640 inst_base->br = TransExtData::NON_BRANCH;
685 641
686 inst_cream->S = BIT(inst, 20); 642 inst_cream->S = BIT(inst, 20);
687 inst_cream->Rm = BITS(inst, 0, 3); 643 inst_cream->Rm = BITS(inst, 0, 3);
688 inst_cream->Rs = BITS(inst, 8, 11); 644 inst_cream->Rs = BITS(inst, 8, 11);
689 inst_cream->Rd = BITS(inst, 16, 19); 645 inst_cream->Rd = BITS(inst, 16, 19);
690 646
691 return inst_base; 647 return inst_base;
692} 648}
693static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) 649static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index) {
694{ 650 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst));
695 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(mvn_inst)); 651 mvn_inst* inst_cream = (mvn_inst*)inst_base->component;
696 mvn_inst *inst_cream = (mvn_inst *)inst_base->component;
697 652
698 inst_base->cond = BITS(inst, 28, 31); 653 inst_base->cond = BITS(inst, 28, 31);
699 inst_base->idx = index; 654 inst_base->idx = index;
700 inst_base->br = TransExtData::NON_BRANCH; 655 inst_base->br = TransExtData::NON_BRANCH;
701 656
702 inst_cream->I = BIT(inst, 25); 657 inst_cream->I = BIT(inst, 25);
703 inst_cream->S = BIT(inst, 20); 658 inst_cream->S = BIT(inst, 20);
704 inst_cream->Rd = BITS(inst, 12, 15); 659 inst_cream->Rd = BITS(inst, 12, 15);
705 inst_cream->shifter_operand = BITS(inst, 0, 11); 660 inst_cream->shifter_operand = BITS(inst, 0, 11);
706 inst_cream->shtop_func = GetShifterOp(inst); 661 inst_cream->shtop_func = GetShifterOp(inst);
@@ -709,19 +664,17 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(mvn)(unsigned int inst, int index)
709 inst_base->br = TransExtData::INDIRECT_BRANCH; 664 inst_base->br = TransExtData::INDIRECT_BRANCH;
710 } 665 }
711 return inst_base; 666 return inst_base;
712
713} 667}
714static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) 668static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index) {
715{ 669 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst));
716 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(orr_inst)); 670 orr_inst* inst_cream = (orr_inst*)inst_base->component;
717 orr_inst *inst_cream = (orr_inst *)inst_base->component;
718 671
719 inst_base->cond = BITS(inst, 28, 31); 672 inst_base->cond = BITS(inst, 28, 31);
720 inst_base->idx = index; 673 inst_base->idx = index;
721 inst_base->br = TransExtData::NON_BRANCH; 674 inst_base->br = TransExtData::NON_BRANCH;
722 675
723 inst_cream->I = BIT(inst, 25); 676 inst_cream->I = BIT(inst, 25);
724 inst_cream->S = BIT(inst, 20); 677 inst_cream->S = BIT(inst, 20);
725 inst_cream->Rd = BITS(inst, 12, 15); 678 inst_cream->Rd = BITS(inst, 12, 15);
726 inst_cream->Rn = BITS(inst, 16, 19); 679 inst_cream->Rn = BITS(inst, 16, 19);
727 inst_cream->shifter_operand = BITS(inst, 0, 11); 680 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -734,150 +687,132 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(orr)(unsigned int inst, int index)
734} 687}
735 688
736// NOP introduced in ARMv6K. 689// NOP introduced in ARMv6K.
737static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index) 690static ARM_INST_PTR INTERPRETER_TRANSLATE(nop)(unsigned int inst, int index) {
738{
739 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); 691 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
740 692
741 inst_base->cond = BITS(inst, 28, 31); 693 inst_base->cond = BITS(inst, 28, 31);
742 inst_base->idx = index; 694 inst_base->idx = index;
743 inst_base->br = TransExtData::NON_BRANCH; 695 inst_base->br = TransExtData::NON_BRANCH;
744 696
745 return inst_base; 697 return inst_base;
746} 698}
747 699
748static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) 700static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhbt)(unsigned int inst, int index) {
749{ 701 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst));
750 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pkh_inst)); 702 pkh_inst* inst_cream = (pkh_inst*)inst_base->component;
751 pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
752 703
753 inst_base->cond = BITS(inst, 28, 31); 704 inst_base->cond = BITS(inst, 28, 31);
754 inst_base->idx = index; 705 inst_base->idx = index;
755 inst_base->br = TransExtData::NON_BRANCH; 706 inst_base->br = TransExtData::NON_BRANCH;
756 707
757 inst_cream->Rd = BITS(inst, 12, 15); 708 inst_cream->Rd = BITS(inst, 12, 15);
758 inst_cream->Rn = BITS(inst, 16, 19); 709 inst_cream->Rn = BITS(inst, 16, 19);
759 inst_cream->Rm = BITS(inst, 0, 3); 710 inst_cream->Rm = BITS(inst, 0, 3);
760 inst_cream->imm = BITS(inst, 7, 11); 711 inst_cream->imm = BITS(inst, 7, 11);
761 712
762 return inst_base; 713 return inst_base;
763} 714}
764 715
765static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) 716static ARM_INST_PTR INTERPRETER_TRANSLATE(pkhtb)(unsigned int inst, int index) {
766{
767 return INTERPRETER_TRANSLATE(pkhbt)(inst, index); 717 return INTERPRETER_TRANSLATE(pkhbt)(inst, index);
768} 718}
769 719
770static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) 720static ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index) {
771{ 721 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst));
772 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(pld_inst));
773 722
774 inst_base->cond = BITS(inst, 28, 31); 723 inst_base->cond = BITS(inst, 28, 31);
775 inst_base->idx = index; 724 inst_base->idx = index;
776 inst_base->br = TransExtData::NON_BRANCH; 725 inst_base->br = TransExtData::NON_BRANCH;
777 726
778 return inst_base; 727 return inst_base;
779} 728}
780 729
781static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) 730static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) {
782{
783 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 731 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
784 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 732 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
785 733
786 inst_base->cond = BITS(inst, 28, 31); 734 inst_base->cond = BITS(inst, 28, 31);
787 inst_base->idx = index; 735 inst_base->idx = index;
788 inst_base->br = TransExtData::NON_BRANCH; 736 inst_base->br = TransExtData::NON_BRANCH;
789 737
790 inst_cream->op1 = BITS(inst, 21, 22); 738 inst_cream->op1 = BITS(inst, 21, 22);
791 inst_cream->Rm = BITS(inst, 0, 3); 739 inst_cream->Rm = BITS(inst, 0, 3);
792 inst_cream->Rn = BITS(inst, 16, 19); 740 inst_cream->Rn = BITS(inst, 16, 19);
793 inst_cream->Rd = BITS(inst, 12, 15); 741 inst_cream->Rd = BITS(inst, 12, 15);
794 742
795 return inst_base; 743 return inst_base;
796} 744}
797static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) 745static ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) {
798{
799 return INTERPRETER_TRANSLATE(qadd)(inst, index); 746 return INTERPRETER_TRANSLATE(qadd)(inst, index);
800} 747}
801static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) 748static ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) {
802{
803 return INTERPRETER_TRANSLATE(qadd)(inst, index); 749 return INTERPRETER_TRANSLATE(qadd)(inst, index);
804} 750}
805static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) 751static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) {
806{
807 return INTERPRETER_TRANSLATE(qadd)(inst, index); 752 return INTERPRETER_TRANSLATE(qadd)(inst, index);
808} 753}
809 754
810static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) 755static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index) {
811{
812 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 756 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
813 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 757 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
814 758
815 inst_base->cond = BITS(inst, 28, 31); 759 inst_base->cond = BITS(inst, 28, 31);
816 inst_base->idx = index; 760 inst_base->idx = index;
817 inst_base->br = TransExtData::NON_BRANCH; 761 inst_base->br = TransExtData::NON_BRANCH;
818 762
819 inst_cream->Rm = BITS(inst, 0, 3); 763 inst_cream->Rm = BITS(inst, 0, 3);
820 inst_cream->Rn = BITS(inst, 16, 19); 764 inst_cream->Rn = BITS(inst, 16, 19);
821 inst_cream->Rd = BITS(inst, 12, 15); 765 inst_cream->Rd = BITS(inst, 12, 15);
822 inst_cream->op1 = BITS(inst, 20, 21); 766 inst_cream->op1 = BITS(inst, 20, 21);
823 inst_cream->op2 = BITS(inst, 5, 7); 767 inst_cream->op2 = BITS(inst, 5, 7);
824 768
825 return inst_base; 769 return inst_base;
826} 770}
827static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) 771static ARM_INST_PTR INTERPRETER_TRANSLATE(qadd16)(unsigned int inst, int index) {
828{
829 return INTERPRETER_TRANSLATE(qadd8)(inst, index); 772 return INTERPRETER_TRANSLATE(qadd8)(inst, index);
830} 773}
831static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) 774static ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index) {
832{
833 return INTERPRETER_TRANSLATE(qadd8)(inst, index); 775 return INTERPRETER_TRANSLATE(qadd8)(inst, index);
834} 776}
835static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) 777static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index) {
836{
837 return INTERPRETER_TRANSLATE(qadd8)(inst, index); 778 return INTERPRETER_TRANSLATE(qadd8)(inst, index);
838} 779}
839static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) 780static ARM_INST_PTR INTERPRETER_TRANSLATE(qsub16)(unsigned int inst, int index) {
840{
841 return INTERPRETER_TRANSLATE(qadd8)(inst, index); 781 return INTERPRETER_TRANSLATE(qadd8)(inst, index);
842} 782}
843static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) 783static ARM_INST_PTR INTERPRETER_TRANSLATE(qsubaddx)(unsigned int inst, int index) {
844{
845 return INTERPRETER_TRANSLATE(qadd8)(inst, index); 784 return INTERPRETER_TRANSLATE(qadd8)(inst, index);
846} 785}
847 786
848static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) 787static ARM_INST_PTR INTERPRETER_TRANSLATE(rev)(unsigned int inst, int index) {
849{
850 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst)); 788 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rev_inst));
851 rev_inst* const inst_cream = (rev_inst*)inst_base->component; 789 rev_inst* const inst_cream = (rev_inst*)inst_base->component;
852 790
853 inst_base->cond = BITS(inst, 28, 31); 791 inst_base->cond = BITS(inst, 28, 31);
854 inst_base->idx = index; 792 inst_base->idx = index;
855 inst_base->br = TransExtData::NON_BRANCH; 793 inst_base->br = TransExtData::NON_BRANCH;
856 794
857 inst_cream->Rm = BITS(inst, 0, 3); 795 inst_cream->Rm = BITS(inst, 0, 3);
858 inst_cream->Rd = BITS(inst, 12, 15); 796 inst_cream->Rd = BITS(inst, 12, 15);
859 inst_cream->op1 = BITS(inst, 20, 22); 797 inst_cream->op1 = BITS(inst, 20, 22);
860 inst_cream->op2 = BITS(inst, 5, 7); 798 inst_cream->op2 = BITS(inst, 5, 7);
861 799
862 return inst_base; 800 return inst_base;
863} 801}
864static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) 802static ARM_INST_PTR INTERPRETER_TRANSLATE(rev16)(unsigned int inst, int index) {
865{
866 return INTERPRETER_TRANSLATE(rev)(inst, index); 803 return INTERPRETER_TRANSLATE(rev)(inst, index);
867} 804}
868static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) 805static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index) {
869{ 806 return INTERPRETER_TRANSLATE(rev)(inst, index);
870 return INTERPRETER_TRANSLATE(rev)(inst, index);
871} 807}
872 808
873static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) 809static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) {
874{
875 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 810 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
876 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; 811 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
877 812
878 inst_base->cond = AL; 813 inst_base->cond = AL;
879 inst_base->idx = index; 814 inst_base->idx = index;
880 inst_base->br = TransExtData::INDIRECT_BRANCH; 815 inst_base->br = TransExtData::INDIRECT_BRANCH;
881 816
882 inst_cream->inst = inst; 817 inst_cream->inst = inst;
883 inst_cream->get_addr = GetAddressingOp(inst); 818 inst_cream->get_addr = GetAddressingOp(inst);
@@ -885,17 +820,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index)
885 return inst_base; 820 return inst_base;
886} 821}
887 822
888static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) 823static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) {
889{ 824 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst));
890 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); 825 rsb_inst* inst_cream = (rsb_inst*)inst_base->component;
891 rsb_inst *inst_cream = (rsb_inst *)inst_base->component;
892 826
893 inst_base->cond = BITS(inst, 28, 31); 827 inst_base->cond = BITS(inst, 28, 31);
894 inst_base->idx = index; 828 inst_base->idx = index;
895 inst_base->br = TransExtData::NON_BRANCH; 829 inst_base->br = TransExtData::NON_BRANCH;
896 830
897 inst_cream->I = BIT(inst, 25); 831 inst_cream->I = BIT(inst, 25);
898 inst_cream->S = BIT(inst, 20); 832 inst_cream->S = BIT(inst, 20);
899 inst_cream->Rn = BITS(inst, 16, 19); 833 inst_cream->Rn = BITS(inst, 16, 19);
900 inst_cream->Rd = BITS(inst, 12, 15); 834 inst_cream->Rd = BITS(inst, 12, 15);
901 inst_cream->shifter_operand = BITS(inst, 0, 11); 835 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -906,17 +840,16 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index)
906 840
907 return inst_base; 841 return inst_base;
908} 842}
909static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) 843static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index) {
910{ 844 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst));
911 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsc_inst)); 845 rsc_inst* inst_cream = (rsc_inst*)inst_base->component;
912 rsc_inst *inst_cream = (rsc_inst *)inst_base->component;
913 846
914 inst_base->cond = BITS(inst, 28, 31); 847 inst_base->cond = BITS(inst, 28, 31);
915 inst_base->idx = index; 848 inst_base->idx = index;
916 inst_base->br = TransExtData::NON_BRANCH; 849 inst_base->br = TransExtData::NON_BRANCH;
917 850
918 inst_cream->I = BIT(inst, 25); 851 inst_cream->I = BIT(inst, 25);
919 inst_cream->S = BIT(inst, 20); 852 inst_cream->S = BIT(inst, 20);
920 inst_cream->Rn = BITS(inst, 16, 19); 853 inst_cream->Rn = BITS(inst, 16, 19);
921 inst_cream->Rd = BITS(inst, 12, 15); 854 inst_cream->Rd = BITS(inst, 12, 15);
922 inst_cream->shifter_operand = BITS(inst, 0, 11); 855 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -927,55 +860,48 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(rsc)(unsigned int inst, int index)
927 860
928 return inst_base; 861 return inst_base;
929} 862}
930static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) 863static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd8)(unsigned int inst, int index) {
931{
932 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 864 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
933 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 865 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
934 866
935 inst_base->cond = BITS(inst, 28, 31); 867 inst_base->cond = BITS(inst, 28, 31);
936 inst_base->idx = index; 868 inst_base->idx = index;
937 inst_base->br = TransExtData::NON_BRANCH; 869 inst_base->br = TransExtData::NON_BRANCH;
938 870
939 inst_cream->Rm = BITS(inst, 0, 3); 871 inst_cream->Rm = BITS(inst, 0, 3);
940 inst_cream->Rn = BITS(inst, 16, 19); 872 inst_cream->Rn = BITS(inst, 16, 19);
941 inst_cream->Rd = BITS(inst, 12, 15); 873 inst_cream->Rd = BITS(inst, 12, 15);
942 inst_cream->op1 = BITS(inst, 20, 21); 874 inst_cream->op1 = BITS(inst, 20, 21);
943 inst_cream->op2 = BITS(inst, 5, 7); 875 inst_cream->op2 = BITS(inst, 5, 7);
944 876
945 return inst_base; 877 return inst_base;
946} 878}
947static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) 879static ARM_INST_PTR INTERPRETER_TRANSLATE(sadd16)(unsigned int inst, int index) {
948{
949 return INTERPRETER_TRANSLATE(sadd8)(inst, index); 880 return INTERPRETER_TRANSLATE(sadd8)(inst, index);
950} 881}
951static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) 882static ARM_INST_PTR INTERPRETER_TRANSLATE(saddsubx)(unsigned int inst, int index) {
952{
953 return INTERPRETER_TRANSLATE(sadd8)(inst, index); 883 return INTERPRETER_TRANSLATE(sadd8)(inst, index);
954} 884}
955static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) 885static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub8)(unsigned int inst, int index) {
956{
957 return INTERPRETER_TRANSLATE(sadd8)(inst, index); 886 return INTERPRETER_TRANSLATE(sadd8)(inst, index);
958} 887}
959static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) 888static ARM_INST_PTR INTERPRETER_TRANSLATE(ssub16)(unsigned int inst, int index) {
960{
961 return INTERPRETER_TRANSLATE(sadd8)(inst, index); 889 return INTERPRETER_TRANSLATE(sadd8)(inst, index);
962} 890}
963static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) 891static ARM_INST_PTR INTERPRETER_TRANSLATE(ssubaddx)(unsigned int inst, int index) {
964{
965 return INTERPRETER_TRANSLATE(sadd8)(inst, index); 892 return INTERPRETER_TRANSLATE(sadd8)(inst, index);
966} 893}
967 894
968static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) 895static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index) {
969{ 896 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst));
970 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sbc_inst)); 897 sbc_inst* inst_cream = (sbc_inst*)inst_base->component;
971 sbc_inst *inst_cream = (sbc_inst *)inst_base->component;
972 898
973 inst_base->cond = BITS(inst, 28, 31); 899 inst_base->cond = BITS(inst, 28, 31);
974 inst_base->idx = index; 900 inst_base->idx = index;
975 inst_base->br = TransExtData::NON_BRANCH; 901 inst_base->br = TransExtData::NON_BRANCH;
976 902
977 inst_cream->I = BIT(inst, 25); 903 inst_cream->I = BIT(inst, 25);
978 inst_cream->S = BIT(inst, 20); 904 inst_cream->S = BIT(inst, 20);
979 inst_cream->Rn = BITS(inst, 16, 19); 905 inst_cream->Rn = BITS(inst, 16, 19);
980 inst_cream->Rd = BITS(inst, 12, 15); 906 inst_cream->Rd = BITS(inst, 12, 15);
981 inst_cream->shifter_operand = BITS(inst, 0, 11); 907 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -986,98 +912,88 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sbc)(unsigned int inst, int index)
986 912
987 return inst_base; 913 return inst_base;
988} 914}
989static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) 915static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index) {
990{
991 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 916 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
992 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 917 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
993 918
994 inst_base->cond = BITS(inst, 28, 31); 919 inst_base->cond = BITS(inst, 28, 31);
995 inst_base->idx = index; 920 inst_base->idx = index;
996 inst_base->br = TransExtData::NON_BRANCH; 921 inst_base->br = TransExtData::NON_BRANCH;
997 922
998 inst_cream->Rm = BITS(inst, 0, 3); 923 inst_cream->Rm = BITS(inst, 0, 3);
999 inst_cream->Rn = BITS(inst, 16, 19); 924 inst_cream->Rn = BITS(inst, 16, 19);
1000 inst_cream->Rd = BITS(inst, 12, 15); 925 inst_cream->Rd = BITS(inst, 12, 15);
1001 inst_cream->op1 = BITS(inst, 20, 22); 926 inst_cream->op1 = BITS(inst, 20, 22);
1002 inst_cream->op2 = BITS(inst, 5, 7); 927 inst_cream->op2 = BITS(inst, 5, 7);
1003 928
1004 return inst_base; 929 return inst_base;
1005} 930}
1006 931
1007static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) 932static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) {
1008{
1009 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(setend_inst)); 933 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(setend_inst));
1010 setend_inst* const inst_cream = (setend_inst*)inst_base->component; 934 setend_inst* const inst_cream = (setend_inst*)inst_base->component;
1011 935
1012 inst_base->cond = AL; 936 inst_base->cond = AL;
1013 inst_base->idx = index; 937 inst_base->idx = index;
1014 inst_base->br = TransExtData::NON_BRANCH; 938 inst_base->br = TransExtData::NON_BRANCH;
1015 939
1016 inst_cream->set_bigend = BIT(inst, 9); 940 inst_cream->set_bigend = BIT(inst, 9);
1017 941
1018 return inst_base; 942 return inst_base;
1019} 943}
1020 944
1021static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index) 945static ARM_INST_PTR INTERPRETER_TRANSLATE(sev)(unsigned int inst, int index) {
1022{
1023 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); 946 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
1024 947
1025 inst_base->cond = BITS(inst, 28, 31); 948 inst_base->cond = BITS(inst, 28, 31);
1026 inst_base->idx = index; 949 inst_base->idx = index;
1027 inst_base->br = TransExtData::NON_BRANCH; 950 inst_base->br = TransExtData::NON_BRANCH;
1028 951
1029 return inst_base; 952 return inst_base;
1030} 953}
1031 954
1032static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) 955static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) {
1033{
1034 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 956 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1035 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 957 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
1036 958
1037 inst_base->cond = BITS(inst, 28, 31); 959 inst_base->cond = BITS(inst, 28, 31);
1038 inst_base->idx = index; 960 inst_base->idx = index;
1039 inst_base->br = TransExtData::NON_BRANCH; 961 inst_base->br = TransExtData::NON_BRANCH;
1040 962
1041 inst_cream->op1 = BITS(inst, 20, 21); 963 inst_cream->op1 = BITS(inst, 20, 21);
1042 inst_cream->op2 = BITS(inst, 5, 7); 964 inst_cream->op2 = BITS(inst, 5, 7);
1043 inst_cream->Rm = BITS(inst, 0, 3); 965 inst_cream->Rm = BITS(inst, 0, 3);
1044 inst_cream->Rn = BITS(inst, 16, 19); 966 inst_cream->Rn = BITS(inst, 16, 19);
1045 inst_cream->Rd = BITS(inst, 12, 15); 967 inst_cream->Rd = BITS(inst, 12, 15);
1046 968
1047 return inst_base; 969 return inst_base;
1048} 970}
1049static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) 971static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd16)(unsigned int inst, int index) {
1050{
1051 return INTERPRETER_TRANSLATE(shadd8)(inst, index); 972 return INTERPRETER_TRANSLATE(shadd8)(inst, index);
1052} 973}
1053static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) 974static ARM_INST_PTR INTERPRETER_TRANSLATE(shaddsubx)(unsigned int inst, int index) {
1054{
1055 return INTERPRETER_TRANSLATE(shadd8)(inst, index); 975 return INTERPRETER_TRANSLATE(shadd8)(inst, index);
1056} 976}
1057static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) 977static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub8)(unsigned int inst, int index) {
1058{
1059 return INTERPRETER_TRANSLATE(shadd8)(inst, index); 978 return INTERPRETER_TRANSLATE(shadd8)(inst, index);
1060} 979}
1061static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) 980static ARM_INST_PTR INTERPRETER_TRANSLATE(shsub16)(unsigned int inst, int index) {
1062{
1063 return INTERPRETER_TRANSLATE(shadd8)(inst, index); 981 return INTERPRETER_TRANSLATE(shadd8)(inst, index);
1064} 982}
1065static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) 983static ARM_INST_PTR INTERPRETER_TRANSLATE(shsubaddx)(unsigned int inst, int index) {
1066{
1067 return INTERPRETER_TRANSLATE(shadd8)(inst, index); 984 return INTERPRETER_TRANSLATE(shadd8)(inst, index);
1068} 985}
1069 986
1070static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) 987static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index) {
1071{ 988 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst));
1072 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smla_inst)); 989 smla_inst* inst_cream = (smla_inst*)inst_base->component;
1073 smla_inst *inst_cream = (smla_inst *)inst_base->component;
1074 990
1075 inst_base->cond = BITS(inst, 28, 31); 991 inst_base->cond = BITS(inst, 28, 31);
1076 inst_base->idx = index; 992 inst_base->idx = index;
1077 inst_base->br = TransExtData::NON_BRANCH; 993 inst_base->br = TransExtData::NON_BRANCH;
1078 994
1079 inst_cream->x = BIT(inst, 5); 995 inst_cream->x = BIT(inst, 5);
1080 inst_cream->y = BIT(inst, 6); 996 inst_cream->y = BIT(inst, 6);
1081 inst_cream->Rm = BITS(inst, 0, 3); 997 inst_cream->Rm = BITS(inst, 0, 3);
1082 inst_cream->Rs = BITS(inst, 8, 11); 998 inst_cream->Rs = BITS(inst, 8, 11);
1083 inst_cream->Rd = BITS(inst, 16, 19); 999 inst_cream->Rd = BITS(inst, 16, 19);
@@ -1086,192 +1002,176 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smla)(unsigned int inst, int index)
1086 return inst_base; 1002 return inst_base;
1087} 1003}
1088 1004
1089static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) 1005static ARM_INST_PTR INTERPRETER_TRANSLATE(smlad)(unsigned int inst, int index) {
1090{
1091 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); 1006 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
1092 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; 1007 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
1093 1008
1094 inst_base->cond = BITS(inst, 28, 31); 1009 inst_base->cond = BITS(inst, 28, 31);
1095 inst_base->idx = index; 1010 inst_base->idx = index;
1096 inst_base->br = TransExtData::NON_BRANCH; 1011 inst_base->br = TransExtData::NON_BRANCH;
1097 1012
1098 inst_cream->m = BIT(inst, 5); 1013 inst_cream->m = BIT(inst, 5);
1099 inst_cream->Rn = BITS(inst, 0, 3); 1014 inst_cream->Rn = BITS(inst, 0, 3);
1100 inst_cream->Rm = BITS(inst, 8, 11); 1015 inst_cream->Rm = BITS(inst, 8, 11);
1101 inst_cream->Rd = BITS(inst, 16, 19); 1016 inst_cream->Rd = BITS(inst, 16, 19);
1102 inst_cream->Ra = BITS(inst, 12, 15); 1017 inst_cream->Ra = BITS(inst, 12, 15);
1103 inst_cream->op1 = BITS(inst, 20, 22); 1018 inst_cream->op1 = BITS(inst, 20, 22);
1104 inst_cream->op2 = BITS(inst, 5, 7); 1019 inst_cream->op2 = BITS(inst, 5, 7);
1105 1020
1106 return inst_base; 1021 return inst_base;
1107} 1022}
1108static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) 1023static ARM_INST_PTR INTERPRETER_TRANSLATE(smuad)(unsigned int inst, int index) {
1109{
1110 return INTERPRETER_TRANSLATE(smlad)(inst, index); 1024 return INTERPRETER_TRANSLATE(smlad)(inst, index);
1111} 1025}
1112static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) 1026static ARM_INST_PTR INTERPRETER_TRANSLATE(smusd)(unsigned int inst, int index) {
1113{
1114 return INTERPRETER_TRANSLATE(smlad)(inst, index); 1027 return INTERPRETER_TRANSLATE(smlad)(inst, index);
1115} 1028}
1116static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) 1029static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsd)(unsigned int inst, int index) {
1117{
1118 return INTERPRETER_TRANSLATE(smlad)(inst, index); 1030 return INTERPRETER_TRANSLATE(smlad)(inst, index);
1119} 1031}
1120 1032
1121static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) 1033static ARM_INST_PTR INTERPRETER_TRANSLATE(smlal)(unsigned int inst, int index) {
1122{ 1034 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst));
1123 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); 1035 umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
1124 umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
1125 1036
1126 inst_base->cond = BITS(inst, 28, 31); 1037 inst_base->cond = BITS(inst, 28, 31);
1127 inst_base->idx = index; 1038 inst_base->idx = index;
1128 inst_base->br = TransExtData::NON_BRANCH; 1039 inst_base->br = TransExtData::NON_BRANCH;
1129 1040
1130 inst_cream->S = BIT(inst, 20); 1041 inst_cream->S = BIT(inst, 20);
1131 inst_cream->Rm = BITS(inst, 0, 3); 1042 inst_cream->Rm = BITS(inst, 0, 3);
1132 inst_cream->Rs = BITS(inst, 8, 11); 1043 inst_cream->Rs = BITS(inst, 8, 11);
1133 inst_cream->RdHi = BITS(inst, 16, 19); 1044 inst_cream->RdHi = BITS(inst, 16, 19);
1134 inst_cream->RdLo = BITS(inst, 12, 15); 1045 inst_cream->RdLo = BITS(inst, 12, 15);
1135 1046
1136 return inst_base; 1047 return inst_base;
1137} 1048}
1138 1049
1139static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) 1050static ARM_INST_PTR INTERPRETER_TRANSLATE(smlalxy)(unsigned int inst, int index) {
1140{
1141 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst)); 1051 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlalxy_inst));
1142 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component; 1052 smlalxy_inst* const inst_cream = (smlalxy_inst*)inst_base->component;
1143 1053
1144 inst_base->cond = BITS(inst, 28, 31); 1054 inst_base->cond = BITS(inst, 28, 31);
1145 inst_base->idx = index; 1055 inst_base->idx = index;
1146 inst_base->br = TransExtData::NON_BRANCH; 1056 inst_base->br = TransExtData::NON_BRANCH;
1147 1057
1148 inst_cream->x = BIT(inst, 5); 1058 inst_cream->x = BIT(inst, 5);
1149 inst_cream->y = BIT(inst, 6); 1059 inst_cream->y = BIT(inst, 6);
1150 inst_cream->RdLo = BITS(inst, 12, 15); 1060 inst_cream->RdLo = BITS(inst, 12, 15);
1151 inst_cream->RdHi = BITS(inst, 16, 19); 1061 inst_cream->RdHi = BITS(inst, 16, 19);
1152 inst_cream->Rn = BITS(inst, 0, 4); 1062 inst_cream->Rn = BITS(inst, 0, 4);
1153 inst_cream->Rm = BITS(inst, 8, 11); 1063 inst_cream->Rm = BITS(inst, 8, 11);
1154 1064
1155 return inst_base; 1065 return inst_base;
1156} 1066}
1157 1067
1158static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) 1068static ARM_INST_PTR INTERPRETER_TRANSLATE(smlaw)(unsigned int inst, int index) {
1159{
1160 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); 1069 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
1161 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; 1070 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
1162 1071
1163 inst_base->cond = BITS(inst, 28, 31); 1072 inst_base->cond = BITS(inst, 28, 31);
1164 inst_base->idx = index; 1073 inst_base->idx = index;
1165 inst_base->br = TransExtData::NON_BRANCH; 1074 inst_base->br = TransExtData::NON_BRANCH;
1166 1075
1167 inst_cream->Ra = BITS(inst, 12, 15); 1076 inst_cream->Ra = BITS(inst, 12, 15);
1168 inst_cream->Rm = BITS(inst, 8, 11); 1077 inst_cream->Rm = BITS(inst, 8, 11);
1169 inst_cream->Rn = BITS(inst, 0, 3); 1078 inst_cream->Rn = BITS(inst, 0, 3);
1170 inst_cream->Rd = BITS(inst, 16, 19); 1079 inst_cream->Rd = BITS(inst, 16, 19);
1171 inst_cream->m = BIT(inst, 6); 1080 inst_cream->m = BIT(inst, 6);
1172 1081
1173 return inst_base; 1082 return inst_base;
1174} 1083}
1175 1084
1176static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) 1085static ARM_INST_PTR INTERPRETER_TRANSLATE(smlald)(unsigned int inst, int index) {
1177{
1178 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlald_inst)); 1086 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlald_inst));
1179 smlald_inst* const inst_cream = (smlald_inst*)inst_base->component; 1087 smlald_inst* const inst_cream = (smlald_inst*)inst_base->component;
1180 1088
1181 inst_base->cond = BITS(inst, 28, 31); 1089 inst_base->cond = BITS(inst, 28, 31);
1182 inst_base->idx = index; 1090 inst_base->idx = index;
1183 inst_base->br = TransExtData::NON_BRANCH; 1091 inst_base->br = TransExtData::NON_BRANCH;
1184 1092
1185 inst_cream->Rm = BITS(inst, 8, 11); 1093 inst_cream->Rm = BITS(inst, 8, 11);
1186 inst_cream->Rn = BITS(inst, 0, 3); 1094 inst_cream->Rn = BITS(inst, 0, 3);
1187 inst_cream->RdLo = BITS(inst, 12, 15); 1095 inst_cream->RdLo = BITS(inst, 12, 15);
1188 inst_cream->RdHi = BITS(inst, 16, 19); 1096 inst_cream->RdHi = BITS(inst, 16, 19);
1189 inst_cream->swap = BIT(inst, 5); 1097 inst_cream->swap = BIT(inst, 5);
1190 inst_cream->op1 = BITS(inst, 20, 22); 1098 inst_cream->op1 = BITS(inst, 20, 22);
1191 inst_cream->op2 = BITS(inst, 5, 7); 1099 inst_cream->op2 = BITS(inst, 5, 7);
1192 1100
1193 return inst_base; 1101 return inst_base;
1194} 1102}
1195static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) 1103static ARM_INST_PTR INTERPRETER_TRANSLATE(smlsld)(unsigned int inst, int index) {
1196{
1197 return INTERPRETER_TRANSLATE(smlald)(inst, index); 1104 return INTERPRETER_TRANSLATE(smlald)(inst, index);
1198} 1105}
1199 1106
1200static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) 1107static ARM_INST_PTR INTERPRETER_TRANSLATE(smmla)(unsigned int inst, int index) {
1201{
1202 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); 1108 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
1203 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; 1109 smlad_inst* const inst_cream = (smlad_inst*)inst_base->component;
1204 1110
1205 inst_base->cond = BITS(inst, 28, 31); 1111 inst_base->cond = BITS(inst, 28, 31);
1206 inst_base->idx = index; 1112 inst_base->idx = index;
1207 inst_base->br = TransExtData::NON_BRANCH; 1113 inst_base->br = TransExtData::NON_BRANCH;
1208 1114
1209 inst_cream->m = BIT(inst, 5); 1115 inst_cream->m = BIT(inst, 5);
1210 inst_cream->Ra = BITS(inst, 12, 15); 1116 inst_cream->Ra = BITS(inst, 12, 15);
1211 inst_cream->Rm = BITS(inst, 8, 11); 1117 inst_cream->Rm = BITS(inst, 8, 11);
1212 inst_cream->Rn = BITS(inst, 0, 3); 1118 inst_cream->Rn = BITS(inst, 0, 3);
1213 inst_cream->Rd = BITS(inst, 16, 19); 1119 inst_cream->Rd = BITS(inst, 16, 19);
1214 inst_cream->op1 = BITS(inst, 20, 22); 1120 inst_cream->op1 = BITS(inst, 20, 22);
1215 inst_cream->op2 = BITS(inst, 5, 7); 1121 inst_cream->op2 = BITS(inst, 5, 7);
1216 1122
1217 return inst_base; 1123 return inst_base;
1218} 1124}
1219static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) 1125static ARM_INST_PTR INTERPRETER_TRANSLATE(smmls)(unsigned int inst, int index) {
1220{
1221 return INTERPRETER_TRANSLATE(smmla)(inst, index); 1126 return INTERPRETER_TRANSLATE(smmla)(inst, index);
1222} 1127}
1223static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) 1128static ARM_INST_PTR INTERPRETER_TRANSLATE(smmul)(unsigned int inst, int index) {
1224{
1225 return INTERPRETER_TRANSLATE(smmla)(inst, index); 1129 return INTERPRETER_TRANSLATE(smmla)(inst, index);
1226} 1130}
1227 1131
1228static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) 1132static ARM_INST_PTR INTERPRETER_TRANSLATE(smul)(unsigned int inst, int index) {
1229{ 1133 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst));
1230 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smul_inst)); 1134 smul_inst* inst_cream = (smul_inst*)inst_base->component;
1231 smul_inst *inst_cream = (smul_inst *)inst_base->component;
1232 1135
1233 inst_base->cond = BITS(inst, 28, 31); 1136 inst_base->cond = BITS(inst, 28, 31);
1234 inst_base->idx = index; 1137 inst_base->idx = index;
1235 inst_base->br = TransExtData::NON_BRANCH; 1138 inst_base->br = TransExtData::NON_BRANCH;
1236 1139
1237 inst_cream->Rd = BITS(inst, 16, 19); 1140 inst_cream->Rd = BITS(inst, 16, 19);
1238 inst_cream->Rs = BITS(inst, 8, 11); 1141 inst_cream->Rs = BITS(inst, 8, 11);
1239 inst_cream->Rm = BITS(inst, 0, 3); 1142 inst_cream->Rm = BITS(inst, 0, 3);
1240 1143
1241 inst_cream->x = BIT(inst, 5); 1144 inst_cream->x = BIT(inst, 5);
1242 inst_cream->y = BIT(inst, 6); 1145 inst_cream->y = BIT(inst, 6);
1243 1146
1244 return inst_base; 1147 return inst_base;
1245
1246} 1148}
1247static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) 1149static ARM_INST_PTR INTERPRETER_TRANSLATE(smull)(unsigned int inst, int index) {
1248{ 1150 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst));
1249 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); 1151 umull_inst* inst_cream = (umull_inst*)inst_base->component;
1250 umull_inst *inst_cream = (umull_inst *)inst_base->component;
1251 1152
1252 inst_base->cond = BITS(inst, 28, 31); 1153 inst_base->cond = BITS(inst, 28, 31);
1253 inst_base->idx = index; 1154 inst_base->idx = index;
1254 inst_base->br = TransExtData::NON_BRANCH; 1155 inst_base->br = TransExtData::NON_BRANCH;
1255 1156
1256 inst_cream->S = BIT(inst, 20); 1157 inst_cream->S = BIT(inst, 20);
1257 inst_cream->Rm = BITS(inst, 0, 3); 1158 inst_cream->Rm = BITS(inst, 0, 3);
1258 inst_cream->Rs = BITS(inst, 8, 11); 1159 inst_cream->Rs = BITS(inst, 8, 11);
1259 inst_cream->RdHi = BITS(inst, 16, 19); 1160 inst_cream->RdHi = BITS(inst, 16, 19);
1260 inst_cream->RdLo = BITS(inst, 12, 15); 1161 inst_cream->RdLo = BITS(inst, 12, 15);
1261 1162
1262 return inst_base; 1163 return inst_base;
1263} 1164}
1264 1165
1265static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) 1166static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index) {
1266{ 1167 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst));
1267 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(smlad_inst)); 1168 smlad_inst* inst_cream = (smlad_inst*)inst_base->component;
1268 smlad_inst *inst_cream = (smlad_inst *)inst_base->component;
1269 1169
1270 inst_base->cond = BITS(inst, 28, 31); 1170 inst_base->cond = BITS(inst, 28, 31);
1271 inst_base->idx = index; 1171 inst_base->idx = index;
1272 inst_base->br = TransExtData::NON_BRANCH; 1172 inst_base->br = TransExtData::NON_BRANCH;
1273 1173
1274 inst_cream->m = BIT(inst, 6); 1174 inst_cream->m = BIT(inst, 6);
1275 inst_cream->Rm = BITS(inst, 8, 11); 1175 inst_cream->Rm = BITS(inst, 8, 11);
1276 inst_cream->Rn = BITS(inst, 0, 3); 1176 inst_cream->Rn = BITS(inst, 0, 3);
1277 inst_cream->Rd = BITS(inst, 16, 19); 1177 inst_cream->Rd = BITS(inst, 16, 19);
@@ -1279,29 +1179,27 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
1279 return inst_base; 1179 return inst_base;
1280} 1180}
1281 1181
1282static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) 1182static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) {
1283{
1284 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1183 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1285 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component; 1184 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
1286 1185
1287 inst_base->cond = AL; 1186 inst_base->cond = AL;
1288 inst_base->idx = index; 1187 inst_base->idx = index;
1289 inst_base->br = TransExtData::NON_BRANCH; 1188 inst_base->br = TransExtData::NON_BRANCH;
1290 1189
1291 inst_cream->inst = inst; 1190 inst_cream->inst = inst;
1292 inst_cream->get_addr = GetAddressingOp(inst); 1191 inst_cream->get_addr = GetAddressingOp(inst);
1293 1192
1294 return inst_base; 1193 return inst_base;
1295} 1194}
1296 1195
1297static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) 1196static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) {
1298{
1299 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); 1197 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
1300 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; 1198 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
1301 1199
1302 inst_base->cond = BITS(inst, 28, 31); 1200 inst_base->cond = BITS(inst, 28, 31);
1303 inst_base->idx = index; 1201 inst_base->idx = index;
1304 inst_base->br = TransExtData::NON_BRANCH; 1202 inst_base->br = TransExtData::NON_BRANCH;
1305 1203
1306 inst_cream->Rn = BITS(inst, 0, 3); 1204 inst_cream->Rn = BITS(inst, 0, 3);
1307 inst_cream->Rd = BITS(inst, 12, 15); 1205 inst_cream->Rd = BITS(inst, 12, 15);
@@ -1311,211 +1209,195 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
1311 1209
1312 return inst_base; 1210 return inst_base;
1313} 1211}
1314static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) 1212static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat16)(unsigned int inst, int index) {
1315{
1316 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); 1213 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
1317 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component; 1214 ssat_inst* const inst_cream = (ssat_inst*)inst_base->component;
1318 1215
1319 inst_base->cond = BITS(inst, 28, 31); 1216 inst_base->cond = BITS(inst, 28, 31);
1320 inst_base->idx = index; 1217 inst_base->idx = index;
1321 inst_base->br = TransExtData::NON_BRANCH; 1218 inst_base->br = TransExtData::NON_BRANCH;
1322 1219
1323 inst_cream->Rn = BITS(inst, 0, 3); 1220 inst_cream->Rn = BITS(inst, 0, 3);
1324 inst_cream->Rd = BITS(inst, 12, 15); 1221 inst_cream->Rd = BITS(inst, 12, 15);
1325 inst_cream->sat_imm = BITS(inst, 16, 19); 1222 inst_cream->sat_imm = BITS(inst, 16, 19);
1326 1223
1327 return inst_base; 1224 return inst_base;
1328} 1225}
1329 1226
1330static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) 1227static ARM_INST_PTR INTERPRETER_TRANSLATE(stc)(unsigned int inst, int index) {
1331{ 1228 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst));
1332 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(stc_inst));
1333 inst_base->cond = BITS(inst, 28, 31); 1229 inst_base->cond = BITS(inst, 28, 31);
1334 inst_base->idx = index; 1230 inst_base->idx = index;
1335 inst_base->br = TransExtData::NON_BRANCH; 1231 inst_base->br = TransExtData::NON_BRANCH;
1336 1232
1337 return inst_base; 1233 return inst_base;
1338} 1234}
1339static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) 1235static ARM_INST_PTR INTERPRETER_TRANSLATE(stm)(unsigned int inst, int index) {
1340{ 1236 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1341 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1237 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1342 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
1343 1238
1344 inst_base->cond = BITS(inst, 28, 31); 1239 inst_base->cond = BITS(inst, 28, 31);
1345 inst_base->idx = index; 1240 inst_base->idx = index;
1346 inst_base->br = TransExtData::NON_BRANCH; 1241 inst_base->br = TransExtData::NON_BRANCH;
1347 1242
1348 inst_cream->inst = inst; 1243 inst_cream->inst = inst;
1349 inst_cream->get_addr = GetAddressingOp(inst); 1244 inst_cream->get_addr = GetAddressingOp(inst);
1350 return inst_base; 1245 return inst_base;
1351} 1246}
1352static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) 1247static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb)(unsigned int inst, int index) {
1353{ 1248 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst));
1354 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtb_inst)); 1249 sxtb_inst* inst_cream = (sxtb_inst*)inst_base->component;
1355 sxtb_inst *inst_cream = (sxtb_inst *)inst_base->component;
1356 1250
1357 inst_base->cond = BITS(inst, 28, 31); 1251 inst_base->cond = BITS(inst, 28, 31);
1358 inst_base->idx = index; 1252 inst_base->idx = index;
1359 inst_base->br = TransExtData::NON_BRANCH; 1253 inst_base->br = TransExtData::NON_BRANCH;
1360 1254
1361 inst_cream->Rd = BITS(inst, 12, 15); 1255 inst_cream->Rd = BITS(inst, 12, 15);
1362 inst_cream->Rm = BITS(inst, 0, 3); 1256 inst_cream->Rm = BITS(inst, 0, 3);
1363 inst_cream->rotate = BITS(inst, 10, 11); 1257 inst_cream->rotate = BITS(inst, 10, 11);
1364 1258
1365 return inst_base; 1259 return inst_base;
1366} 1260}
1367static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) 1261static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) {
1368{ 1262 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1369 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1263 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1370 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
1371 1264
1372 inst_base->cond = BITS(inst, 28, 31); 1265 inst_base->cond = BITS(inst, 28, 31);
1373 inst_base->idx = index; 1266 inst_base->idx = index;
1374 inst_base->br = TransExtData::NON_BRANCH; 1267 inst_base->br = TransExtData::NON_BRANCH;
1375 1268
1376 inst_cream->inst = inst; 1269 inst_cream->inst = inst;
1377 inst_cream->get_addr = GetAddressingOp(inst); 1270 inst_cream->get_addr = GetAddressingOp(inst);
1378 1271
1379 return inst_base; 1272 return inst_base;
1380} 1273}
1381static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) 1274static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) {
1382{ 1275 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst));
1383 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxth_inst)); 1276 uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
1384 uxth_inst *inst_cream = (uxth_inst *)inst_base->component;
1385 1277
1386 inst_base->cond = BITS(inst, 28, 31); 1278 inst_base->cond = BITS(inst, 28, 31);
1387 inst_base->idx = index; 1279 inst_base->idx = index;
1388 inst_base->br = TransExtData::NON_BRANCH; 1280 inst_base->br = TransExtData::NON_BRANCH;
1389 1281
1390 inst_cream->Rd = BITS(inst, 12, 15); 1282 inst_cream->Rd = BITS(inst, 12, 15);
1391 inst_cream->rotate = BITS(inst, 10, 11); 1283 inst_cream->rotate = BITS(inst, 10, 11);
1392 inst_cream->Rm = BITS(inst, 0, 3); 1284 inst_cream->Rm = BITS(inst, 0, 3);
1393 1285
1394 return inst_base; 1286 return inst_base;
1395} 1287}
1396static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) 1288static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab)(unsigned int inst, int index) {
1397{ 1289 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst));
1398 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); 1290 uxtab_inst* inst_cream = (uxtab_inst*)inst_base->component;
1399 uxtab_inst *inst_cream = (uxtab_inst *)inst_base->component;
1400 1291
1401 inst_base->cond = BITS(inst, 28, 31); 1292 inst_base->cond = BITS(inst, 28, 31);
1402 inst_base->idx = index; 1293 inst_base->idx = index;
1403 inst_base->br = TransExtData::NON_BRANCH; 1294 inst_base->br = TransExtData::NON_BRANCH;
1404 1295
1405 inst_cream->Rd = BITS(inst, 12, 15); 1296 inst_cream->Rd = BITS(inst, 12, 15);
1406 inst_cream->rotate = BITS(inst, 10, 11); 1297 inst_cream->rotate = BITS(inst, 10, 11);
1407 inst_cream->Rm = BITS(inst, 0, 3); 1298 inst_cream->Rm = BITS(inst, 0, 3);
1408 inst_cream->Rn = BITS(inst, 16, 19); 1299 inst_cream->Rn = BITS(inst, 16, 19);
1409 1300
1410 return inst_base; 1301 return inst_base;
1411} 1302}
1412static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) 1303static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) {
1413{ 1304 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1414 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1305 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1415 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
1416 1306
1417 inst_base->cond = BITS(inst, 28, 31); 1307 inst_base->cond = BITS(inst, 28, 31);
1418 inst_base->idx = index; 1308 inst_base->idx = index;
1419 inst_base->br = TransExtData::NON_BRANCH; 1309 inst_base->br = TransExtData::NON_BRANCH;
1420 1310
1421 inst_cream->inst = inst; 1311 inst_cream->inst = inst;
1422 inst_cream->get_addr = GetAddressingOp(inst); 1312 inst_cream->get_addr = GetAddressingOp(inst);
1423 1313
1424 return inst_base; 1314 return inst_base;
1425} 1315}
1426static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) 1316static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) {
1427{
1428 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1317 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1429 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 1318 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1430 1319
1431 inst_base->cond = BITS(inst, 28, 31); 1320 inst_base->cond = BITS(inst, 28, 31);
1432 inst_base->idx = index; 1321 inst_base->idx = index;
1433 inst_base->br = TransExtData::NON_BRANCH; 1322 inst_base->br = TransExtData::NON_BRANCH;
1434 1323
1435 inst_cream->inst = inst; 1324 inst_cream->inst = inst;
1436 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); 1325 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
1437 1326
1438 return inst_base; 1327 return inst_base;
1439} 1328}
1440static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ 1329static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index) {
1441 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1330 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1442 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 1331 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1443 1332
1444 inst_base->cond = BITS(inst, 28, 31); 1333 inst_base->cond = BITS(inst, 28, 31);
1445 inst_base->idx = index; 1334 inst_base->idx = index;
1446 inst_base->br = TransExtData::NON_BRANCH; 1335 inst_base->br = TransExtData::NON_BRANCH;
1447 1336
1448 inst_cream->inst = inst; 1337 inst_cream->inst = inst;
1449 inst_cream->get_addr = GetAddressingOp(inst); 1338 inst_cream->get_addr = GetAddressingOp(inst);
1450 1339
1451 return inst_base; 1340 return inst_base;
1452} 1341}
1453static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) 1342static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) {
1454{ 1343 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1455 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 1344 generic_arm_inst* inst_cream = (generic_arm_inst*)inst_base->component;
1456 generic_arm_inst *inst_cream = (generic_arm_inst *)inst_base->component;
1457 1345
1458 inst_base->cond = BITS(inst, 28, 31); 1346 inst_base->cond = BITS(inst, 28, 31);
1459 inst_base->idx = index; 1347 inst_base->idx = index;
1460 inst_base->br = TransExtData::NON_BRANCH; 1348 inst_base->br = TransExtData::NON_BRANCH;
1461 1349
1462 inst_cream->Rn = BITS(inst, 16, 19); 1350 inst_cream->Rn = BITS(inst, 16, 19);
1463 inst_cream->Rd = BITS(inst, 12, 15); 1351 inst_cream->Rd = BITS(inst, 12, 15);
1464 inst_cream->Rm = BITS(inst, 0, 3); 1352 inst_cream->Rm = BITS(inst, 0, 3);
1465 1353
1466 return inst_base; 1354 return inst_base;
1467} 1355}
1468static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) 1356static ARM_INST_PTR INTERPRETER_TRANSLATE(strexb)(unsigned int inst, int index) {
1469{
1470 return INTERPRETER_TRANSLATE(strex)(inst, index); 1357 return INTERPRETER_TRANSLATE(strex)(inst, index);
1471} 1358}
1472static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) 1359static ARM_INST_PTR INTERPRETER_TRANSLATE(strexh)(unsigned int inst, int index) {
1473{
1474 return INTERPRETER_TRANSLATE(strex)(inst, index); 1360 return INTERPRETER_TRANSLATE(strex)(inst, index);
1475} 1361}
1476static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) 1362static ARM_INST_PTR INTERPRETER_TRANSLATE(strexd)(unsigned int inst, int index) {
1477{
1478 return INTERPRETER_TRANSLATE(strex)(inst, index); 1363 return INTERPRETER_TRANSLATE(strex)(inst, index);
1479} 1364}
1480static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) 1365static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) {
1481{ 1366 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1482 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1367 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1483 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
1484 1368
1485 inst_base->cond = BITS(inst, 28, 31); 1369 inst_base->cond = BITS(inst, 28, 31);
1486 inst_base->idx = index; 1370 inst_base->idx = index;
1487 inst_base->br = TransExtData::NON_BRANCH; 1371 inst_base->br = TransExtData::NON_BRANCH;
1488 1372
1489 inst_cream->inst = inst; 1373 inst_cream->inst = inst;
1490 inst_cream->get_addr = GetAddressingOp(inst); 1374 inst_cream->get_addr = GetAddressingOp(inst);
1491 1375
1492 return inst_base; 1376 return inst_base;
1493} 1377}
1494static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) 1378static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) {
1495{
1496 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst)); 1379 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
1497 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 1380 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
1498 1381
1499 inst_base->cond = BITS(inst, 28, 31); 1382 inst_base->cond = BITS(inst, 28, 31);
1500 inst_base->idx = index; 1383 inst_base->idx = index;
1501 inst_base->br = TransExtData::NON_BRANCH; 1384 inst_base->br = TransExtData::NON_BRANCH;
1502 1385
1503 inst_cream->inst = inst; 1386 inst_cream->inst = inst;
1504 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); 1387 inst_cream->get_addr = GetAddressingOpLoadStoreT(inst);
1505 1388
1506 return inst_base; 1389 return inst_base;
1507} 1390}
1508static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) 1391static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) {
1509{ 1392 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst));
1510 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sub_inst)); 1393 sub_inst* inst_cream = (sub_inst*)inst_base->component;
1511 sub_inst *inst_cream = (sub_inst *)inst_base->component;
1512 1394
1513 inst_base->cond = BITS(inst, 28, 31); 1395 inst_base->cond = BITS(inst, 28, 31);
1514 inst_base->idx = index; 1396 inst_base->idx = index;
1515 inst_base->br = TransExtData::NON_BRANCH; 1397 inst_base->br = TransExtData::NON_BRANCH;
1516 1398
1517 inst_cream->I = BIT(inst, 25); 1399 inst_cream->I = BIT(inst, 25);
1518 inst_cream->S = BIT(inst, 20); 1400 inst_cream->S = BIT(inst, 20);
1519 inst_cream->Rn = BITS(inst, 16, 19); 1401 inst_cream->Rn = BITS(inst, 16, 19);
1520 inst_cream->Rd = BITS(inst, 12, 15); 1402 inst_cream->Rd = BITS(inst, 12, 15);
1521 inst_cream->shifter_operand = BITS(inst, 0, 11); 1403 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -1526,71 +1408,68 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index)
1526 1408
1527 return inst_base; 1409 return inst_base;
1528} 1410}
1529static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) 1411static ARM_INST_PTR INTERPRETER_TRANSLATE(swi)(unsigned int inst, int index) {
1530{ 1412 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst));
1531 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swi_inst)); 1413 swi_inst* inst_cream = (swi_inst*)inst_base->component;
1532 swi_inst *inst_cream = (swi_inst *)inst_base->component;
1533 1414
1534 inst_base->cond = BITS(inst, 28, 31); 1415 inst_base->cond = BITS(inst, 28, 31);
1535 inst_base->idx = index; 1416 inst_base->idx = index;
1536 inst_base->br = TransExtData::NON_BRANCH; 1417 inst_base->br = TransExtData::NON_BRANCH;
1537 1418
1538 inst_cream->num = BITS(inst, 0, 23); 1419 inst_cream->num = BITS(inst, 0, 23);
1539 return inst_base; 1420 return inst_base;
1540} 1421}
1541static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) 1422static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) {
1542{ 1423 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst));
1543 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); 1424 swp_inst* inst_cream = (swp_inst*)inst_base->component;
1544 swp_inst *inst_cream = (swp_inst *)inst_base->component;
1545 1425
1546 inst_base->cond = BITS(inst, 28, 31); 1426 inst_base->cond = BITS(inst, 28, 31);
1547 inst_base->idx = index; 1427 inst_base->idx = index;
1548 inst_base->br = TransExtData::NON_BRANCH; 1428 inst_base->br = TransExtData::NON_BRANCH;
1549 1429
1550 inst_cream->Rn = BITS(inst, 16, 19); 1430 inst_cream->Rn = BITS(inst, 16, 19);
1551 inst_cream->Rd = BITS(inst, 12, 15); 1431 inst_cream->Rd = BITS(inst, 12, 15);
1552 inst_cream->Rm = BITS(inst, 0, 3); 1432 inst_cream->Rm = BITS(inst, 0, 3);
1553 1433
1554 return inst_base; 1434 return inst_base;
1555} 1435}
1556static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ 1436static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index) {
1557 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst)); 1437 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(swp_inst));
1558 swp_inst *inst_cream = (swp_inst *)inst_base->component; 1438 swp_inst* inst_cream = (swp_inst*)inst_base->component;
1559 1439
1560 inst_base->cond = BITS(inst, 28, 31); 1440 inst_base->cond = BITS(inst, 28, 31);
1561 inst_base->idx = index; 1441 inst_base->idx = index;
1562 inst_base->br = TransExtData::NON_BRANCH; 1442 inst_base->br = TransExtData::NON_BRANCH;
1563 1443
1564 inst_cream->Rn = BITS(inst, 16, 19); 1444 inst_cream->Rn = BITS(inst, 16, 19);
1565 inst_cream->Rd = BITS(inst, 12, 15); 1445 inst_cream->Rd = BITS(inst, 12, 15);
1566 inst_cream->Rm = BITS(inst, 0, 3); 1446 inst_cream->Rm = BITS(inst, 0, 3);
1567 1447
1568 return inst_base; 1448 return inst_base;
1569} 1449}
1570static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ 1450static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index) {
1571 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); 1451 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst));
1572 sxtab_inst *inst_cream = (sxtab_inst *)inst_base->component; 1452 sxtab_inst* inst_cream = (sxtab_inst*)inst_base->component;
1573 1453
1574 inst_base->cond = BITS(inst, 28, 31); 1454 inst_base->cond = BITS(inst, 28, 31);
1575 inst_base->idx = index; 1455 inst_base->idx = index;
1576 inst_base->br = TransExtData::NON_BRANCH; 1456 inst_base->br = TransExtData::NON_BRANCH;
1577 1457
1578 inst_cream->Rd = BITS(inst, 12, 15); 1458 inst_cream->Rd = BITS(inst, 12, 15);
1579 inst_cream->rotate = BITS(inst, 10, 11); 1459 inst_cream->rotate = BITS(inst, 10, 11);
1580 inst_cream->Rm = BITS(inst, 0, 3); 1460 inst_cream->Rm = BITS(inst, 0, 3);
1581 inst_cream->Rn = BITS(inst, 16, 19); 1461 inst_cream->Rn = BITS(inst, 16, 19);
1582 1462
1583 return inst_base; 1463 return inst_base;
1584} 1464}
1585 1465
1586static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) 1466static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index) {
1587{
1588 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst)); 1467 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtab_inst));
1589 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component; 1468 sxtab_inst* const inst_cream = (sxtab_inst*)inst_base->component;
1590 1469
1591 inst_base->cond = BITS(inst, 28, 31); 1470 inst_base->cond = BITS(inst, 28, 31);
1592 inst_base->idx = index; 1471 inst_base->idx = index;
1593 inst_base->br = TransExtData::NON_BRANCH; 1472 inst_base->br = TransExtData::NON_BRANCH;
1594 1473
1595 inst_cream->Rm = BITS(inst, 0, 3); 1474 inst_cream->Rm = BITS(inst, 0, 3);
1596 inst_cream->Rn = BITS(inst, 16, 19); 1475 inst_cream->Rn = BITS(inst, 16, 19);
@@ -1599,54 +1478,51 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab16)(unsigned int inst, int index)
1599 1478
1600 return inst_base; 1479 return inst_base;
1601} 1480}
1602static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) 1481static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtb16)(unsigned int inst, int index) {
1603{
1604 return INTERPRETER_TRANSLATE(sxtab16)(inst, index); 1482 return INTERPRETER_TRANSLATE(sxtab16)(inst, index);
1605} 1483}
1606 1484
1607static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index) { 1485static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtah)(unsigned int inst, int index) {
1608 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst)); 1486 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(sxtah_inst));
1609 sxtah_inst *inst_cream = (sxtah_inst *)inst_base->component; 1487 sxtah_inst* inst_cream = (sxtah_inst*)inst_base->component;
1610 1488
1611 inst_base->cond = BITS(inst, 28, 31); 1489 inst_base->cond = BITS(inst, 28, 31);
1612 inst_base->idx = index; 1490 inst_base->idx = index;
1613 inst_base->br = TransExtData::NON_BRANCH; 1491 inst_base->br = TransExtData::NON_BRANCH;
1614 1492
1615 inst_cream->Rd = BITS(inst, 12, 15); 1493 inst_cream->Rd = BITS(inst, 12, 15);
1616 inst_cream->rotate = BITS(inst, 10, 11); 1494 inst_cream->rotate = BITS(inst, 10, 11);
1617 inst_cream->Rm = BITS(inst, 0, 3); 1495 inst_cream->Rm = BITS(inst, 0, 3);
1618 inst_cream->Rn = BITS(inst, 16, 19); 1496 inst_cream->Rn = BITS(inst, 16, 19);
1619 1497
1620 return inst_base; 1498 return inst_base;
1621} 1499}
1622 1500
1623static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) 1501static ARM_INST_PTR INTERPRETER_TRANSLATE(teq)(unsigned int inst, int index) {
1624{ 1502 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst));
1625 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(teq_inst)); 1503 teq_inst* inst_cream = (teq_inst*)inst_base->component;
1626 teq_inst *inst_cream = (teq_inst *)inst_base->component;
1627 1504
1628 inst_base->cond = BITS(inst, 28, 31); 1505 inst_base->cond = BITS(inst, 28, 31);
1629 inst_base->idx = index; 1506 inst_base->idx = index;
1630 inst_base->br = TransExtData::NON_BRANCH; 1507 inst_base->br = TransExtData::NON_BRANCH;
1631 1508
1632 inst_cream->I = BIT(inst, 25); 1509 inst_cream->I = BIT(inst, 25);
1633 inst_cream->Rn = BITS(inst, 16, 19); 1510 inst_cream->Rn = BITS(inst, 16, 19);
1634 inst_cream->shifter_operand = BITS(inst, 0, 11); 1511 inst_cream->shifter_operand = BITS(inst, 0, 11);
1635 inst_cream->shtop_func = GetShifterOp(inst); 1512 inst_cream->shtop_func = GetShifterOp(inst);
1636 1513
1637 return inst_base; 1514 return inst_base;
1638} 1515}
1639static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) 1516static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) {
1640{ 1517 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst));
1641 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(tst_inst)); 1518 tst_inst* inst_cream = (tst_inst*)inst_base->component;
1642 tst_inst *inst_cream = (tst_inst *)inst_base->component;
1643 1519
1644 inst_base->cond = BITS(inst, 28, 31); 1520 inst_base->cond = BITS(inst, 28, 31);
1645 inst_base->idx = index; 1521 inst_base->idx = index;
1646 inst_base->br = TransExtData::NON_BRANCH; 1522 inst_base->br = TransExtData::NON_BRANCH;
1647 1523
1648 inst_cream->I = BIT(inst, 25); 1524 inst_cream->I = BIT(inst, 25);
1649 inst_cream->S = BIT(inst, 20); 1525 inst_cream->S = BIT(inst, 20);
1650 inst_cream->Rn = BITS(inst, 16, 19); 1526 inst_cream->Rn = BITS(inst, 16, 19);
1651 inst_cream->Rd = BITS(inst, 12, 15); 1527 inst_cream->Rd = BITS(inst, 12, 15);
1652 inst_cream->shifter_operand = BITS(inst, 0, 11); 1528 inst_cream->shifter_operand = BITS(inst, 0, 11);
@@ -1655,309 +1531,274 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index)
1655 return inst_base; 1531 return inst_base;
1656} 1532}
1657 1533
1658static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) 1534static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd8)(unsigned int inst, int index) {
1659{
1660 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 1535 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1661 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 1536 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
1662 1537
1663 inst_base->cond = BITS(inst, 28, 31); 1538 inst_base->cond = BITS(inst, 28, 31);
1664 inst_base->idx = index; 1539 inst_base->idx = index;
1665 inst_base->br = TransExtData::NON_BRANCH; 1540 inst_base->br = TransExtData::NON_BRANCH;
1666 1541
1667 inst_cream->op1 = BITS(inst, 20, 21); 1542 inst_cream->op1 = BITS(inst, 20, 21);
1668 inst_cream->op2 = BITS(inst, 5, 7); 1543 inst_cream->op2 = BITS(inst, 5, 7);
1669 inst_cream->Rm = BITS(inst, 0, 3); 1544 inst_cream->Rm = BITS(inst, 0, 3);
1670 inst_cream->Rn = BITS(inst, 16, 19); 1545 inst_cream->Rn = BITS(inst, 16, 19);
1671 inst_cream->Rd = BITS(inst, 12, 15); 1546 inst_cream->Rd = BITS(inst, 12, 15);
1672 1547
1673 return inst_base; 1548 return inst_base;
1674} 1549}
1675static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) 1550static ARM_INST_PTR INTERPRETER_TRANSLATE(uadd16)(unsigned int inst, int index) {
1676{
1677 return INTERPRETER_TRANSLATE(uadd8)(inst, index); 1551 return INTERPRETER_TRANSLATE(uadd8)(inst, index);
1678} 1552}
1679static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) 1553static ARM_INST_PTR INTERPRETER_TRANSLATE(uaddsubx)(unsigned int inst, int index) {
1680{
1681 return INTERPRETER_TRANSLATE(uadd8)(inst, index); 1554 return INTERPRETER_TRANSLATE(uadd8)(inst, index);
1682} 1555}
1683static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) 1556static ARM_INST_PTR INTERPRETER_TRANSLATE(usub8)(unsigned int inst, int index) {
1684{
1685 return INTERPRETER_TRANSLATE(uadd8)(inst, index); 1557 return INTERPRETER_TRANSLATE(uadd8)(inst, index);
1686} 1558}
1687static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) 1559static ARM_INST_PTR INTERPRETER_TRANSLATE(usub16)(unsigned int inst, int index) {
1688{
1689 return INTERPRETER_TRANSLATE(uadd8)(inst, index); 1560 return INTERPRETER_TRANSLATE(uadd8)(inst, index);
1690} 1561}
1691static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) 1562static ARM_INST_PTR INTERPRETER_TRANSLATE(usubaddx)(unsigned int inst, int index) {
1692{
1693 return INTERPRETER_TRANSLATE(uadd8)(inst, index); 1563 return INTERPRETER_TRANSLATE(uadd8)(inst, index);
1694} 1564}
1695 1565
1696static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) 1566static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd8)(unsigned int inst, int index) {
1697{
1698 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 1567 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1699 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 1568 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
1700 1569
1701 inst_base->cond = BITS(inst, 28, 31); 1570 inst_base->cond = BITS(inst, 28, 31);
1702 inst_base->idx = index; 1571 inst_base->idx = index;
1703 inst_base->br = TransExtData::NON_BRANCH; 1572 inst_base->br = TransExtData::NON_BRANCH;
1704 1573
1705 inst_cream->op1 = BITS(inst, 20, 21); 1574 inst_cream->op1 = BITS(inst, 20, 21);
1706 inst_cream->op2 = BITS(inst, 5, 7); 1575 inst_cream->op2 = BITS(inst, 5, 7);
1707 inst_cream->Rm = BITS(inst, 0, 3); 1576 inst_cream->Rm = BITS(inst, 0, 3);
1708 inst_cream->Rn = BITS(inst, 16, 19); 1577 inst_cream->Rn = BITS(inst, 16, 19);
1709 inst_cream->Rd = BITS(inst, 12, 15); 1578 inst_cream->Rd = BITS(inst, 12, 15);
1710 1579
1711 return inst_base; 1580 return inst_base;
1712} 1581}
1713static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) 1582static ARM_INST_PTR INTERPRETER_TRANSLATE(uhadd16)(unsigned int inst, int index) {
1714{
1715 return INTERPRETER_TRANSLATE(uhadd8)(inst, index); 1583 return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
1716} 1584}
1717static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) 1585static ARM_INST_PTR INTERPRETER_TRANSLATE(uhaddsubx)(unsigned int inst, int index) {
1718{
1719 return INTERPRETER_TRANSLATE(uhadd8)(inst, index); 1586 return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
1720} 1587}
1721static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) 1588static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub8)(unsigned int inst, int index) {
1722{
1723 return INTERPRETER_TRANSLATE(uhadd8)(inst, index); 1589 return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
1724} 1590}
1725static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) 1591static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsub16)(unsigned int inst, int index) {
1726{
1727 return INTERPRETER_TRANSLATE(uhadd8)(inst, index); 1592 return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
1728} 1593}
1729static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) 1594static ARM_INST_PTR INTERPRETER_TRANSLATE(uhsubaddx)(unsigned int inst, int index) {
1730{
1731 return INTERPRETER_TRANSLATE(uhadd8)(inst, index); 1595 return INTERPRETER_TRANSLATE(uhadd8)(inst, index);
1732} 1596}
1733static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) 1597static ARM_INST_PTR INTERPRETER_TRANSLATE(umaal)(unsigned int inst, int index) {
1734{
1735 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umaal_inst)); 1598 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umaal_inst));
1736 umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; 1599 umaal_inst* const inst_cream = (umaal_inst*)inst_base->component;
1737 1600
1738 inst_base->cond = BITS(inst, 28, 31); 1601 inst_base->cond = BITS(inst, 28, 31);
1739 inst_base->idx = index; 1602 inst_base->idx = index;
1740 inst_base->br = TransExtData::NON_BRANCH; 1603 inst_base->br = TransExtData::NON_BRANCH;
1741 1604
1742 inst_cream->Rm = BITS(inst, 8, 11); 1605 inst_cream->Rm = BITS(inst, 8, 11);
1743 inst_cream->Rn = BITS(inst, 0, 3); 1606 inst_cream->Rn = BITS(inst, 0, 3);
1744 inst_cream->RdLo = BITS(inst, 12, 15); 1607 inst_cream->RdLo = BITS(inst, 12, 15);
1745 inst_cream->RdHi = BITS(inst, 16, 19); 1608 inst_cream->RdHi = BITS(inst, 16, 19);
1746 1609
1747 return inst_base; 1610 return inst_base;
1748} 1611}
1749static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) 1612static ARM_INST_PTR INTERPRETER_TRANSLATE(umlal)(unsigned int inst, int index) {
1750{ 1613 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst));
1751 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umlal_inst)); 1614 umlal_inst* inst_cream = (umlal_inst*)inst_base->component;
1752 umlal_inst *inst_cream = (umlal_inst *)inst_base->component;
1753 1615
1754 inst_base->cond = BITS(inst, 28, 31); 1616 inst_base->cond = BITS(inst, 28, 31);
1755 inst_base->idx = index; 1617 inst_base->idx = index;
1756 inst_base->br = TransExtData::NON_BRANCH; 1618 inst_base->br = TransExtData::NON_BRANCH;
1757 1619
1758 inst_cream->S = BIT(inst, 20); 1620 inst_cream->S = BIT(inst, 20);
1759 inst_cream->Rm = BITS(inst, 0, 3); 1621 inst_cream->Rm = BITS(inst, 0, 3);
1760 inst_cream->Rs = BITS(inst, 8, 11); 1622 inst_cream->Rs = BITS(inst, 8, 11);
1761 inst_cream->RdHi = BITS(inst, 16, 19); 1623 inst_cream->RdHi = BITS(inst, 16, 19);
1762 inst_cream->RdLo = BITS(inst, 12, 15); 1624 inst_cream->RdLo = BITS(inst, 12, 15);
1763 1625
1764 return inst_base; 1626 return inst_base;
1765} 1627}
1766static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) 1628static ARM_INST_PTR INTERPRETER_TRANSLATE(umull)(unsigned int inst, int index) {
1767{ 1629 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst));
1768 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(umull_inst)); 1630 umull_inst* inst_cream = (umull_inst*)inst_base->component;
1769 umull_inst *inst_cream = (umull_inst *)inst_base->component;
1770 1631
1771 inst_base->cond = BITS(inst, 28, 31); 1632 inst_base->cond = BITS(inst, 28, 31);
1772 inst_base->idx = index; 1633 inst_base->idx = index;
1773 inst_base->br = TransExtData::NON_BRANCH; 1634 inst_base->br = TransExtData::NON_BRANCH;
1774 1635
1775 inst_cream->S = BIT(inst, 20); 1636 inst_cream->S = BIT(inst, 20);
1776 inst_cream->Rm = BITS(inst, 0, 3); 1637 inst_cream->Rm = BITS(inst, 0, 3);
1777 inst_cream->Rs = BITS(inst, 8, 11); 1638 inst_cream->Rs = BITS(inst, 8, 11);
1778 inst_cream->RdHi = BITS(inst, 16, 19); 1639 inst_cream->RdHi = BITS(inst, 16, 19);
1779 inst_cream->RdLo = BITS(inst, 12, 15); 1640 inst_cream->RdLo = BITS(inst, 12, 15);
1780 1641
1781 return inst_base; 1642 return inst_base;
1782} 1643}
1783 1644
1784static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) 1645static ARM_INST_PTR INTERPRETER_TRANSLATE(b_2_thumb)(unsigned int tinst, int index) {
1785{ 1646 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb));
1786 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_2_thumb)); 1647 b_2_thumb* inst_cream = (b_2_thumb*)inst_base->component;
1787 b_2_thumb *inst_cream = (b_2_thumb *)inst_base->component;
1788 1648
1789 inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0); 1649 inst_cream->imm = ((tinst & 0x3FF) << 1) | ((tinst & (1 << 10)) ? 0xFFFFF800 : 0);
1790 1650
1791 inst_base->idx = index; 1651 inst_base->idx = index;
1792 inst_base->br = TransExtData::DIRECT_BRANCH; 1652 inst_base->br = TransExtData::DIRECT_BRANCH;
1793 1653
1794 return inst_base; 1654 return inst_base;
1795} 1655}
1796 1656
1797static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) 1657static ARM_INST_PTR INTERPRETER_TRANSLATE(b_cond_thumb)(unsigned int tinst, int index) {
1798{ 1658 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb));
1799 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(b_cond_thumb)); 1659 b_cond_thumb* inst_cream = (b_cond_thumb*)inst_base->component;
1800 b_cond_thumb *inst_cream = (b_cond_thumb *)inst_base->component;
1801 1660
1802 inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0)); 1661 inst_cream->imm = (((tinst & 0x7F) << 1) | ((tinst & (1 << 7)) ? 0xFFFFFF00 : 0));
1803 inst_cream->cond = ((tinst >> 8) & 0xf); 1662 inst_cream->cond = ((tinst >> 8) & 0xf);
1804 inst_base->idx = index; 1663 inst_base->idx = index;
1805 inst_base->br = TransExtData::DIRECT_BRANCH; 1664 inst_base->br = TransExtData::DIRECT_BRANCH;
1806 1665
1807 return inst_base; 1666 return inst_base;
1808} 1667}
1809 1668
1810static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) 1669static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_1_thumb)(unsigned int tinst, int index) {
1811{ 1670 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb));
1812 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_1_thumb)); 1671 bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component;
1813 bl_1_thumb *inst_cream = (bl_1_thumb *)inst_base->component;
1814 1672
1815 inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0)); 1673 inst_cream->imm = (((tinst & 0x07FF) << 12) | ((tinst & (1 << 10)) ? 0xFF800000 : 0));
1816 1674
1817 inst_base->idx = index; 1675 inst_base->idx = index;
1818 inst_base->br = TransExtData::NON_BRANCH; 1676 inst_base->br = TransExtData::NON_BRANCH;
1819 return inst_base; 1677 return inst_base;
1820} 1678}
1821static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) 1679static ARM_INST_PTR INTERPRETER_TRANSLATE(bl_2_thumb)(unsigned int tinst, int index) {
1822{ 1680 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb));
1823 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(bl_2_thumb)); 1681 bl_2_thumb* inst_cream = (bl_2_thumb*)inst_base->component;
1824 bl_2_thumb *inst_cream = (bl_2_thumb *)inst_base->component;
1825 1682
1826 inst_cream->imm = (tinst & 0x07FF) << 1; 1683 inst_cream->imm = (tinst & 0x07FF) << 1;
1827 1684
1828 inst_base->idx = index; 1685 inst_base->idx = index;
1829 inst_base->br = TransExtData::DIRECT_BRANCH; 1686 inst_base->br = TransExtData::DIRECT_BRANCH;
1830 return inst_base; 1687 return inst_base;
1831} 1688}
1832static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) 1689static ARM_INST_PTR INTERPRETER_TRANSLATE(blx_1_thumb)(unsigned int tinst, int index) {
1833{ 1690 arm_inst* inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb));
1834 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_1_thumb)); 1691 blx_1_thumb* inst_cream = (blx_1_thumb*)inst_base->component;
1835 blx_1_thumb *inst_cream = (blx_1_thumb *)inst_base->component;
1836 1692
1837 inst_cream->imm = (tinst & 0x07FF) << 1; 1693 inst_cream->imm = (tinst & 0x07FF) << 1;
1838 inst_cream->instr = tinst; 1694 inst_cream->instr = tinst;
1839 1695
1840 inst_base->idx = index; 1696 inst_base->idx = index;
1841 inst_base->br = TransExtData::DIRECT_BRANCH; 1697 inst_base->br = TransExtData::DIRECT_BRANCH;
1842 return inst_base; 1698 return inst_base;
1843} 1699}
1844 1700
1845static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) 1701static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd8)(unsigned int inst, int index) {
1846{
1847 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 1702 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1848 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 1703 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
1849 1704
1850 inst_base->cond = BITS(inst, 28, 31); 1705 inst_base->cond = BITS(inst, 28, 31);
1851 inst_base->idx = index; 1706 inst_base->idx = index;
1852 inst_base->br = TransExtData::NON_BRANCH; 1707 inst_base->br = TransExtData::NON_BRANCH;
1853 1708
1854 inst_cream->Rm = BITS(inst, 0, 3); 1709 inst_cream->Rm = BITS(inst, 0, 3);
1855 inst_cream->Rn = BITS(inst, 16, 19); 1710 inst_cream->Rn = BITS(inst, 16, 19);
1856 inst_cream->Rd = BITS(inst, 12, 15); 1711 inst_cream->Rd = BITS(inst, 12, 15);
1857 inst_cream->op1 = BITS(inst, 20, 21); 1712 inst_cream->op1 = BITS(inst, 20, 21);
1858 inst_cream->op2 = BITS(inst, 5, 7); 1713 inst_cream->op2 = BITS(inst, 5, 7);
1859 1714
1860 return inst_base; 1715 return inst_base;
1861} 1716}
1862static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) 1717static ARM_INST_PTR INTERPRETER_TRANSLATE(uqadd16)(unsigned int inst, int index) {
1863{
1864 return INTERPRETER_TRANSLATE(uqadd8)(inst, index); 1718 return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
1865} 1719}
1866static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) 1720static ARM_INST_PTR INTERPRETER_TRANSLATE(uqaddsubx)(unsigned int inst, int index) {
1867{
1868 return INTERPRETER_TRANSLATE(uqadd8)(inst, index); 1721 return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
1869} 1722}
1870static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) 1723static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub8)(unsigned int inst, int index) {
1871{
1872 return INTERPRETER_TRANSLATE(uqadd8)(inst, index); 1724 return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
1873} 1725}
1874static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) 1726static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsub16)(unsigned int inst, int index) {
1875{
1876 return INTERPRETER_TRANSLATE(uqadd8)(inst, index); 1727 return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
1877} 1728}
1878static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) 1729static ARM_INST_PTR INTERPRETER_TRANSLATE(uqsubaddx)(unsigned int inst, int index) {
1879{
1880 return INTERPRETER_TRANSLATE(uqadd8)(inst, index); 1730 return INTERPRETER_TRANSLATE(uqadd8)(inst, index);
1881} 1731}
1882static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) 1732static ARM_INST_PTR INTERPRETER_TRANSLATE(usada8)(unsigned int inst, int index) {
1883{
1884 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst)); 1733 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
1885 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component; 1734 generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
1886 1735
1887 inst_base->cond = BITS(inst, 28, 31); 1736 inst_base->cond = BITS(inst, 28, 31);
1888 inst_base->idx = index; 1737 inst_base->idx = index;
1889 inst_base->br = TransExtData::NON_BRANCH; 1738 inst_base->br = TransExtData::NON_BRANCH;
1890 1739
1891 inst_cream->op1 = BITS(inst, 20, 24); 1740 inst_cream->op1 = BITS(inst, 20, 24);
1892 inst_cream->op2 = BITS(inst, 5, 7); 1741 inst_cream->op2 = BITS(inst, 5, 7);
1893 inst_cream->Rd = BITS(inst, 16, 19); 1742 inst_cream->Rd = BITS(inst, 16, 19);
1894 inst_cream->Rm = BITS(inst, 8, 11); 1743 inst_cream->Rm = BITS(inst, 8, 11);
1895 inst_cream->Rn = BITS(inst, 0, 3); 1744 inst_cream->Rn = BITS(inst, 0, 3);
1896 inst_cream->Ra = BITS(inst, 12, 15); 1745 inst_cream->Ra = BITS(inst, 12, 15);
1897 1746
1898 return inst_base; 1747 return inst_base;
1899} 1748}
1900static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) 1749static ARM_INST_PTR INTERPRETER_TRANSLATE(usad8)(unsigned int inst, int index) {
1901{
1902 return INTERPRETER_TRANSLATE(usada8)(inst, index); 1750 return INTERPRETER_TRANSLATE(usada8)(inst, index);
1903} 1751}
1904static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) 1752static ARM_INST_PTR INTERPRETER_TRANSLATE(usat)(unsigned int inst, int index) {
1905{
1906 return INTERPRETER_TRANSLATE(ssat)(inst, index); 1753 return INTERPRETER_TRANSLATE(ssat)(inst, index);
1907} 1754}
1908static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) 1755static ARM_INST_PTR INTERPRETER_TRANSLATE(usat16)(unsigned int inst, int index) {
1909{
1910 return INTERPRETER_TRANSLATE(ssat16)(inst, index); 1756 return INTERPRETER_TRANSLATE(ssat16)(inst, index);
1911} 1757}
1912 1758
1913static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) 1759static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtab16)(unsigned int inst, int index) {
1914{
1915 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst)); 1760 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(uxtab_inst));
1916 uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component; 1761 uxtab_inst* const inst_cream = (uxtab_inst*)inst_base->component;
1917 1762
1918 inst_base->cond = BITS(inst, 28, 31); 1763 inst_base->cond = BITS(inst, 28, 31);
1919 inst_base->idx = index; 1764 inst_base->idx = index;
1920 inst_base->br = TransExtData::NON_BRANCH; 1765 inst_base->br = TransExtData::NON_BRANCH;
1921 1766
1922 inst_cream->Rm = BITS(inst, 0, 3); 1767 inst_cream->Rm = BITS(inst, 0, 3);
1923 inst_cream->Rn = BITS(inst, 16, 19); 1768 inst_cream->Rn = BITS(inst, 16, 19);
1924 inst_cream->Rd = BITS(inst, 12, 15); 1769 inst_cream->Rd = BITS(inst, 12, 15);
1925 inst_cream->rotate = BITS(inst, 10, 11); 1770 inst_cream->rotate = BITS(inst, 10, 11);
1926 1771
1927 return inst_base; 1772 return inst_base;
1928} 1773}
1929static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) 1774static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) {
1930{
1931 return INTERPRETER_TRANSLATE(uxtab16)(inst, index); 1775 return INTERPRETER_TRANSLATE(uxtab16)(inst, index);
1932} 1776}
1933 1777
1934static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index) 1778static ARM_INST_PTR INTERPRETER_TRANSLATE(wfe)(unsigned int inst, int index) {
1935{
1936 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); 1779 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
1937 1780
1938 inst_base->cond = BITS(inst, 28, 31); 1781 inst_base->cond = BITS(inst, 28, 31);
1939 inst_base->idx = index; 1782 inst_base->idx = index;
1940 inst_base->br = TransExtData::NON_BRANCH; 1783 inst_base->br = TransExtData::NON_BRANCH;
1941 1784
1942 return inst_base; 1785 return inst_base;
1943} 1786}
1944static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index) 1787static ARM_INST_PTR INTERPRETER_TRANSLATE(wfi)(unsigned int inst, int index) {
1945{
1946 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); 1788 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
1947 1789
1948 inst_base->cond = BITS(inst, 28, 31); 1790 inst_base->cond = BITS(inst, 28, 31);
1949 inst_base->idx = index; 1791 inst_base->idx = index;
1950 inst_base->br = TransExtData::NON_BRANCH; 1792 inst_base->br = TransExtData::NON_BRANCH;
1951 1793
1952 return inst_base; 1794 return inst_base;
1953} 1795}
1954static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index) 1796static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index) {
1955{
1956 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst)); 1797 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst));
1957 1798
1958 inst_base->cond = BITS(inst, 28, 31); 1799 inst_base->cond = BITS(inst, 28, 31);
1959 inst_base->idx = index; 1800 inst_base->idx = index;
1960 inst_base->br = TransExtData::NON_BRANCH; 1801 inst_base->br = TransExtData::NON_BRANCH;
1961 1802
1962 return inst_base; 1803 return inst_base;
1963} 1804}
@@ -1968,211 +1809,79 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(yield)(unsigned int inst, int index)
1968#undef VFP_INTERPRETER_TRANS 1809#undef VFP_INTERPRETER_TRANS
1969 1810
1970const transop_fp_t arm_instruction_trans[] = { 1811const transop_fp_t arm_instruction_trans[] = {
1971 INTERPRETER_TRANSLATE(vmla), 1812 INTERPRETER_TRANSLATE(vmla), INTERPRETER_TRANSLATE(vmls), INTERPRETER_TRANSLATE(vnmla),
1972 INTERPRETER_TRANSLATE(vmls), 1813 INTERPRETER_TRANSLATE(vnmls), INTERPRETER_TRANSLATE(vnmul), INTERPRETER_TRANSLATE(vmul),
1973 INTERPRETER_TRANSLATE(vnmla), 1814 INTERPRETER_TRANSLATE(vadd), INTERPRETER_TRANSLATE(vsub), INTERPRETER_TRANSLATE(vdiv),
1974 INTERPRETER_TRANSLATE(vnmls), 1815 INTERPRETER_TRANSLATE(vmovi), INTERPRETER_TRANSLATE(vmovr), INTERPRETER_TRANSLATE(vabs),
1975 INTERPRETER_TRANSLATE(vnmul), 1816 INTERPRETER_TRANSLATE(vneg), INTERPRETER_TRANSLATE(vsqrt), INTERPRETER_TRANSLATE(vcmp),
1976 INTERPRETER_TRANSLATE(vmul), 1817 INTERPRETER_TRANSLATE(vcmp2), INTERPRETER_TRANSLATE(vcvtbds), INTERPRETER_TRANSLATE(vcvtbff),
1977 INTERPRETER_TRANSLATE(vadd), 1818 INTERPRETER_TRANSLATE(vcvtbfi), INTERPRETER_TRANSLATE(vmovbrs), INTERPRETER_TRANSLATE(vmsr),
1978 INTERPRETER_TRANSLATE(vsub), 1819 INTERPRETER_TRANSLATE(vmovbrc), INTERPRETER_TRANSLATE(vmrs), INTERPRETER_TRANSLATE(vmovbcr),
1979 INTERPRETER_TRANSLATE(vdiv), 1820 INTERPRETER_TRANSLATE(vmovbrrss), INTERPRETER_TRANSLATE(vmovbrrd), INTERPRETER_TRANSLATE(vstr),
1980 INTERPRETER_TRANSLATE(vmovi), 1821 INTERPRETER_TRANSLATE(vpush), INTERPRETER_TRANSLATE(vstm), INTERPRETER_TRANSLATE(vpop),
1981 INTERPRETER_TRANSLATE(vmovr), 1822 INTERPRETER_TRANSLATE(vldr), INTERPRETER_TRANSLATE(vldm),
1982 INTERPRETER_TRANSLATE(vabs), 1823
1983 INTERPRETER_TRANSLATE(vneg), 1824 INTERPRETER_TRANSLATE(srs), INTERPRETER_TRANSLATE(rfe), INTERPRETER_TRANSLATE(bkpt),
1984 INTERPRETER_TRANSLATE(vsqrt), 1825 INTERPRETER_TRANSLATE(blx), INTERPRETER_TRANSLATE(cps), INTERPRETER_TRANSLATE(pld),
1985 INTERPRETER_TRANSLATE(vcmp), 1826 INTERPRETER_TRANSLATE(setend), INTERPRETER_TRANSLATE(clrex), INTERPRETER_TRANSLATE(rev16),
1986 INTERPRETER_TRANSLATE(vcmp2), 1827 INTERPRETER_TRANSLATE(usad8), INTERPRETER_TRANSLATE(sxtb), INTERPRETER_TRANSLATE(uxtb),
1987 INTERPRETER_TRANSLATE(vcvtbds), 1828 INTERPRETER_TRANSLATE(sxth), INTERPRETER_TRANSLATE(sxtb16), INTERPRETER_TRANSLATE(uxth),
1988 INTERPRETER_TRANSLATE(vcvtbff), 1829 INTERPRETER_TRANSLATE(uxtb16), INTERPRETER_TRANSLATE(cpy), INTERPRETER_TRANSLATE(uxtab),
1989 INTERPRETER_TRANSLATE(vcvtbfi), 1830 INTERPRETER_TRANSLATE(ssub8), INTERPRETER_TRANSLATE(shsub8), INTERPRETER_TRANSLATE(ssubaddx),
1990 INTERPRETER_TRANSLATE(vmovbrs), 1831 INTERPRETER_TRANSLATE(strex), INTERPRETER_TRANSLATE(strexb), INTERPRETER_TRANSLATE(swp),
1991 INTERPRETER_TRANSLATE(vmsr), 1832 INTERPRETER_TRANSLATE(swpb), INTERPRETER_TRANSLATE(ssub16), INTERPRETER_TRANSLATE(ssat16),
1992 INTERPRETER_TRANSLATE(vmovbrc), 1833 INTERPRETER_TRANSLATE(shsubaddx), INTERPRETER_TRANSLATE(qsubaddx),
1993 INTERPRETER_TRANSLATE(vmrs), 1834 INTERPRETER_TRANSLATE(shaddsubx), INTERPRETER_TRANSLATE(shadd8), INTERPRETER_TRANSLATE(shadd16),
1994 INTERPRETER_TRANSLATE(vmovbcr), 1835 INTERPRETER_TRANSLATE(sel), INTERPRETER_TRANSLATE(saddsubx), INTERPRETER_TRANSLATE(sadd8),
1995 INTERPRETER_TRANSLATE(vmovbrrss), 1836 INTERPRETER_TRANSLATE(sadd16), INTERPRETER_TRANSLATE(shsub16), INTERPRETER_TRANSLATE(umaal),
1996 INTERPRETER_TRANSLATE(vmovbrrd), 1837 INTERPRETER_TRANSLATE(uxtab16), INTERPRETER_TRANSLATE(usubaddx), INTERPRETER_TRANSLATE(usub8),
1997 INTERPRETER_TRANSLATE(vstr), 1838 INTERPRETER_TRANSLATE(usub16), INTERPRETER_TRANSLATE(usat16), INTERPRETER_TRANSLATE(usada8),
1998 INTERPRETER_TRANSLATE(vpush), 1839 INTERPRETER_TRANSLATE(uqsubaddx), INTERPRETER_TRANSLATE(uqsub8), INTERPRETER_TRANSLATE(uqsub16),
1999 INTERPRETER_TRANSLATE(vstm), 1840 INTERPRETER_TRANSLATE(uqaddsubx), INTERPRETER_TRANSLATE(uqadd8), INTERPRETER_TRANSLATE(uqadd16),
2000 INTERPRETER_TRANSLATE(vpop), 1841 INTERPRETER_TRANSLATE(sxtab), INTERPRETER_TRANSLATE(uhsubaddx), INTERPRETER_TRANSLATE(uhsub8),
2001 INTERPRETER_TRANSLATE(vldr), 1842 INTERPRETER_TRANSLATE(uhsub16), INTERPRETER_TRANSLATE(uhaddsubx), INTERPRETER_TRANSLATE(uhadd8),
2002 INTERPRETER_TRANSLATE(vldm), 1843 INTERPRETER_TRANSLATE(uhadd16), INTERPRETER_TRANSLATE(uaddsubx), INTERPRETER_TRANSLATE(uadd8),
2003 1844 INTERPRETER_TRANSLATE(uadd16), INTERPRETER_TRANSLATE(sxtah), INTERPRETER_TRANSLATE(sxtab16),
2004 INTERPRETER_TRANSLATE(srs), 1845 INTERPRETER_TRANSLATE(qadd8), INTERPRETER_TRANSLATE(bxj), INTERPRETER_TRANSLATE(clz),
2005 INTERPRETER_TRANSLATE(rfe), 1846 INTERPRETER_TRANSLATE(uxtah), INTERPRETER_TRANSLATE(bx), INTERPRETER_TRANSLATE(rev),
2006 INTERPRETER_TRANSLATE(bkpt), 1847 INTERPRETER_TRANSLATE(blx), INTERPRETER_TRANSLATE(revsh), INTERPRETER_TRANSLATE(qadd),
2007 INTERPRETER_TRANSLATE(blx), 1848 INTERPRETER_TRANSLATE(qadd16), INTERPRETER_TRANSLATE(qaddsubx), INTERPRETER_TRANSLATE(ldrex),
2008 INTERPRETER_TRANSLATE(cps), 1849 INTERPRETER_TRANSLATE(qdadd), INTERPRETER_TRANSLATE(qdsub), INTERPRETER_TRANSLATE(qsub),
2009 INTERPRETER_TRANSLATE(pld), 1850 INTERPRETER_TRANSLATE(ldrexb), INTERPRETER_TRANSLATE(qsub8), INTERPRETER_TRANSLATE(qsub16),
2010 INTERPRETER_TRANSLATE(setend), 1851 INTERPRETER_TRANSLATE(smuad), INTERPRETER_TRANSLATE(smmul), INTERPRETER_TRANSLATE(smusd),
2011 INTERPRETER_TRANSLATE(clrex), 1852 INTERPRETER_TRANSLATE(smlsd), INTERPRETER_TRANSLATE(smlsld), INTERPRETER_TRANSLATE(smmla),
2012 INTERPRETER_TRANSLATE(rev16), 1853 INTERPRETER_TRANSLATE(smmls), INTERPRETER_TRANSLATE(smlald), INTERPRETER_TRANSLATE(smlad),
2013 INTERPRETER_TRANSLATE(usad8), 1854 INTERPRETER_TRANSLATE(smlaw), INTERPRETER_TRANSLATE(smulw), INTERPRETER_TRANSLATE(pkhtb),
2014 INTERPRETER_TRANSLATE(sxtb), 1855 INTERPRETER_TRANSLATE(pkhbt), INTERPRETER_TRANSLATE(smul), INTERPRETER_TRANSLATE(smlalxy),
2015 INTERPRETER_TRANSLATE(uxtb), 1856 INTERPRETER_TRANSLATE(smla), INTERPRETER_TRANSLATE(mcrr), INTERPRETER_TRANSLATE(mrrc),
2016 INTERPRETER_TRANSLATE(sxth), 1857 INTERPRETER_TRANSLATE(cmp), INTERPRETER_TRANSLATE(tst), INTERPRETER_TRANSLATE(teq),
2017 INTERPRETER_TRANSLATE(sxtb16), 1858 INTERPRETER_TRANSLATE(cmn), INTERPRETER_TRANSLATE(smull), INTERPRETER_TRANSLATE(umull),
2018 INTERPRETER_TRANSLATE(uxth), 1859 INTERPRETER_TRANSLATE(umlal), INTERPRETER_TRANSLATE(smlal), INTERPRETER_TRANSLATE(mul),
2019 INTERPRETER_TRANSLATE(uxtb16), 1860 INTERPRETER_TRANSLATE(mla), INTERPRETER_TRANSLATE(ssat), INTERPRETER_TRANSLATE(usat),
2020 INTERPRETER_TRANSLATE(cpy), 1861 INTERPRETER_TRANSLATE(mrs), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(and),
2021 INTERPRETER_TRANSLATE(uxtab), 1862 INTERPRETER_TRANSLATE(bic), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(eor),
2022 INTERPRETER_TRANSLATE(ssub8), 1863 INTERPRETER_TRANSLATE(add), INTERPRETER_TRANSLATE(rsb), INTERPRETER_TRANSLATE(rsc),
2023 INTERPRETER_TRANSLATE(shsub8), 1864 INTERPRETER_TRANSLATE(sbc), INTERPRETER_TRANSLATE(adc), INTERPRETER_TRANSLATE(sub),
2024 INTERPRETER_TRANSLATE(ssubaddx), 1865 INTERPRETER_TRANSLATE(orr), INTERPRETER_TRANSLATE(mvn), INTERPRETER_TRANSLATE(mov),
2025 INTERPRETER_TRANSLATE(strex), 1866 INTERPRETER_TRANSLATE(stm), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(ldrsh),
2026 INTERPRETER_TRANSLATE(strexb), 1867 INTERPRETER_TRANSLATE(stm), INTERPRETER_TRANSLATE(ldm), INTERPRETER_TRANSLATE(ldrsb),
2027 INTERPRETER_TRANSLATE(swp), 1868 INTERPRETER_TRANSLATE(strd), INTERPRETER_TRANSLATE(ldrh), INTERPRETER_TRANSLATE(strh),
2028 INTERPRETER_TRANSLATE(swpb), 1869 INTERPRETER_TRANSLATE(ldrd), INTERPRETER_TRANSLATE(strt), INTERPRETER_TRANSLATE(strbt),
2029 INTERPRETER_TRANSLATE(ssub16), 1870 INTERPRETER_TRANSLATE(ldrbt), INTERPRETER_TRANSLATE(ldrt), INTERPRETER_TRANSLATE(mrc),
2030 INTERPRETER_TRANSLATE(ssat16), 1871 INTERPRETER_TRANSLATE(mcr), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr),
2031 INTERPRETER_TRANSLATE(shsubaddx), 1872 INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr), INTERPRETER_TRANSLATE(msr),
2032 INTERPRETER_TRANSLATE(qsubaddx), 1873 INTERPRETER_TRANSLATE(ldrb), INTERPRETER_TRANSLATE(strb), INTERPRETER_TRANSLATE(ldr),
2033 INTERPRETER_TRANSLATE(shaddsubx), 1874 INTERPRETER_TRANSLATE(ldrcond), INTERPRETER_TRANSLATE(str), INTERPRETER_TRANSLATE(cdp),
2034 INTERPRETER_TRANSLATE(shadd8), 1875 INTERPRETER_TRANSLATE(stc), INTERPRETER_TRANSLATE(ldc), INTERPRETER_TRANSLATE(ldrexd),
2035 INTERPRETER_TRANSLATE(shadd16), 1876 INTERPRETER_TRANSLATE(strexd), INTERPRETER_TRANSLATE(ldrexh), INTERPRETER_TRANSLATE(strexh),
2036 INTERPRETER_TRANSLATE(sel), 1877 INTERPRETER_TRANSLATE(nop), INTERPRETER_TRANSLATE(yield), INTERPRETER_TRANSLATE(wfe),
2037 INTERPRETER_TRANSLATE(saddsubx), 1878 INTERPRETER_TRANSLATE(wfi), INTERPRETER_TRANSLATE(sev), INTERPRETER_TRANSLATE(swi),
2038 INTERPRETER_TRANSLATE(sadd8),
2039 INTERPRETER_TRANSLATE(sadd16),
2040 INTERPRETER_TRANSLATE(shsub16),
2041 INTERPRETER_TRANSLATE(umaal),
2042 INTERPRETER_TRANSLATE(uxtab16),
2043 INTERPRETER_TRANSLATE(usubaddx),
2044 INTERPRETER_TRANSLATE(usub8),
2045 INTERPRETER_TRANSLATE(usub16),
2046 INTERPRETER_TRANSLATE(usat16),
2047 INTERPRETER_TRANSLATE(usada8),
2048 INTERPRETER_TRANSLATE(uqsubaddx),
2049 INTERPRETER_TRANSLATE(uqsub8),
2050 INTERPRETER_TRANSLATE(uqsub16),
2051 INTERPRETER_TRANSLATE(uqaddsubx),
2052 INTERPRETER_TRANSLATE(uqadd8),
2053 INTERPRETER_TRANSLATE(uqadd16),
2054 INTERPRETER_TRANSLATE(sxtab),
2055 INTERPRETER_TRANSLATE(uhsubaddx),
2056 INTERPRETER_TRANSLATE(uhsub8),
2057 INTERPRETER_TRANSLATE(uhsub16),
2058 INTERPRETER_TRANSLATE(uhaddsubx),
2059 INTERPRETER_TRANSLATE(uhadd8),
2060 INTERPRETER_TRANSLATE(uhadd16),
2061 INTERPRETER_TRANSLATE(uaddsubx),
2062 INTERPRETER_TRANSLATE(uadd8),
2063 INTERPRETER_TRANSLATE(uadd16),
2064 INTERPRETER_TRANSLATE(sxtah),
2065 INTERPRETER_TRANSLATE(sxtab16),
2066 INTERPRETER_TRANSLATE(qadd8),
2067 INTERPRETER_TRANSLATE(bxj),
2068 INTERPRETER_TRANSLATE(clz),
2069 INTERPRETER_TRANSLATE(uxtah),
2070 INTERPRETER_TRANSLATE(bx),
2071 INTERPRETER_TRANSLATE(rev),
2072 INTERPRETER_TRANSLATE(blx),
2073 INTERPRETER_TRANSLATE(revsh),
2074 INTERPRETER_TRANSLATE(qadd),
2075 INTERPRETER_TRANSLATE(qadd16),
2076 INTERPRETER_TRANSLATE(qaddsubx),
2077 INTERPRETER_TRANSLATE(ldrex),
2078 INTERPRETER_TRANSLATE(qdadd),
2079 INTERPRETER_TRANSLATE(qdsub),
2080 INTERPRETER_TRANSLATE(qsub),
2081 INTERPRETER_TRANSLATE(ldrexb),
2082 INTERPRETER_TRANSLATE(qsub8),
2083 INTERPRETER_TRANSLATE(qsub16),
2084 INTERPRETER_TRANSLATE(smuad),
2085 INTERPRETER_TRANSLATE(smmul),
2086 INTERPRETER_TRANSLATE(smusd),
2087 INTERPRETER_TRANSLATE(smlsd),
2088 INTERPRETER_TRANSLATE(smlsld),
2089 INTERPRETER_TRANSLATE(smmla),
2090 INTERPRETER_TRANSLATE(smmls),
2091 INTERPRETER_TRANSLATE(smlald),
2092 INTERPRETER_TRANSLATE(smlad),
2093 INTERPRETER_TRANSLATE(smlaw),
2094 INTERPRETER_TRANSLATE(smulw),
2095 INTERPRETER_TRANSLATE(pkhtb),
2096 INTERPRETER_TRANSLATE(pkhbt),
2097 INTERPRETER_TRANSLATE(smul),
2098 INTERPRETER_TRANSLATE(smlalxy),
2099 INTERPRETER_TRANSLATE(smla),
2100 INTERPRETER_TRANSLATE(mcrr),
2101 INTERPRETER_TRANSLATE(mrrc),
2102 INTERPRETER_TRANSLATE(cmp),
2103 INTERPRETER_TRANSLATE(tst),
2104 INTERPRETER_TRANSLATE(teq),
2105 INTERPRETER_TRANSLATE(cmn),
2106 INTERPRETER_TRANSLATE(smull),
2107 INTERPRETER_TRANSLATE(umull),
2108 INTERPRETER_TRANSLATE(umlal),
2109 INTERPRETER_TRANSLATE(smlal),
2110 INTERPRETER_TRANSLATE(mul),
2111 INTERPRETER_TRANSLATE(mla),
2112 INTERPRETER_TRANSLATE(ssat),
2113 INTERPRETER_TRANSLATE(usat),
2114 INTERPRETER_TRANSLATE(mrs),
2115 INTERPRETER_TRANSLATE(msr),
2116 INTERPRETER_TRANSLATE(and),
2117 INTERPRETER_TRANSLATE(bic),
2118 INTERPRETER_TRANSLATE(ldm),
2119 INTERPRETER_TRANSLATE(eor),
2120 INTERPRETER_TRANSLATE(add),
2121 INTERPRETER_TRANSLATE(rsb),
2122 INTERPRETER_TRANSLATE(rsc),
2123 INTERPRETER_TRANSLATE(sbc),
2124 INTERPRETER_TRANSLATE(adc),
2125 INTERPRETER_TRANSLATE(sub),
2126 INTERPRETER_TRANSLATE(orr),
2127 INTERPRETER_TRANSLATE(mvn),
2128 INTERPRETER_TRANSLATE(mov),
2129 INTERPRETER_TRANSLATE(stm),
2130 INTERPRETER_TRANSLATE(ldm),
2131 INTERPRETER_TRANSLATE(ldrsh),
2132 INTERPRETER_TRANSLATE(stm),
2133 INTERPRETER_TRANSLATE(ldm),
2134 INTERPRETER_TRANSLATE(ldrsb),
2135 INTERPRETER_TRANSLATE(strd),
2136 INTERPRETER_TRANSLATE(ldrh),
2137 INTERPRETER_TRANSLATE(strh),
2138 INTERPRETER_TRANSLATE(ldrd),
2139 INTERPRETER_TRANSLATE(strt),
2140 INTERPRETER_TRANSLATE(strbt),
2141 INTERPRETER_TRANSLATE(ldrbt),
2142 INTERPRETER_TRANSLATE(ldrt),
2143 INTERPRETER_TRANSLATE(mrc),
2144 INTERPRETER_TRANSLATE(mcr),
2145 INTERPRETER_TRANSLATE(msr),
2146 INTERPRETER_TRANSLATE(msr),
2147 INTERPRETER_TRANSLATE(msr),
2148 INTERPRETER_TRANSLATE(msr),
2149 INTERPRETER_TRANSLATE(msr),
2150 INTERPRETER_TRANSLATE(ldrb),
2151 INTERPRETER_TRANSLATE(strb),
2152 INTERPRETER_TRANSLATE(ldr),
2153 INTERPRETER_TRANSLATE(ldrcond),
2154 INTERPRETER_TRANSLATE(str),
2155 INTERPRETER_TRANSLATE(cdp),
2156 INTERPRETER_TRANSLATE(stc),
2157 INTERPRETER_TRANSLATE(ldc),
2158 INTERPRETER_TRANSLATE(ldrexd),
2159 INTERPRETER_TRANSLATE(strexd),
2160 INTERPRETER_TRANSLATE(ldrexh),
2161 INTERPRETER_TRANSLATE(strexh),
2162 INTERPRETER_TRANSLATE(nop),
2163 INTERPRETER_TRANSLATE(yield),
2164 INTERPRETER_TRANSLATE(wfe),
2165 INTERPRETER_TRANSLATE(wfi),
2166 INTERPRETER_TRANSLATE(sev),
2167 INTERPRETER_TRANSLATE(swi),
2168 INTERPRETER_TRANSLATE(bbl), 1879 INTERPRETER_TRANSLATE(bbl),
2169 1880
2170 // All the thumb instructions should be placed the end of table 1881 // All the thumb instructions should be placed the end of table
2171 INTERPRETER_TRANSLATE(b_2_thumb), 1882 INTERPRETER_TRANSLATE(b_2_thumb), INTERPRETER_TRANSLATE(b_cond_thumb),
2172 INTERPRETER_TRANSLATE(b_cond_thumb), 1883 INTERPRETER_TRANSLATE(bl_1_thumb), INTERPRETER_TRANSLATE(bl_2_thumb),
2173 INTERPRETER_TRANSLATE(bl_1_thumb), 1884 INTERPRETER_TRANSLATE(blx_1_thumb),
2174 INTERPRETER_TRANSLATE(bl_2_thumb),
2175 INTERPRETER_TRANSLATE(blx_1_thumb)
2176}; 1885};
2177 1886
2178const size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t); 1887const size_t arm_instruction_trans_len = sizeof(arm_instruction_trans) / sizeof(transop_fp_t);
diff --git a/src/core/arm/dyncom/arm_dyncom_trans.h b/src/core/arm/dyncom/arm_dyncom_trans.h
index 7af71f4e3..b1ec90662 100644
--- a/src/core/arm/dyncom/arm_dyncom_trans.h
+++ b/src/core/arm/dyncom/arm_dyncom_trans.h
@@ -1,16 +1,19 @@
1#include <cstddef>
2#include "common/common_types.h"
3
1struct ARMul_State; 4struct ARMul_State;
2typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper); 5typedef unsigned int (*shtop_fp_t)(ARMul_State* cpu, unsigned int sht_oper);
3 6
4enum class TransExtData { 7enum class TransExtData {
5 COND = (1 << 0), 8 COND = (1 << 0),
6 NON_BRANCH = (1 << 1), 9 NON_BRANCH = (1 << 1),
7 DIRECT_BRANCH = (1 << 2), 10 DIRECT_BRANCH = (1 << 2),
8 INDIRECT_BRANCH = (1 << 3), 11 INDIRECT_BRANCH = (1 << 3),
9 CALL = (1 << 4), 12 CALL = (1 << 4),
10 RET = (1 << 5), 13 RET = (1 << 5),
11 END_OF_PAGE = (1 << 6), 14 END_OF_PAGE = (1 << 6),
12 THUMB = (1 << 7), 15 THUMB = (1 << 7),
13 SINGLE_STEP = (1 << 8) 16 SINGLE_STEP = (1 << 8)
14}; 17};
15 18
16struct arm_inst { 19struct arm_inst {
@@ -106,8 +109,7 @@ struct cps_inst {
106 unsigned int mode; 109 unsigned int mode;
107}; 110};
108 111
109struct clrex_inst { 112struct clrex_inst {};
110};
111 113
112struct cpy_inst { 114struct cpy_inst {
113 unsigned int Rm; 115 unsigned int Rm;
@@ -163,11 +165,9 @@ struct bkpt_inst {
163 u32 imm; 165 u32 imm;
164}; 166};
165 167
166struct stc_inst { 168struct stc_inst {};
167};
168 169
169struct ldc_inst { 170struct ldc_inst {};
170};
171 171
172struct swi_inst { 172struct swi_inst {
173 unsigned int num; 173 unsigned int num;
@@ -369,8 +369,7 @@ struct msr_inst {
369 unsigned int inst; 369 unsigned int inst;
370}; 370};
371 371
372struct pld_inst { 372struct pld_inst {};
373};
374 373
375struct sxtb_inst { 374struct sxtb_inst {
376 unsigned int Rd; 375 unsigned int Rd;
@@ -475,7 +474,7 @@ struct pkh_inst {
475#include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 474#include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
476#undef VFP_INTERPRETER_STRUCT 475#undef VFP_INTERPRETER_STRUCT
477 476
478typedef void (*get_addr_fp_t)(ARMul_State *cpu, unsigned int inst, unsigned int &virt_addr); 477typedef void (*get_addr_fp_t)(ARMul_State* cpu, unsigned int inst, unsigned int& virt_addr);
479 478
480struct ldst_inst { 479struct ldst_inst {
481 unsigned int inst; 480 unsigned int inst;
HIC SVNT DRACONES