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authorGravatar bunnei2017-10-09 23:56:20 -0400
committerGravatar bunnei2017-10-09 23:56:20 -0400
commitb1d5db1cf60344b6b081c9d03cb6ccc3264326cd (patch)
treefde377c4ba3c0f92c032e6f5ec8627aae37270ef /src/core/arm/dyncom
parentloader: Various improvements for NSO/NRO loaders. (diff)
parentMerge pull request #2996 from MerryMage/split-travis (diff)
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Merge remote-tracking branch 'upstream/master' into nx
# Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp19
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h5
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp8
3 files changed, 19 insertions, 13 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 99758fc2a..5ebf7a2f1 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -29,6 +29,10 @@ void ARM_DynCom::SetPC(u64 pc) {
29 state->Reg[15] = pc; 29 state->Reg[15] = pc;
30} 30}
31 31
32void ARM_DynCom::PageTableChanged() {
33 ClearInstructionCache();
34}
35
32u64 ARM_DynCom::GetPC() const { 36u64 ARM_DynCom::GetPC() const {
33 return state->Reg[15]; 37 return state->Reg[15];
34} 38}
@@ -41,6 +45,13 @@ void ARM_DynCom::SetReg(int index, u64 value) {
41 state->Reg[index] = value; 45 state->Reg[index] = value;
42} 46}
43 47
48const u128& ARM_DynCom::GetExtReg(int index) const {
49 return {};
50}
51
52void ARM_DynCom::SetExtReg(int index, u128& value) {
53}
54
44u32 ARM_DynCom::GetVFPReg(int index) const { 55u32 ARM_DynCom::GetVFPReg(int index) const {
45 return state->ExtReg[index]; 56 return state->ExtReg[index];
46} 57}
@@ -80,12 +91,6 @@ VAddr ARM_DynCom::GetTlsAddress() const {
80void ARM_DynCom::SetTlsAddress(VAddr /*address*/) { 91void ARM_DynCom::SetTlsAddress(VAddr /*address*/) {
81} 92}
82 93
83void ARM_DynCom::AddTicks(u64 ticks) {
84 down_count -= ticks;
85 if (down_count < 0)
86 CoreTiming::Advance();
87}
88
89void ARM_DynCom::ExecuteInstructions(int num_instructions) { 94void ARM_DynCom::ExecuteInstructions(int num_instructions) {
90 state->NumInstrsToExecute = num_instructions; 95 state->NumInstrsToExecute = num_instructions;
91 96
@@ -93,7 +98,7 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
93 // executing one instruction at a time. Otherwise, if a block is being executed, more 98 // executing one instruction at a time. Otherwise, if a block is being executed, more
94 // instructions may actually be executed than specified. 99 // instructions may actually be executed than specified.
95 unsigned ticks_executed = InterpreterMainLoop(state.get()); 100 unsigned ticks_executed = InterpreterMainLoop(state.get());
96 AddTicks(ticks_executed); 101 CoreTiming::AddTicks(ticks_executed);
97} 102}
98 103
99void ARM_DynCom::SaveContext(ThreadContext& ctx) { 104void ARM_DynCom::SaveContext(ThreadContext& ctx) {
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 44e674ae2..cc3c0f3da 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -16,11 +16,14 @@ public:
16 ~ARM_DynCom(); 16 ~ARM_DynCom();
17 17
18 void ClearInstructionCache() override; 18 void ClearInstructionCache() override;
19 void PageTableChanged() override;
19 20
20 void SetPC(u64 pc) override; 21 void SetPC(u64 pc) override;
21 u64 GetPC() const override; 22 u64 GetPC() const override;
22 u64 GetReg(int index) const override; 23 u64 GetReg(int index) const override;
23 void SetReg(int index, u64 value) override; 24 void SetReg(int index, u64 value) override;
25 const u128& GetExtReg(int index) const override;
26 void SetExtReg(int index, u128& value) override;
24 u32 GetVFPReg(int index) const override; 27 u32 GetVFPReg(int index) const override;
25 void SetVFPReg(int index, u32 value) override; 28 void SetVFPReg(int index, u32 value) override;
26 u32 GetVFPSystemReg(VFPSystemRegister reg) const override; 29 u32 GetVFPSystemReg(VFPSystemRegister reg) const override;
@@ -32,8 +35,6 @@ public:
32 VAddr GetTlsAddress() const override; 35 VAddr GetTlsAddress() const override;
33 void SetTlsAddress(VAddr address) override; 36 void SetTlsAddress(VAddr address) override;
34 37
35 void AddTicks(u64 ticks) override;
36
37 void SaveContext(ThreadContext& ctx) override; 38 void SaveContext(ThreadContext& ctx) override;
38 void LoadContext(const ThreadContext& ctx) override; 39 void LoadContext(const ThreadContext& ctx) override;
39 40
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index f4fbb8d04..3522d1e82 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -759,7 +759,7 @@ static ThumbDecodeStatus DecodeThumbInstruction(u32 inst, u32 addr, u32* arm_ins
759 ThumbDecodeStatus ret = TranslateThumbInstruction(addr, inst, arm_inst, inst_size); 759 ThumbDecodeStatus ret = TranslateThumbInstruction(addr, inst, arm_inst, inst_size);
760 if (ret == ThumbDecodeStatus::BRANCH) { 760 if (ret == ThumbDecodeStatus::BRANCH) {
761 int inst_index; 761 int inst_index;
762 int table_length = arm_instruction_trans_len; 762 int table_length = static_cast<int>(arm_instruction_trans_len);
763 u32 tinstr = GetThumbInstruction(inst, addr); 763 u32 tinstr = GetThumbInstruction(inst, addr);
764 764
765 switch ((tinstr & 0xF800) >> 11) { 765 switch ((tinstr & 0xF800) >> 11) {
@@ -838,7 +838,7 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
838 return inst_size; 838 return inst_size;
839} 839}
840 840
841static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) { 841static int InterpreterTranslateBlock(ARMul_State* cpu, std::size_t& bb_start, u32 addr) {
842 MICROPROFILE_SCOPE(DynCom_Decode); 842 MICROPROFILE_SCOPE(DynCom_Decode);
843 843
844 // Decode instruction, get index 844 // Decode instruction, get index
@@ -871,7 +871,7 @@ static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr)
871 return KEEP_GOING; 871 return KEEP_GOING;
872} 872}
873 873
874static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) { 874static int InterpreterTranslateSingle(ARMul_State* cpu, std::size_t& bb_start, u32 addr) {
875 MICROPROFILE_SCOPE(DynCom_Decode); 875 MICROPROFILE_SCOPE(DynCom_Decode);
876 876
877 ARM_INST_PTR inst_base = nullptr; 877 ARM_INST_PTR inst_base = nullptr;
@@ -1620,7 +1620,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
1620 unsigned int addr; 1620 unsigned int addr;
1621 unsigned int num_instrs = 0; 1621 unsigned int num_instrs = 0;
1622 1622
1623 int ptr; 1623 std::size_t ptr;
1624 1624
1625 LOAD_NZCVT; 1625 LOAD_NZCVT;
1626DISPATCH : { 1626DISPATCH : {