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authorGravatar Lioncash2014-12-28 18:41:40 -0500
committerGravatar Lioncash2014-12-28 18:55:01 -0500
commit9c7f2570f774a05bfd085264c5db20074cd1f8d2 (patch)
tree21e5a73a28e0dbbc5e89b34d376e7a3509fb4fdb /src/core/arm/dyncom
parentMerge pull request #357 from bunnei/dyncom-pkhbt-pkhtb (diff)
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vfp: Actually make the code somewhat readable
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp74
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp49
2 files changed, 109 insertions, 14 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 5d174a08f..551bb77a6 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -28,9 +28,40 @@
28#include "core/arm/dyncom/arm_dyncom_dec.h" 28#include "core/arm/dyncom/arm_dyncom_dec.h"
29 29
30const ISEITEM arm_instruction[] = { 30const ISEITEM arm_instruction[] = {
31 #define VFP_DECODE 31 {"vmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0},
32 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 32 {"vmls", 7, ARMVFP2, 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0},
33 #undef VFP_DECODE 33 {"vnmla", 4, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0},
34 {"vnmla", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
35 {"vnmls", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
36 {"vnmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
37 {"vmul", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x2, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
38 {"vadd", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
39 {"vsub", 5, ARMVFP2, 23, 27, 0x1C, 20, 21, 0x3, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
40 {"vdiv", 5, ARMVFP2, 23, 27, 0x1D, 20, 21, 0x0, 9, 11, 0x5, 6, 6, 0, 4, 4, 0},
41 {"vmov(i)", 4, ARMVFP3, 23, 27, 0x1D, 20, 21, 0x3, 9, 11, 0x5, 4, 7, 0},
42 {"vmov(r)", 5, ARMVFP3, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 1, 4, 4, 0},
43 {"vabs", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x30, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
44 {"vneg", 5, ARMVFP2, 23, 27, 0x1D, 17, 21, 0x18, 9, 11, 0x5, 6, 7, 1, 4, 4, 0},
45 {"vsqrt", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x31, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
46 {"vcmp", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x34, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
47 {"vcmp2", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x35, 9, 11, 0x5, 0, 6, 0x40},
48 {"vcvt(bds)", 5, ARMVFP2, 23, 27, 0x1D, 16, 21, 0x37, 9, 11, 0x5, 6, 7, 3, 4, 4, 0},
49 {"vcvt(bff)", 6, ARMVFP3, 23, 27, 0x1D, 19, 21, 0x7, 17, 17, 0x1, 9, 11,5, 6, 6, 1},
50 {"vcvt(bfi)", 5, ARMVFP2, 23, 27, 0x1D, 19, 21, 0x7, 9, 11, 0x5, 6, 6, 1, 4, 4, 0},
51 {"vmovbrs", 3, ARMVFP2, 21, 27, 0x70, 8, 11, 0xA, 0, 6, 0x10},
52 {"vmsr", 2, ARMVFP2, 20, 27, 0xEE, 0, 11, 0xA10},
53 {"vmovbrc", 4, ARMVFP2, 23, 27, 0x1C, 20, 20, 0x0, 8, 11, 0xB, 0,4,0x10},
54 {"vmrs", 2, ARMVFP2, 20, 27, 0xEF, 0, 11, 0xA10},
55 {"vmovbcr", 4, ARMVFP2, 24, 27, 0xE, 20, 20, 1, 8, 11, 0xB, 0,4,0x10},
56 {"vmovbrrss", 3, ARMVFP2, 21, 27, 0x62, 8, 11, 0xA, 4, 4, 1},
57 {"vmovbrrd", 3, ARMVFP2, 21, 27, 0x62, 6, 11, 0x2C, 4, 4, 1},
58 {"vstr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 0, 9, 11,5},
59 {"vpush", 3, ARMVFP2, 23, 27, 0x1A, 16, 21, 0x2D, 9, 11,5},
60 {"vstm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 0, 9, 11,5},
61 {"vpop", 3, ARMVFP2, 23, 27, 0x19, 16, 21, 0x3D, 9, 11,5},
62 {"vldr", 3, ARMVFP2, 24, 27, 0xD, 20, 21, 1, 9, 11,5},
63 {"vldm", 3, ARMVFP2, 25, 27, 0x6, 20, 20, 1, 9, 11,5},
64
34 {"srs" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005}, 65 {"srs" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005},
35 {"rfe" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a}, 66 {"rfe" , 4 , 6 , 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a},
36 {"bkpt" , 2 , 3 , 20, 31, 0x00000e12, 4, 7, 0x00000007}, 67 {"bkpt" , 2 , 3 , 20, 31, 0x00000e12, 4, 7, 0x00000007},
@@ -187,9 +218,40 @@ const ISEITEM arm_instruction[] = {
187}; 218};
188 219
189const ISEITEM arm_exclusion_code[] = { 220const ISEITEM arm_exclusion_code[] = {
190 #define VFP_DECODE_EXCLUSION 221 {"vmla", 0, ARMVFP2, 0},
191 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 222 {"vmls", 0, ARMVFP2, 0},
192 #undef VFP_DECODE_EXCLUSION 223 {"vnmla", 0, ARMVFP2, 0},
224 {"vnmla", 0, ARMVFP2, 0},
225 {"vnmls", 0, ARMVFP2, 0},
226 {"vnmul", 0, ARMVFP2, 0},
227 {"vmul", 0, ARMVFP2, 0},
228 {"vadd", 0, ARMVFP2, 0},
229 {"vsub", 0, ARMVFP2, 0},
230 {"vdiv", 0, ARMVFP2, 0},
231 {"vmov(i)", 0, ARMVFP3, 0},
232 {"vmov(r)", 0, ARMVFP3, 0},
233 {"vabs", 0, ARMVFP2, 0},
234 {"vneg", 0, ARMVFP2, 0},
235 {"vsqrt", 0, ARMVFP2, 0},
236 {"vcmp", 0, ARMVFP2, 0},
237 {"vcmp2", 0, ARMVFP2, 0},
238 {"vcvt(bff)", 0, ARMVFP3, 4, 4, 1},
239 {"vcvt(bds)", 0, ARMVFP2, 0},
240 {"vcvt(bfi)", 0, ARMVFP2, 0},
241 {"vmovbrs", 0, ARMVFP2, 0},
242 {"vmsr", 0, ARMVFP2, 0},
243 {"vmovbrc", 0, ARMVFP2, 0},
244 {"vmrs", 0, ARMVFP2, 0},
245 {"vmovbcr", 0, ARMVFP2, 0},
246 {"vmovbrrss", 0, ARMVFP2, 0},
247 {"vmovbrrd", 0, ARMVFP2, 0},
248 {"vstr", 0, ARMVFP2, 0},
249 {"vpush", 0, ARMVFP2, 0},
250 {"vstm", 0, ARMVFP2, 0},
251 {"vpop", 0, ARMVFP2, 0},
252 {"vldr", 0, ARMVFP2, 0},
253 {"vldm", 0, ARMVFP2, 0},
254
193 {"srs" , 0 , 6 , 0}, 255 {"srs" , 0 , 6 , 0},
194 {"rfe" , 0 , 6 , 0}, 256 {"rfe" , 0 , 6 , 0},
195 {"bkpt" , 0 , 3 , 0}, 257 {"bkpt" , 0 , 3 , 0},
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 4cd8fe6ac..b4ee64203 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3363,9 +3363,40 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb16)(unsigned int inst, int index) { UN
3363typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int); 3363typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int);
3364 3364
3365const transop_fp_t arm_instruction_trans[] = { 3365const transop_fp_t arm_instruction_trans[] = {
3366 #define VFP_INTERPRETER_TABLE 3366 INTERPRETER_TRANSLATE(vmla),
3367 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 3367 INTERPRETER_TRANSLATE(vmls),
3368 #undef VFP_INTERPRETER_TABLE 3368 INTERPRETER_TRANSLATE(vnmla),
3369 INTERPRETER_TRANSLATE(vnmla),
3370 INTERPRETER_TRANSLATE(vnmls),
3371 INTERPRETER_TRANSLATE(vnmul),
3372 INTERPRETER_TRANSLATE(vmul),
3373 INTERPRETER_TRANSLATE(vadd),
3374 INTERPRETER_TRANSLATE(vsub),
3375 INTERPRETER_TRANSLATE(vdiv),
3376 INTERPRETER_TRANSLATE(vmovi),
3377 INTERPRETER_TRANSLATE(vmovr),
3378 INTERPRETER_TRANSLATE(vabs),
3379 INTERPRETER_TRANSLATE(vneg),
3380 INTERPRETER_TRANSLATE(vsqrt),
3381 INTERPRETER_TRANSLATE(vcmp),
3382 INTERPRETER_TRANSLATE(vcmp2),
3383 INTERPRETER_TRANSLATE(vcvtbds),
3384 INTERPRETER_TRANSLATE(vcvtbff),
3385 INTERPRETER_TRANSLATE(vcvtbfi),
3386 INTERPRETER_TRANSLATE(vmovbrs),
3387 INTERPRETER_TRANSLATE(vmsr),
3388 INTERPRETER_TRANSLATE(vmovbrc),
3389 INTERPRETER_TRANSLATE(vmrs),
3390 INTERPRETER_TRANSLATE(vmovbcr),
3391 INTERPRETER_TRANSLATE(vmovbrrss),
3392 INTERPRETER_TRANSLATE(vmovbrrd),
3393 INTERPRETER_TRANSLATE(vstr),
3394 INTERPRETER_TRANSLATE(vpush),
3395 INTERPRETER_TRANSLATE(vstm),
3396 INTERPRETER_TRANSLATE(vpop),
3397 INTERPRETER_TRANSLATE(vldr),
3398 INTERPRETER_TRANSLATE(vldm),
3399
3369 INTERPRETER_TRANSLATE(srs), 3400 INTERPRETER_TRANSLATE(srs),
3370 INTERPRETER_TRANSLATE(rfe), 3401 INTERPRETER_TRANSLATE(rfe),
3371 INTERPRETER_TRANSLATE(bkpt), 3402 INTERPRETER_TRANSLATE(bkpt),
@@ -4206,10 +4237,12 @@ unsigned InterpreterMainLoop(ARMul_State* state)
4206 // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback 4237 // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
4207 // to a clunky switch statement. 4238 // to a clunky switch statement.
4208#if defined __GNUC__ || defined __clang__ 4239#if defined __GNUC__ || defined __clang__
4209 void *InstLabel[] = { 4240 void *InstLabel[] = {
4210 #define VFP_INTERPRETER_LABEL 4241 &&VMLA_INST, &&VMLS_INST, &&VNMLA_INST, &&VNMLA_INST, &&VNMLS_INST, &&VNMUL_INST, &&VMUL_INST, &&VADD_INST, &&VSUB_INST,
4211 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 4242 &&VDIV_INST, &&VMOVI_INST, &&VMOVR_INST, &&VABS_INST, &&VNEG_INST, &&VSQRT_INST, &&VCMP_INST, &&VCMP2_INST, &&VCVTBDS_INST,
4212 #undef VFP_INTERPRETER_LABEL 4243 &&VCVTBFF_INST, &&VCVTBFI_INST, &&VMOVBRS_INST, &&VMSR_INST, &&VMOVBRC_INST, &&VMRS_INST, &&VMOVBCR_INST, &&VMOVBRRSS_INST,
4244 &&VMOVBRRD_INST, &&VSTR_INST, &&VPUSH_INST, &&VSTM_INST, &&VPOP_INST, &&VLDR_INST, &&VLDM_INST,
4245
4213 &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST, 4246 &&SRS_INST,&&RFE_INST,&&BKPT_INST,&&BLX_INST,&&CPS_INST,&&PLD_INST,&&SETEND_INST,&&CLREX_INST,&&REV16_INST,&&USAD8_INST,&&SXTB_INST,
4214 &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST, 4247 &&UXTB_INST,&&SXTH_INST,&&SXTB16_INST,&&UXTH_INST,&&UXTB16_INST,&&CPY_INST,&&UXTAB_INST,&&SSUB8_INST,&&SHSUB8_INST,&&SSUBADDX_INST,
4215 &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST, 4248 &&STREX_INST,&&STREXB_INST,&&SWP_INST,&&SWPB_INST,&&SSUB16_INST,&&SSAT16_INST,&&SHSUBADDX_INST,&&QSUBADDX_INST,&&SHADDSUBX_INST,
@@ -4243,7 +4276,7 @@ unsigned InterpreterMainLoop(ARMul_State* state)
4243 DISPATCH: 4276 DISPATCH:
4244 { 4277 {
4245 if (!cpu->NirqSig) { 4278 if (!cpu->NirqSig) {
4246 if (!(cpu->Cpsr & 0x80)) { 4279 if (!(cpu->Cpsr & 0x80)) {
4247 goto END; 4280 goto END;
4248 } 4281 }
4249 } 4282 }
HIC SVNT DRACONES