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authorGravatar Lioncash2015-04-20 16:15:33 -0400
committerGravatar Lioncash2015-04-20 16:30:34 -0400
commit8b2b620a5e70a47a5ff8b3b90c5159a03ead2745 (patch)
treefded294e2ca1076f9bdb52d6085b1fc620e17840 /src/core/arm/dyncom
parentMerge pull request #704 from citra-emu/archshift-patch-1 (diff)
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dyncom: Remove more unused/unnecessary code
Gets rid of a sizeable amount of stuff in armdefs.
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 1b1d01420..bc1e969e4 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -31,7 +31,6 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
31 31
32 // Reset the core to initial state 32 // Reset the core to initial state
33 ARMul_Reset(state.get()); 33 ARMul_Reset(state.get());
34 state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
35 state->Emulate = RUN; 34 state->Emulate = RUN;
36 35
37 // Switch to the desired privilege mode. 36 // Switch to the desired privilege mode.
@@ -99,7 +98,6 @@ void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 e
99 context.pc = entry_point; 98 context.pc = entry_point;
100 context.sp = stack_top; 99 context.sp = stack_top;
101 context.cpsr = 0x1F; // Usermode 100 context.cpsr = 0x1F; // Usermode
102 context.mode = 8; // Instructs dyncom CPU core to start execution as if it's "resuming" a thread.
103} 101}
104 102
105void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) { 103void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
@@ -113,8 +111,6 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
113 111
114 ctx.fpscr = state->VFP[1]; 112 ctx.fpscr = state->VFP[1];
115 ctx.fpexc = state->VFP[2]; 113 ctx.fpexc = state->VFP[2];
116
117 ctx.mode = state->NextInstr;
118} 114}
119 115
120void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) { 116void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
@@ -128,8 +124,6 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
128 124
129 state->VFP[1] = ctx.fpscr; 125 state->VFP[1] = ctx.fpscr;
130 state->VFP[2] = ctx.fpexc; 126 state->VFP[2] = ctx.fpexc;
131
132 state->NextInstr = ctx.mode;
133} 127}
134 128
135void ARM_DynCom::PrepareReschedule() { 129void ARM_DynCom::PrepareReschedule() {