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authorGravatar bunnei2017-05-08 16:02:53 -0400
committerGravatar GitHub2017-05-08 16:02:53 -0400
commit7325413cd8b4f02719ca0f87c8a70d4713333a98 (patch)
tree2bed3e545cb8b660d695763ce27dc3069847d7b1 /src/core/arm/dyncom
parentMerge pull request #2682 from nicoboss/filter (diff)
parentDyncom: Remove disassembler code (diff)
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Merge pull request #2689 from yuriks/remove-disassembler
Remove built-in disassembler and related code
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp15
3 files changed, 9 insertions, 10 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 64dcaae08..dcfcd6561 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -415,7 +415,7 @@ const InstructionSetEncodingItem arm_exclusion_code[] = {
415}; 415};
416// clang-format on 416// clang-format on
417 417
418ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { 418ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx) {
419 int n = 0; 419 int n = 0;
420 int base = 0; 420 int base = 0;
421 int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem); 421 int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index 2fb7ac37c..1dcf7ecd1 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -8,7 +8,7 @@
8 8
9enum class ARMDecodeStatus { SUCCESS, FAILURE }; 9enum class ARMDecodeStatus { SUCCESS, FAILURE };
10 10
11ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx); 11ARMDecodeStatus DecodeARMInstruction(u32 instr, int* idx);
12 12
13struct InstructionSetEncodingItem { 13struct InstructionSetEncodingItem {
14 const char* name; 14 const char* name;
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 273bc8167..f4fbb8d04 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5,11 +5,11 @@
5#define CITRA_IGNORE_EXIT(x) 5#define CITRA_IGNORE_EXIT(x)
6 6
7#include <algorithm> 7#include <algorithm>
8#include <cinttypes>
8#include <cstdio> 9#include <cstdio>
9#include "common/common_types.h" 10#include "common/common_types.h"
10#include "common/logging/log.h" 11#include "common/logging/log.h"
11#include "common/microprofile.h" 12#include "common/microprofile.h"
12#include "core/arm/disassembler/arm_disasm.h"
13#include "core/arm/dyncom/arm_dyncom_dec.h" 13#include "core/arm/dyncom/arm_dyncom_dec.h"
14#include "core/arm/dyncom/arm_dyncom_interpreter.h" 14#include "core/arm/dyncom/arm_dyncom_interpreter.h"
15#include "core/arm/dyncom/arm_dyncom_run.h" 15#include "core/arm/dyncom/arm_dyncom_run.h"
@@ -808,8 +808,8 @@ MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
808 808
809static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, 809static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr,
810 ARM_INST_PTR& inst_base) { 810 ARM_INST_PTR& inst_base) {
811 unsigned int inst_size = 4; 811 u32 inst_size = 4;
812 unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC); 812 u32 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
813 813
814 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM 814 // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM
815 // instruction 815 // instruction
@@ -827,11 +827,10 @@ static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, cons
827 827
828 int idx; 828 int idx;
829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) { 829 if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
830 std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst); 830 LOG_ERROR(Core_ARM11, "Decode failure.\tPC: [0x%08" PRIX32 "]\tInstruction: %08" PRIX32,
831 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, 831 phys_addr, inst);
832 disasm.c_str(), inst); 832 LOG_ERROR(Core_ARM11, "cpsr=0x%" PRIX32 ", cpu->TFlag=%d, r15=0x%08" PRIX32, cpu->Cpsr,
833 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, 833 cpu->TFlag, cpu->Reg[15]);
834 cpu->Reg[15]);
835 CITRA_IGNORE_EXIT(-1); 834 CITRA_IGNORE_EXIT(-1);
836 } 835 }
837 inst_base = arm_instruction_trans[idx](inst, idx); 836 inst_base = arm_instruction_trans[idx](inst, idx);