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authorGravatar Lioncash2015-12-06 15:11:09 -0500
committerGravatar Lioncash2015-12-06 15:14:51 -0500
commit56e22e6aac513e65acfec208a5d5ba2170eceb7a (patch)
tree27fa840b335e0898bd7220638e5e6b9ffeef79f9 /src/core/arm/dyncom
parentarm_interface: Make GetNumInstructions const (diff)
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dyncom: Remove static keyword from header functions
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_run.h4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h
index 85c8d798e..8eb694fee 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.h
+++ b/src/core/arm/dyncom/arm_dyncom_run.h
@@ -30,7 +30,7 @@
30 * @return If the PC is being read, then the word-aligned PC value is returned. 30 * @return If the PC is being read, then the word-aligned PC value is returned.
31 * If the PC is not being read, then the value stored in the register is returned. 31 * If the PC is not being read, then the value stored in the register is returned.
32 */ 32 */
33static inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) { 33inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
34 return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn]; 34 return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
35} 35}
36 36
@@ -43,6 +43,6 @@ static inline u32 CHECK_READ_REG15_WA(const ARMul_State* cpu, int Rn) {
43 * @return If the PC is being read, then the incremented PC value is returned. 43 * @return If the PC is being read, then the incremented PC value is returned.
44 * If the PC is not being read, then the values stored in the register is returned. 44 * If the PC is not being read, then the values stored in the register is returned.
45 */ 45 */
46static inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) { 46inline u32 CHECK_READ_REG15(const ARMul_State* cpu, int Rn) {
47 return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn]; 47 return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
48} 48}
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.h b/src/core/arm/dyncom/arm_dyncom_thumb.h
index 447974363..c1be3c735 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.h
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.h
@@ -38,7 +38,7 @@ enum class ThumbDecodeStatus {
38// Translates a Thumb mode instruction into its ARM equivalent. 38// Translates a Thumb mode instruction into its ARM equivalent.
39ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size); 39ThumbDecodeStatus TranslateThumbInstruction(u32 addr, u32 instr, u32* ainstr, u32* inst_size);
40 40
41static inline u32 GetThumbInstruction(u32 instr, u32 address) { 41inline u32 GetThumbInstruction(u32 instr, u32 address) {
42 // Normally you would need to handle instruction endianness, 42 // Normally you would need to handle instruction endianness,
43 // however, it is fixed to little-endian on the MPCore, so 43 // however, it is fixed to little-endian on the MPCore, so
44 // there's no need to check for this beforehand. 44 // there's no need to check for this beforehand.