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authorGravatar Lioncash2015-07-29 04:13:46 -0400
committerGravatar Lioncash2015-07-29 10:57:47 -0400
commit2e420aba3c007bff84988cf1c281db73c12c7f9a (patch)
tree039f0d852266d40de51982330d04aa54b68b8cef /src/core/arm/dyncom
parentMerge pull request #1007 from lioncash/pc (diff)
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dyncom: Handle the case where PC is the source register for STR/VSTM/VLDM
Diffstat (limited to 'src/core/arm/dyncom')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 0c20c2bc3..759ef7285 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -5997,7 +5997,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
5997 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 5997 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
5998 inst_cream->get_addr(cpu, inst_cream->inst, addr); 5998 inst_cream->get_addr(cpu, inst_cream->inst, addr);
5999 5999
6000 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 6000 unsigned int reg = BITS(inst_cream->inst, 12, 15);
6001 unsigned int value = cpu->Reg[reg];
6002
6003 if (reg == 15)
6004 value += 2 * cpu->GetInstructionSize();
6005
6001 cpu->WriteMemory32(addr, value); 6006 cpu->WriteMemory32(addr, value);
6002 } 6007 }
6003 cpu->Reg[15] += cpu->GetInstructionSize(); 6008 cpu->Reg[15] += cpu->GetInstructionSize();