dyncom: Use ARMul_State as an object

Gets rid of C-like parameter passing.

4 files changed, 189 insertions, 301 deletions

diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index a51a3acf8..9228a49ab 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -18,16 +18,7 @@
 #include "core/core_timing.h"
 
 ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
-    state = Common::make_unique<ARMul_State>();
-
-    // Reset the core to initial state
-    ARMul_Reset(state.get());
-
-    // Switch to the desired privilege mode.
-    switch_mode(state.get(), initial_mode);
-
-    state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
-    state->Reg[15] = 0x00000000;
+    state = Common::make_unique<ARMul_State>(initial_mode);
 }
 
 ARM_DynCom::~ARM_DynCom() {
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index fd5e13295..cf09acb4e 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -17,7 +17,6 @@
 #include "core/arm/dyncom/arm_dyncom_interpreter.h"
 #include "core/arm/dyncom/arm_dyncom_thumb.h"
 #include "core/arm/dyncom/arm_dyncom_run.h"
-#include "core/arm/skyeye_common/armmmu.h"
 #include "core/arm/skyeye_common/armstate.h"
 #include "core/arm/skyeye_common/armsupp.h"
 #include "core/arm/skyeye_common/vfp/vfp.h"
@@ -3964,7 +3963,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -3978,7 +3977,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(adc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -3990,7 +3989,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             u32 rn_val = RN;
             if (inst_cream->Rn == 15)
-                rn_val += 2 * GET_INST_SIZE(cpu);
+                rn_val += 2 * cpu->GetInstructionSize();
 
             bool carry;
             bool overflow;
@@ -3999,7 +3998,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Cpsr & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4013,7 +4012,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(add_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4028,7 +4027,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Cpsr & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4041,7 +4040,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(and_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4057,7 +4056,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             INC_PC(sizeof(bbl_inst));
             goto DISPATCH;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(bbl_inst));
         goto DISPATCH;
     }
@@ -4067,14 +4066,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
             u32 lop = RN;
             if (inst_cream->Rn == 15) {
-                lop += 2 * GET_INST_SIZE(cpu);
+                lop += 2 * cpu->GetInstructionSize();
             }
             u32 rop = SHIFTER_OPERAND;
             RD = lop & (~rop);
             if ((inst_cream->S) && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4087,7 +4086,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(bic_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4098,7 +4097,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
             LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(bkpt_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4109,13 +4108,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
             unsigned int inst = inst_cream->inst;
             if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
-                cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu));
+                cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
                 if(cpu->TFlag)
                     cpu->Reg[14] |= 0x1;
                 cpu->Reg[15] = cpu->Reg[inst_cream->val.Rm] & 0xfffffffe;
                 cpu->TFlag = cpu->Reg[inst_cream->val.Rm] & 0x1;
             } else {
-                cpu->Reg[14] = (cpu->Reg[15] + GET_INST_SIZE(cpu));
+                cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
                 cpu->TFlag = 0x1;
                 int signed_int = inst_cream->val.signed_immed_24;
                 signed_int = (signed_int & 0x800000) ? (0x3F000000 | signed_int) : signed_int;
@@ -4125,7 +4124,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             INC_PC(sizeof(blx_inst));
             goto DISPATCH;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(blx_inst));
         goto DISPATCH;
     }
@@ -4147,7 +4146,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             u32 address = RM;
 
             if (inst_cream->Rm == 15)
-                address += 2 * GET_INST_SIZE(cpu);
+                address += 2 * cpu->GetInstructionSize();
 
             cpu->TFlag   = address & 1;
             cpu->Reg[15] = address & 0xfffffffe;
@@ -4155,7 +4154,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             goto DISPATCH;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(bx_inst));
         goto DISPATCH;
     }
@@ -4167,7 +4166,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             cpu->NumInstrsToExecute = 0;
             return num_instrs;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(cdp_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4178,7 +4177,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         remove_exclusive(cpu, 0);
         cpu->exclusive_state = 0;
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(clrex_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4189,7 +4188,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             clz_inst* inst_cream = (clz_inst*)inst_base->component;
             RD = clz(RM);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(clz_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4208,7 +4207,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             cpu->CFlag = carry;
             cpu->VFlag = overflow;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(cmn_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4220,7 +4219,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             u32 rn_val = RN;
             if (inst_cream->Rn == 15)
-                rn_val += 2 * GET_INST_SIZE(cpu);
+                rn_val += 2 * cpu->GetInstructionSize();
 
             bool carry;
             bool overflow;
@@ -4231,7 +4230,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             cpu->CFlag = carry;
             cpu->VFlag = overflow;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(cmp_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4241,7 +4240,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         cps_inst *inst_cream = (cps_inst *)inst_base->component;
         uint32_t aif_val = 0;
         uint32_t aif_mask = 0;
-        if (InAPrivilegedMode(cpu)) {
+        if (cpu->InAPrivilegedMode()) {
             if (inst_cream->imod1) {
                 if (inst_cream->A) {
                     aif_val |= (inst_cream->imod0 << 8);
@@ -4260,10 +4259,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
             if (inst_cream->mmod) {
                 cpu->Cpsr = (cpu->Cpsr & 0xffffffe0) | inst_cream->mode;
-                switch_mode(cpu, inst_cream->mode);
+                cpu->ChangePrivilegeMode(inst_cream->mode);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(cps_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4279,7 +4278,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mov_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4291,14 +4290,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             u32 lop = RN;
             if (inst_cream->Rn == 15) {
-                lop += 2 * GET_INST_SIZE(cpu);
+                lop += 2 * cpu->GetInstructionSize();
             }
             u32 rop = SHIFTER_OPERAND;
             RD = lop ^ rop;
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4311,7 +4310,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(eor_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4320,7 +4319,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
     {
         // Instruction not implemented
         //LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4335,30 +4334,30 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (BIT(inst, 22) && !BIT(inst, 15)) {
                 for (int i = 0; i < 13; i++) {
                     if(BIT(inst, i)) {
-                        cpu->Reg[i] = ReadMemory32(cpu, addr);
+                        cpu->Reg[i] = cpu->ReadMemory32(addr);
                         addr += 4;
                     }
                 }
                 if (BIT(inst, 13)) {
                     if (cpu->Mode == USER32MODE)
-                        cpu->Reg[13] = ReadMemory32(cpu, addr);
+                        cpu->Reg[13] = cpu->ReadMemory32(addr);
                     else
-                        cpu->Reg_usr[0] = ReadMemory32(cpu, addr);
+                        cpu->Reg_usr[0] = cpu->ReadMemory32(addr);
 
                     addr += 4;
                 }
                 if (BIT(inst, 14)) {
                     if (cpu->Mode == USER32MODE)
-                        cpu->Reg[14] = ReadMemory32(cpu, addr);
+                        cpu->Reg[14] = cpu->ReadMemory32(addr);
                     else
-                        cpu->Reg_usr[1] = ReadMemory32(cpu, addr);
+                        cpu->Reg_usr[1] = cpu->ReadMemory32(addr);
 
                     addr += 4;
                 }
             } else if (!BIT(inst, 22)) {
                 for(int i = 0; i < 16; i++ ){
                     if(BIT(inst, i)){
-                        unsigned int ret = ReadMemory32(cpu, addr);
+                        unsigned int ret = cpu->ReadMemory32(addr);
 
                         // For armv5t, should enter thumb when bits[0] is non-zero.
                         if(i == 15){
@@ -4373,18 +4372,18 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             } else if (BIT(inst, 22) && BIT(inst, 15)) {
                 for(int i = 0; i < 15; i++ ){
                     if(BIT(inst, i)){
-                        cpu->Reg[i] = ReadMemory32(cpu, addr);
+                        cpu->Reg[i] = cpu->ReadMemory32(addr);
                         addr += 4;
                      }
                  }
 
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Cpsr & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
                     LOAD_NZCVT;
                 }
 
-                cpu->Reg[15] = ReadMemory32(cpu, addr);
+                cpu->Reg[15] = cpu->ReadMemory32(addr);
             }
 
             if (BIT(inst, 15)) {
@@ -4392,7 +4391,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4410,7 +4409,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
             RD = operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sxth_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4420,7 +4419,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
         inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
-        unsigned int value = ReadMemory32(cpu, addr);
+        unsigned int value = cpu->ReadMemory32(addr);
         cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
 
         if (BITS(inst_cream->inst, 12, 15) == 15) {
@@ -4431,7 +4430,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             goto DISPATCH;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4442,7 +4441,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
-            unsigned int value = ReadMemory32(cpu, addr);
+            unsigned int value = cpu->ReadMemory32(addr);
             cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
 
             if (BITS(inst_cream->inst, 12, 15) == 15) {
@@ -4453,7 +4452,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4464,7 +4463,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             uxth_inst* inst_cream = (uxth_inst*)inst_base->component;
             RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xffff;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxth_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4477,7 +4476,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             RD = RN + operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxtah_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4495,7 +4494,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4513,7 +4512,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4527,8 +4526,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             // The 3DS doesn't have LPAE (Large Physical Access Extension), so it
             // wouldn't do this as a single read.
-            cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = ReadMemory32(cpu, addr);
-            cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = ReadMemory32(cpu, addr + 4);
+            cpu->Reg[BITS(inst_cream->inst, 12, 15) + 0] = cpu->ReadMemory32(addr);
+            cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = cpu->ReadMemory32(addr + 4);
 
             // No dispatch since this operation should not modify R15
         }
@@ -4547,13 +4546,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             add_exclusive_addr(cpu, read_addr);
             cpu->exclusive_state = 1;
 
-            RD = ReadMemory32(cpu, read_addr);
+            RD = cpu->ReadMemory32(read_addr);
             if (inst_cream->Rd == 15) {
                 INC_PC(sizeof(generic_arm_inst));
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4573,7 +4572,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4587,13 +4586,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             add_exclusive_addr(cpu, read_addr);
             cpu->exclusive_state = 1;
 
-            RD = ReadMemory16(cpu, read_addr);
+            RD = cpu->ReadMemory16(read_addr);
             if (inst_cream->Rd == 15) {
                 INC_PC(sizeof(generic_arm_inst));
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4607,15 +4606,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             add_exclusive_addr(cpu, read_addr);
             cpu->exclusive_state = 1;
 
-            RD  = ReadMemory32(cpu, read_addr);
-            RD2 = ReadMemory32(cpu, read_addr + 4);
+            RD  = cpu->ReadMemory32(read_addr);
+            RD2 = cpu->ReadMemory32(read_addr + 4);
 
             if (inst_cream->Rd == 15) {
                 INC_PC(sizeof(generic_arm_inst));
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4626,13 +4625,13 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
-            cpu->Reg[BITS(inst_cream->inst, 12, 15)] = ReadMemory16(cpu, addr);
+            cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr);
             if (BITS(inst_cream->inst, 12, 15) == 15) {
                 INC_PC(sizeof(ldst_inst));
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4652,7 +4651,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4663,7 +4662,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
-            unsigned int value = ReadMemory16(cpu, addr);
+            unsigned int value = cpu->ReadMemory16(addr);
             if (BIT(value, 15)) {
                 value |= 0xffff0000;
             }
@@ -4673,7 +4672,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4684,7 +4683,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
-            unsigned int value = ReadMemory32(cpu, addr);
+            unsigned int value = cpu->ReadMemory32(addr);
             cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
 
             if (BITS(inst_cream->inst, 12, 15) == 15) {
@@ -4692,7 +4691,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4707,10 +4706,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 DEBUG_MSG;
             } else {
                 if (inst_cream->cp_num == 15)
-                    WriteCP15Register(cpu, RD, CRn, OPCODE_1, CRm, OPCODE_2);
+                    cpu->WriteCP15Register(RD, CRn, OPCODE_1, CRm, OPCODE_2);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mcr_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4727,7 +4726,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                       inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mcrr_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4752,7 +4751,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mla_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4766,7 +4765,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4779,7 +4778,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mov_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4800,10 +4799,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto END;
             } else {
                 if (inst_cream->cp_num == 15)
-                     RD = ReadCP15Register(cpu, CRn, OPCODE_1, CRm, OPCODE_2);
+                     RD = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mrc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4820,7 +4819,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                       inst_cream->cp_num, inst_cream->crm, inst_cream->opcode_1, inst_cream->rt, inst_cream->rt2);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mcrr_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4838,7 +4837,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 RD = cpu->Cpsr;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mrs_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4861,7 +4860,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                         | (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
             uint32_t mask = 0;
             if (!inst_cream->R) {
-                if (InAPrivilegedMode(cpu)) {
+                if (cpu->InAPrivilegedMode()) {
                     if ((operand & StateMask) != 0) {
                         /// UNPREDICTABLE
                         DEBUG_MSG;
@@ -4873,7 +4872,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 SAVE_NZCVT;
 
                 cpu->Cpsr = (cpu->Cpsr & ~mask) | (operand & mask);
-                switch_mode(cpu, cpu->Cpsr & 0x1f);
+                cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
                 LOAD_NZCVT;
             } else {
                 if (CurrentModeHasSPSR) {
@@ -4882,7 +4881,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 }
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(msr_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4904,7 +4903,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mul_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4919,7 +4918,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4932,7 +4931,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(mvn_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4949,7 +4948,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -4962,7 +4961,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(orr_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4970,7 +4969,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
     NOP_INST:
     {
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC_STUB;
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4982,7 +4981,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             pkh_inst *inst_cream = (pkh_inst *)inst_base->component;
             RD = (RN & 0xFFFF) | ((RM << inst_cream->imm) & 0xFFFF0000);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(pkh_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -4995,7 +4994,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             int shift_imm = inst_cream->imm ? inst_cream->imm : 31;
             RD = ((static_cast<s32>(RM) >> shift_imm) & 0xFFFF) | (RN & 0xFFFF0000);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(pkh_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5005,7 +5004,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
     {
         // Not implemented. PLD is a hint instruction, so it's optional.
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(pld_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5078,7 +5077,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = result;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5140,7 +5139,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5173,7 +5172,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(rev_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5187,8 +5186,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         u32 address = 0;
         inst_cream->get_addr(cpu, inst_cream->inst, address);
 
-        cpu->Cpsr    = ReadMemory32(cpu, address);
-        cpu->Reg[15] = ReadMemory32(cpu, address + 4);
+        cpu->Cpsr    = cpu->ReadMemory32(address);
+        cpu->Reg[15] = cpu->ReadMemory32(address + 4);
 
         INC_PC(sizeof(ldst_inst));
         goto DISPATCH;
@@ -5201,7 +5200,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             u32 rn_val = RN;
             if (inst_cream->Rn == 15)
-                rn_val += 2 * GET_INST_SIZE(cpu);
+                rn_val += 2 * cpu->GetInstructionSize();
 
             bool carry;
             bool overflow;
@@ -5210,7 +5209,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -5224,7 +5223,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(rsb_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5241,7 +5240,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -5255,7 +5254,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(rsc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5363,7 +5362,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5381,7 +5380,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -5395,7 +5394,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sbc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5434,7 +5433,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = result;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5453,7 +5452,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
         LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(setend_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5466,7 +5465,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             LOG_TRACE(Core_ARM11, "SEV executed.");
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC_STUB;
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5538,7 +5537,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5563,7 +5562,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (AddOverflow(operand1 * operand2, RN, RD))
                 cpu->Cpsr |= (1 << 27);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smla_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5619,7 +5618,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlad_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5648,7 +5647,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(umlal_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5678,7 +5677,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RDHI = ((dest >> 32) & 0xFFFFFFFF);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlalxy_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5703,7 +5702,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->Cpsr |= (1 << 27);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlad_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5741,7 +5740,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RDHI = ((result >> 32) & 0xFFFFFFFF);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlald_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5777,7 +5776,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = ((result >> 32) & 0xFFFFFFFF);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlad_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5799,7 +5798,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 operand2 = (BIT(RS, 31)) ? (BITS(RS, 16, 31) | 0xffff0000) : BITS(RS, 16, 31);
             RD = operand1 * operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smul_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5825,7 +5824,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(umull_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5841,7 +5840,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             s64 result = (s64)rm * (s64)(s32)RN;
             RD = BITS(result, 16, 47);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(smlad_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5855,10 +5854,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
         u32 address = 0;
         inst_cream->get_addr(cpu, inst_cream->inst, address);
 
-        WriteMemory32(cpu, address + 0, cpu->Reg[14]);
-        WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
+        cpu->WriteMemory32(address + 0, cpu->Reg[14]);
+        cpu->WriteMemory32(address + 4, cpu->Spsr_copy);
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5891,7 +5890,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = rn_val;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ssat_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5913,7 +5912,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->Cpsr |= (1 << 27);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ssat_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5923,7 +5922,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
     {
         // Instruction not implemented
         //LOG_CRITICAL(Core_ARM11, "unimplemented instruction");
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(stc_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5941,36 +5940,36 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (BIT(inst_cream->inst, 22) == 1) {
                 for (int i = 0; i < 13; i++) {
                     if (BIT(inst_cream->inst, i)) {
-                        WriteMemory32(cpu, addr, cpu->Reg[i]);
+                        cpu->WriteMemory32(addr, cpu->Reg[i]);
                         addr += 4;
                     }
                 }
                 if (BIT(inst_cream->inst, 13)) {
                     if (cpu->Mode == USER32MODE)
-                        WriteMemory32(cpu, addr, cpu->Reg[13]);
+                        cpu->WriteMemory32(addr, cpu->Reg[13]);
                     else
-                        WriteMemory32(cpu, addr, cpu->Reg_usr[0]);
+                        cpu->WriteMemory32(addr, cpu->Reg_usr[0]);
 
                     addr += 4;
                 }
                 if (BIT(inst_cream->inst, 14)) {
                     if (cpu->Mode == USER32MODE)
-                        WriteMemory32(cpu, addr, cpu->Reg[14]);
+                        cpu->WriteMemory32(addr, cpu->Reg[14]);
                     else
-                        WriteMemory32(cpu, addr, cpu->Reg_usr[1]);
+                        cpu->WriteMemory32(addr, cpu->Reg_usr[1]);
 
                     addr += 4;
                 }
                 if (BIT(inst_cream->inst, 15)) {
-                    WriteMemory32(cpu, addr, cpu->Reg_usr[1] + 8);
+                    cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8);
                 }
             } else {
                 for (int i = 0; i < 15; i++) {
                     if (BIT(inst_cream->inst, i)) {
                         if (i == Rn)
-                            WriteMemory32(cpu, addr, old_RN);
+                            cpu->WriteMemory32(addr, old_RN);
                         else
-                            WriteMemory32(cpu, addr, cpu->Reg[i]);
+                            cpu->WriteMemory32(addr, cpu->Reg[i]);
 
                         addr += 4;
                     }
@@ -5978,10 +5977,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
                 // Check PC reg
                 if (BIT(inst_cream->inst, 15))
-                    WriteMemory32(cpu, addr, cpu->Reg_usr[1] + 8);
+                    cpu->WriteMemory32(addr, cpu->Reg_usr[1] + 8);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -5999,7 +5998,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
             RD = operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sxtb_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6011,9 +6010,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
             unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
-            WriteMemory32(cpu, addr, value);
+            cpu->WriteMemory32(addr, value);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6024,7 +6023,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             uxtb_inst* inst_cream = (uxtb_inst*)inst_base->component;
             RD = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxtb_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6037,7 +6036,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             unsigned int operand2 = ROTATE_RIGHT_32(RM, 8 * inst_cream->rotate) & 0xff;
             RD = RN + operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxtab_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6050,7 +6049,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
             Memory::Write8(addr, value);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6063,7 +6062,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
             Memory::Write8(addr, value);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6076,10 +6075,10 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
 
             // The 3DS doesn't have the Large Physical Access Extension (LPAE)
             // so STRD wouldn't store these as a single write.
-            WriteMemory32(cpu, addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);
-            WriteMemory32(cpu, addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);
+            cpu->WriteMemory32(addr + 0, cpu->Reg[BITS(inst_cream->inst, 12, 15)]);
+            cpu->WriteMemory32(addr + 4, cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6094,14 +6093,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 remove_exclusive(cpu, write_addr);
                 cpu->exclusive_state = 0;
 
-                WriteMemory32(cpu, write_addr, RM);
+                cpu->WriteMemory32(write_addr, RM);
                 RD = 0;
             } else {
                 // Failed to write due to mutex access
                 RD = 1;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6123,7 +6122,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 RD = 1;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6142,12 +6141,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 const u32 rt2 = cpu->Reg[inst_cream->Rm + 1];
                 u64 value;
 
-                if (InBigEndianMode(cpu))
+                if (cpu->InBigEndianMode())
                     value = (((u64)rt << 32) | rt2);
                 else
                     value = (((u64)rt2 << 32) | rt);
 
-                WriteMemory64(cpu, write_addr, value);
+                cpu->WriteMemory64(write_addr, value);
                 RD = 0;
             }
             else {
@@ -6155,7 +6154,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 RD = 1;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6170,14 +6169,14 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 remove_exclusive(cpu, write_addr);
                 cpu->exclusive_state = 0;
 
-                WriteMemory16(cpu, write_addr, RM);
+                cpu->WriteMemory16(write_addr, RM);
                 RD = 0;
             } else {
                 // Failed to write due to mutex access
                 RD = 1;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6189,9 +6188,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
             unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
-            WriteMemory16(cpu, addr, value);
+            cpu->WriteMemory16(addr, value);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6203,9 +6202,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             inst_cream->get_addr(cpu, inst_cream->inst, addr);
 
             unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
-            WriteMemory32(cpu, addr, value);
+            cpu->WriteMemory32(addr, value);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ldst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6226,7 +6225,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             if (inst_cream->S && (inst_cream->Rd == 15)) {
                 if (CurrentModeHasSPSR) {
                     cpu->Cpsr = cpu->Spsr_copy;
-                    switch_mode(cpu, cpu->Spsr_copy & 0x1f);
+                    cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
                     LOAD_NZCVT;
                 }
             } else if (inst_cream->S) {
@@ -6240,7 +6239,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 goto DISPATCH;
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sub_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6252,7 +6251,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             SVC::CallSVC(inst_cream->num & 0xFFFF);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(swi_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6263,12 +6262,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             swp_inst* inst_cream = (swp_inst*)inst_base->component;
 
             addr = RN;
-            unsigned int value = ReadMemory32(cpu, addr);
-            WriteMemory32(cpu, addr, RM);
+            unsigned int value = cpu->ReadMemory32(addr);
+            cpu->WriteMemory32(addr, RM);
 
             RD = value;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(swp_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6282,7 +6281,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             Memory::Write8(addr, (RM & 0xFF));
             RD = value;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(swp_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6298,7 +6297,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             operand2 = (0x80 & operand2)? (0xFFFFFF00 | operand2):operand2;
             RD = RN + operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxtab_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6331,7 +6330,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sxtab_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6347,7 +6346,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             operand2 = (0x8000 & operand2) ? (0xFFFF0000 | operand2) : operand2;
             RD = RN + operand2;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(sxtah_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6362,7 +6361,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             u32 rop = SHIFTER_OPERAND;
 
             if (inst_cream->Rn == 15)
-                lop += GET_INST_SIZE(cpu) * 2;
+                lop += cpu->GetInstructionSize() * 2;
 
             u32 result = lop ^ rop;
 
@@ -6370,7 +6369,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             UPDATE_ZFLAG(result);
             UPDATE_CFLAG_WITH_SC;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(teq_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6384,7 +6383,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             u32 rop = SHIFTER_OPERAND;
 
             if (inst_cream->Rn == 15)
-                lop += GET_INST_SIZE(cpu) * 2;
+                lop += cpu->GetInstructionSize() * 2;
 
             u32 result = lop & rop;
 
@@ -6392,7 +6391,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             UPDATE_ZFLAG(result);
             UPDATE_CFLAG_WITH_SC;
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(tst_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6563,7 +6562,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6643,7 +6642,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6662,7 +6661,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RDLO = (result & 0xFFFFFFFF);
             RDHI = ((result >> 32) & 0xFFFFFFFF);
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(umaal_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6685,7 +6684,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(umlal_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6705,7 +6704,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->ZFlag = (RDHI == 0 && RDLO == 0);
             }
         }
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(umull_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6733,7 +6732,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
     {
         bl_1_thumb* inst_cream = (bl_1_thumb*)inst_base->component;
         cpu->Reg[14] = cpu->Reg[15] + 4 + inst_cream->imm;
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(bl_1_thumb));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6814,7 +6813,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = ((lo_val & 0xFFFF) | hi_val << 16);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6844,7 +6843,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = finalDif;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(generic_arm_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6877,7 +6876,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             RD = rn_val;
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ssat_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6899,7 +6898,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
                 cpu->Cpsr |= (1 << 27);
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(ssat_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6930,7 +6929,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             }
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC(sizeof(uxtab_inst));
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6943,7 +6942,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             LOG_TRACE(Core_ARM11, "WFE executed.");
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC_STUB;
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6956,7 +6955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             LOG_TRACE(Core_ARM11, "WFI executed.");
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC_STUB;
         FETCH_INST;
         GOTO_NEXT_INST;
@@ -6969,7 +6968,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
             LOG_TRACE(Core_ARM11, "YIELD executed.");
         }
 
-        cpu->Reg[15] += GET_INST_SIZE(cpu);
+        cpu->Reg[15] += cpu->GetInstructionSize();
         INC_PC_STUB;
         FETCH_INST;
         GOTO_NEXT_INST;
diff --git a/src/core/arm/dyncom/arm_dyncom_run.cpp b/src/core/arm/dyncom/arm_dyncom_run.cpp
deleted file mode 100644
index 4c6acba98..000000000
--- a/src/core/arm/dyncom/arm_dyncom_run.cpp
+++ /dev/null
@@ -1,93 +0,0 @@
-// Copyright 2012 Michael Kang, 2014 Citra Emulator Project
-// Licensed under GPLv2 or any later version
-// Refer to the license.txt file included.
-
-#include "core/arm/dyncom/arm_dyncom_run.h"
-#include "core/arm/skyeye_common/armstate.h"
-
-void switch_mode(ARMul_State* core, uint32_t mode) {
-    if (core->Mode == mode)
-        return;
-
-    if (mode != USERBANK) {
-        switch (core->Mode) {
-        case SYSTEM32MODE: // Shares registers with user mode
-        case USER32MODE:
-            core->Reg_usr[0] = core->Reg[13];
-            core->Reg_usr[1] = core->Reg[14];
-            break;
-        case IRQ32MODE:
-            core->Reg_irq[0] = core->Reg[13];
-            core->Reg_irq[1] = core->Reg[14];
-            core->Spsr[IRQBANK] = core->Spsr_copy;
-            break;
-        case SVC32MODE:
-            core->Reg_svc[0] = core->Reg[13];
-            core->Reg_svc[1] = core->Reg[14];
-            core->Spsr[SVCBANK] = core->Spsr_copy;
-            break;
-        case ABORT32MODE:
-            core->Reg_abort[0] = core->Reg[13];
-            core->Reg_abort[1] = core->Reg[14];
-            core->Spsr[ABORTBANK] = core->Spsr_copy;
-            break;
-        case UNDEF32MODE:
-            core->Reg_undef[0] = core->Reg[13];
-            core->Reg_undef[1] = core->Reg[14];
-            core->Spsr[UNDEFBANK] = core->Spsr_copy;
-            break;
-        case FIQ32MODE:
-            core->Reg_firq[0] = core->Reg[13];
-            core->Reg_firq[1] = core->Reg[14];
-            core->Spsr[FIQBANK] = core->Spsr_copy;
-            break;
-        }
-
-        switch (mode) {
-        case USER32MODE:
-            core->Reg[13] = core->Reg_usr[0];
-            core->Reg[14] = core->Reg_usr[1];
-            core->Bank = USERBANK;
-            break;
-        case IRQ32MODE:
-            core->Reg[13] = core->Reg_irq[0];
-            core->Reg[14] = core->Reg_irq[1];
-            core->Spsr_copy = core->Spsr[IRQBANK];
-            core->Bank = IRQBANK;
-            break;
-        case SVC32MODE:
-            core->Reg[13] = core->Reg_svc[0];
-            core->Reg[14] = core->Reg_svc[1];
-            core->Spsr_copy = core->Spsr[SVCBANK];
-            core->Bank = SVCBANK;
-            break;
-        case ABORT32MODE:
-            core->Reg[13] = core->Reg_abort[0];
-            core->Reg[14] = core->Reg_abort[1];
-            core->Spsr_copy = core->Spsr[ABORTBANK];
-            core->Bank = ABORTBANK;
-            break;
-        case UNDEF32MODE:
-            core->Reg[13] = core->Reg_undef[0];
-            core->Reg[14] = core->Reg_undef[1];
-            core->Spsr_copy = core->Spsr[UNDEFBANK];
-            core->Bank = UNDEFBANK;
-            break;
-        case FIQ32MODE:
-            core->Reg[13] = core->Reg_firq[0];
-            core->Reg[14] = core->Reg_firq[1];
-            core->Spsr_copy = core->Spsr[FIQBANK];
-            core->Bank = FIQBANK;
-            break;
-        case SYSTEM32MODE: // Shares registers with user mode.
-            core->Reg[13] = core->Reg_usr[0];
-            core->Reg[14] = core->Reg_usr[1];
-            core->Bank = SYSTEMBANK;
-            break;
-        }
-
-        // Set the mode bits in the APSR
-        core->Cpsr = (core->Cpsr & ~core->Mode) | mode;
-        core->Mode = mode;
-    }
-}
diff --git a/src/core/arm/dyncom/arm_dyncom_run.h b/src/core/arm/dyncom/arm_dyncom_run.h
index ef18455bc..13bef17fc 100644
--- a/src/core/arm/dyncom/arm_dyncom_run.h
+++ b/src/core/arm/dyncom/arm_dyncom_run.h
@@ -20,38 +20,29 @@
 
 #include "core/arm/skyeye_common/armstate.h"
 
-void switch_mode(ARMul_State* core, uint32_t mode);
-
-// Note that for the 3DS, a Thumb instruction will only ever be
-// two bytes in size. Thus we don't need to worry about ThumbEE
-// or Thumb-2 where instructions can be 4 bytes in length.
-static inline u32 GET_INST_SIZE(ARMul_State* core) {
-    return core->TFlag? 2 : 4;
-}
-
 /**
  * Checks if the PC is being read, and if so, word-aligns it.
  * Used with address calculations.
  *
- * @param core The ARM CPU state instance.
+ * @param cpu The ARM CPU state instance.
  * @param Rn   The register being read.
  *
  * @return If the PC is being read, then the word-aligned PC value is returned.
  *         If the PC is not being read, then the value stored in the register is returned.
  */
-static inline u32 CHECK_READ_REG15_WA(ARMul_State* core, int Rn) {
-    return (Rn == 15) ? ((core->Reg[15] & ~0x3) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
+static inline u32 CHECK_READ_REG15_WA(ARMul_State* cpu, int Rn) {
+    return (Rn == 15) ? ((cpu->Reg[15] & ~0x3) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
 }
 
 /**
  * Reads the PC. Used for data processing operations that use the PC.
  *
- * @param core The ARM CPU state instance.
+ * @param cpu The ARM CPU state instance.
  * @param Rn   The register being read.
  *
  * @return If the PC is being read, then the incremented PC value is returned.
  *         If the PC is not being read, then the values stored in the register is returned.
  */
-static inline u32 CHECK_READ_REG15(ARMul_State* core, int Rn) {
-    return (Rn == 15) ? ((core->Reg[15] & ~0x1) + GET_INST_SIZE(core) * 2) : core->Reg[Rn];
+static inline u32 CHECK_READ_REG15(ARMul_State* cpu, int Rn) {
+    return (Rn == 15) ? ((cpu->Reg[15] & ~0x1) + cpu->GetInstructionSize() * 2) : cpu->Reg[Rn];
 }