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authorGravatar bunnei2018-09-18 14:24:20 -0400
committerGravatar GitHub2018-09-18 14:24:20 -0400
commitc2cf784376c16c16655ddffb3fd3441e4f4ee5fb (patch)
tree280b3949296ee26f5fd4d10a8953cc3f3c532ca4 /src/core/arm/dynarmic
parentMerge pull request #1345 from lioncash/write (diff)
parentarm_interface: Remove ARM11-isms from the CPU interface (diff)
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Merge pull request #1344 from lioncash/arm
arm_interface: Remove ARM11-isms from the CPU interface
Diffstat (limited to 'src/core/arm/dynarmic')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.cpp31
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.h10
2 files changed, 15 insertions, 26 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 6db81c014..3f072c51f 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -194,29 +194,20 @@ void ARM_Dynarmic::SetReg(int index, u64 value) {
194 jit->SetRegister(index, value); 194 jit->SetRegister(index, value);
195} 195}
196 196
197u128 ARM_Dynarmic::GetExtReg(int index) const { 197u128 ARM_Dynarmic::GetVectorReg(int index) const {
198 return jit->GetVector(index); 198 return jit->GetVector(index);
199} 199}
200 200
201void ARM_Dynarmic::SetExtReg(int index, u128 value) { 201void ARM_Dynarmic::SetVectorReg(int index, u128 value) {
202 jit->SetVector(index, value); 202 jit->SetVector(index, value);
203} 203}
204 204
205u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const { 205u32 ARM_Dynarmic::GetPSTATE() const {
206 UNIMPLEMENTED();
207 return {};
208}
209
210void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
211 UNIMPLEMENTED();
212}
213
214u32 ARM_Dynarmic::GetCPSR() const {
215 return jit->GetPstate(); 206 return jit->GetPstate();
216} 207}
217 208
218void ARM_Dynarmic::SetCPSR(u32 cpsr) { 209void ARM_Dynarmic::SetPSTATE(u32 pstate) {
219 jit->SetPstate(cpsr); 210 jit->SetPstate(pstate);
220} 211}
221 212
222u64 ARM_Dynarmic::GetTlsAddress() const { 213u64 ARM_Dynarmic::GetTlsAddress() const {
@@ -239,18 +230,18 @@ void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
239 ctx.cpu_registers = jit->GetRegisters(); 230 ctx.cpu_registers = jit->GetRegisters();
240 ctx.sp = jit->GetSP(); 231 ctx.sp = jit->GetSP();
241 ctx.pc = jit->GetPC(); 232 ctx.pc = jit->GetPC();
242 ctx.cpsr = jit->GetPstate(); 233 ctx.pstate = jit->GetPstate();
243 ctx.fpu_registers = jit->GetVectors(); 234 ctx.vector_registers = jit->GetVectors();
244 ctx.fpscr = jit->GetFpcr(); 235 ctx.fpcr = jit->GetFpcr();
245} 236}
246 237
247void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) { 238void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
248 jit->SetRegisters(ctx.cpu_registers); 239 jit->SetRegisters(ctx.cpu_registers);
249 jit->SetSP(ctx.sp); 240 jit->SetSP(ctx.sp);
250 jit->SetPC(ctx.pc); 241 jit->SetPC(ctx.pc);
251 jit->SetPstate(static_cast<u32>(ctx.cpsr)); 242 jit->SetPstate(static_cast<u32>(ctx.pstate));
252 jit->SetVectors(ctx.fpu_registers); 243 jit->SetVectors(ctx.vector_registers);
253 jit->SetFpcr(static_cast<u32>(ctx.fpscr)); 244 jit->SetFpcr(static_cast<u32>(ctx.fpcr));
254} 245}
255 246
256void ARM_Dynarmic::PrepareReschedule() { 247void ARM_Dynarmic::PrepareReschedule() {
diff --git a/src/core/arm/dynarmic/arm_dynarmic.h b/src/core/arm/dynarmic/arm_dynarmic.h
index 56c60c853..e61382d3d 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.h
+++ b/src/core/arm/dynarmic/arm_dynarmic.h
@@ -29,14 +29,12 @@ public:
29 u64 GetPC() const override; 29 u64 GetPC() const override;
30 u64 GetReg(int index) const override; 30 u64 GetReg(int index) const override;
31 void SetReg(int index, u64 value) override; 31 void SetReg(int index, u64 value) override;
32 u128 GetExtReg(int index) const override; 32 u128 GetVectorReg(int index) const override;
33 void SetExtReg(int index, u128 value) override; 33 void SetVectorReg(int index, u128 value) override;
34 u32 GetVFPReg(int index) const override; 34 u32 GetPSTATE() const override;
35 void SetVFPReg(int index, u32 value) override; 35 void SetPSTATE(u32 pstate) override;
36 u32 GetCPSR() const override;
37 void Run() override; 36 void Run() override;
38 void Step() override; 37 void Step() override;
39 void SetCPSR(u32 cpsr) override;
40 VAddr GetTlsAddress() const override; 38 VAddr GetTlsAddress() const override;
41 void SetTlsAddress(VAddr address) override; 39 void SetTlsAddress(VAddr address) override;
42 void SetTPIDR_EL0(u64 value) override; 40 void SetTPIDR_EL0(u64 value) override;