Merge pull request #12236 from liamwhite/cpu-refactor

core: refactor emulated cpu core activation

7 files changed, 362 insertions, 492 deletions

diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 44a297cdc..f34865e26 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -1,25 +1,13 @@
 // SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include <cinttypes>
-#include <memory>
-#include <dynarmic/interface/A32/a32.h>
-#include <dynarmic/interface/A32/config.h>
-#include "common/assert.h"
-#include "common/literals.h"
-#include "common/logging/log.h"
-#include "common/page_table.h"
 #include "common/settings.h"
 #include "core/arm/dynarmic/arm_dynarmic.h"
 #include "core/arm/dynarmic/arm_dynarmic_32.h"
 #include "core/arm/dynarmic/dynarmic_cp15.h"
 #include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
-#include "core/core.h"
 #include "core/core_timing.h"
-#include "core/debugger/debugger.h"
 #include "core/hle/kernel/k_process.h"
-#include "core/hle/kernel/svc.h"
-#include "core/memory.h"
 
 namespace Core {
 
@@ -27,78 +15,78 @@ using namespace Common::Literals;
 
 class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks {
 public:
-    explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent_)
-        : parent{parent_}, memory(parent.system.ApplicationMemory()),
-          debugger_enabled{parent.system.DebuggerEnabled()},
-          check_memory_access{debugger_enabled ||
-                              !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
+    explicit DynarmicCallbacks32(ArmDynarmic32& parent, const Kernel::KProcess* process)
+        : m_parent{parent}, m_memory(process->GetMemory()),
+          m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()},
+          m_check_memory_access{m_debugger_enabled ||
+                                !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
 
     u8 MemoryRead8(u32 vaddr) override {
         CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
-        return memory.Read8(vaddr);
+        return m_memory.Read8(vaddr);
     }
     u16 MemoryRead16(u32 vaddr) override {
         CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
-        return memory.Read16(vaddr);
+        return m_memory.Read16(vaddr);
     }
     u32 MemoryRead32(u32 vaddr) override {
         CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
-        return memory.Read32(vaddr);
+        return m_memory.Read32(vaddr);
     }
     u64 MemoryRead64(u32 vaddr) override {
         CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
-        return memory.Read64(vaddr);
+        return m_memory.Read64(vaddr);
     }
     std::optional<u32> MemoryReadCode(u32 vaddr) override {
-        if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
+        if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
             return std::nullopt;
         }
-        return memory.Read32(vaddr);
+        return m_memory.Read32(vaddr);
     }
 
     void MemoryWrite8(u32 vaddr, u8 value) override {
         if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
-            memory.Write8(vaddr, value);
+            m_memory.Write8(vaddr, value);
         }
     }
     void MemoryWrite16(u32 vaddr, u16 value) override {
         if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
-            memory.Write16(vaddr, value);
+            m_memory.Write16(vaddr, value);
         }
     }
     void MemoryWrite32(u32 vaddr, u32 value) override {
         if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
-            memory.Write32(vaddr, value);
+            m_memory.Write32(vaddr, value);
         }
     }
     void MemoryWrite64(u32 vaddr, u64 value) override {
         if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
-            memory.Write64(vaddr, value);
+            m_memory.Write64(vaddr, value);
         }
     }
 
     bool MemoryWriteExclusive8(u32 vaddr, u8 value, u8 expected) override {
         return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive8(vaddr, value, expected);
+               m_memory.WriteExclusive8(vaddr, value, expected);
     }
     bool MemoryWriteExclusive16(u32 vaddr, u16 value, u16 expected) override {
         return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive16(vaddr, value, expected);
+               m_memory.WriteExclusive16(vaddr, value, expected);
     }
     bool MemoryWriteExclusive32(u32 vaddr, u32 value, u32 expected) override {
         return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive32(vaddr, value, expected);
+               m_memory.WriteExclusive32(vaddr, value, expected);
     }
     bool MemoryWriteExclusive64(u32 vaddr, u64 value, u64 expected) override {
         return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive64(vaddr, value, expected);
+               m_memory.WriteExclusive64(vaddr, value, expected);
     }
 
     void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
-        parent.LogBacktrace();
+        m_parent.LogBacktrace(m_process);
         LOG_ERROR(Core_ARM,
                   "Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
-                  num_instructions, memory.Read32(pc));
+                  num_instructions, m_memory.Read32(pc));
     }
 
     void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
@@ -108,73 +96,64 @@ public:
             ReturnException(pc, PrefetchAbort);
             return;
         default:
-            if (debugger_enabled) {
+            if (m_debugger_enabled) {
                 ReturnException(pc, InstructionBreakpoint);
                 return;
             }
 
-            parent.LogBacktrace();
+            m_parent.LogBacktrace(m_process);
             LOG_CRITICAL(Core_ARM,
                          "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X}, thumb = {})",
-                         exception, pc, memory.Read32(pc), parent.IsInThumbMode());
+                         exception, pc, m_memory.Read32(pc), m_parent.IsInThumbMode());
         }
     }
 
     void CallSVC(u32 swi) override {
-        parent.svc_swi = swi;
-        parent.jit.load()->HaltExecution(SupervisorCall);
+        m_parent.m_svc_swi = swi;
+        m_parent.m_jit->HaltExecution(SupervisorCall);
     }
 
     void AddTicks(u64 ticks) override {
-        if (parent.uses_wall_clock) {
-            return;
-        }
+        ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
 
         // Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
         // rough approximation of the amount of executed ticks in the system, it may be thrown off
         // if not all cores are doing a similar amount of work. Instead of doing this, we should
         // device a way so that timing is consistent across all cores without increasing the ticks 4
         // times.
-        u64 amortized_ticks =
-            (ticks - num_interpreted_instructions) / Core::Hardware::NUM_CPU_CORES;
+        u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES;
         // Always execute at least one tick.
         amortized_ticks = std::max<u64>(amortized_ticks, 1);
 
-        parent.system.CoreTiming().AddTicks(amortized_ticks);
-        num_interpreted_instructions = 0;
+        m_parent.m_system.CoreTiming().AddTicks(amortized_ticks);
     }
 
     u64 GetTicksRemaining() override {
-        if (parent.uses_wall_clock) {
-            if (!IsInterrupted()) {
-                return minimum_run_cycles;
-            }
-            return 0U;
-        }
+        ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
 
-        return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
+        return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0);
     }
 
     bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
-        if (!check_memory_access) {
+        if (!m_check_memory_access) {
             return true;
         }
 
-        if (!memory.IsValidVirtualAddressRange(addr, size)) {
+        if (!m_memory.IsValidVirtualAddressRange(addr, size)) {
             LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
                          addr);
-            parent.jit.load()->HaltExecution(PrefetchAbort);
+            m_parent.m_jit->HaltExecution(PrefetchAbort);
             return false;
         }
 
-        if (!debugger_enabled) {
+        if (!m_debugger_enabled) {
             return true;
         }
 
-        const auto match{parent.MatchingWatchpoint(addr, size, type)};
+        const auto match{m_parent.MatchingWatchpoint(addr, size, type)};
         if (match) {
-            parent.halted_watchpoint = match;
-            parent.jit.load()->HaltExecution(DataAbort);
+            m_parent.m_halted_watchpoint = match;
+            m_parent.m_jit->HaltExecution(DataAbort);
             return false;
         }
 
@@ -182,32 +161,31 @@ public:
     }
 
     void ReturnException(u32 pc, Dynarmic::HaltReason hr) {
-        parent.SaveContext(parent.breakpoint_context);
-        parent.breakpoint_context.cpu_registers[15] = pc;
-        parent.jit.load()->HaltExecution(hr);
-    }
-
-    bool IsInterrupted() {
-        return parent.system.Kernel().PhysicalCore(parent.core_index).IsInterrupted();
+        m_parent.GetContext(m_parent.m_breakpoint_context);
+        m_parent.m_breakpoint_context.pc = pc;
+        m_parent.m_breakpoint_context.r[15] = pc;
+        m_parent.m_jit->HaltExecution(hr);
     }
 
-    ARM_Dynarmic_32& parent;
-    Core::Memory::Memory& memory;
-    std::size_t num_interpreted_instructions{};
-    const bool debugger_enabled{};
-    const bool check_memory_access{};
-    static constexpr u64 minimum_run_cycles = 10000U;
+    ArmDynarmic32& m_parent;
+    Core::Memory::Memory& m_memory;
+    const Kernel::KProcess* m_process{};
+    const bool m_debugger_enabled{};
+    const bool m_check_memory_access{};
+    static constexpr u64 MinimumRunCycles = 10000U;
 };
 
-std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable* page_table) const {
+std::shared_ptr<Dynarmic::A32::Jit> ArmDynarmic32::MakeJit(Common::PageTable* page_table) const {
     Dynarmic::A32::UserConfig config;
-    config.callbacks = cb.get();
-    config.coprocessors[15] = cp15;
+    config.callbacks = m_cb.get();
+    config.coprocessors[15] = m_cp15;
     config.define_unpredictable_behaviour = true;
-    static constexpr std::size_t YUZU_PAGEBITS = 12;
-    static constexpr std::size_t NUM_PAGE_TABLE_ENTRIES = 1 << (32 - YUZU_PAGEBITS);
+
     if (page_table) {
-        config.page_table = reinterpret_cast<std::array<std::uint8_t*, NUM_PAGE_TABLE_ENTRIES>*>(
+        constexpr size_t PageBits = 12;
+        constexpr size_t NumPageTableEntries = 1 << (32 - PageBits);
+
+        config.page_table = reinterpret_cast<std::array<std::uint8_t*, NumPageTableEntries>*>(
             page_table->pointers.data());
         config.absolute_offset_page_table = true;
         config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS;
@@ -221,12 +199,12 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
     }
 
     // Multi-process state
-    config.processor_id = core_index;
-    config.global_monitor = &exclusive_monitor.monitor;
+    config.processor_id = m_core_index;
+    config.global_monitor = &m_exclusive_monitor.monitor;
 
     // Timing
-    config.wall_clock_cntpct = uses_wall_clock;
-    config.enable_cycle_counting = true;
+    config.wall_clock_cntpct = m_uses_wall_clock;
+    config.enable_cycle_counting = !m_uses_wall_clock;
 
     // Code cache size
 #ifdef ARCHITECTURE_arm64
@@ -236,7 +214,7 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
 #endif
 
     // Allow memory fault handling to work
-    if (system.DebuggerEnabled()) {
+    if (m_system.DebuggerEnabled()) {
         config.check_halt_on_memory_access = true;
     }
 
@@ -325,137 +303,140 @@ std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable*
     return std::make_unique<Dynarmic::A32::Jit>(config);
 }
 
-HaltReason ARM_Dynarmic_32::RunJit() {
-    return TranslateHaltReason(jit.load()->Run());
+static std::pair<u32, u32> FpscrToFpsrFpcr(u32 fpscr) {
+    // FPSCR bits [31:27] are mapped to FPSR[31:27].
+    // FPSCR bit [7] is mapped to FPSR[7].
+    // FPSCR bits [4:0] are mapped to FPSR[4:0].
+    const u32 nzcv = fpscr & 0xf8000000;
+    const u32 idc = fpscr & 0x80;
+    const u32 fiq = fpscr & 0x1f;
+    const u32 fpsr = nzcv | idc | fiq;
+
+    // FPSCR bits [26:15] are mapped to FPCR[26:15].
+    // FPSCR bits [12:8] are mapped to FPCR[12:8].
+    const u32 round = fpscr & 0x7ff8000;
+    const u32 trap = fpscr & 0x1f00;
+    const u32 fpcr = round | trap;
+
+    return {fpsr, fpcr};
 }
 
-HaltReason ARM_Dynarmic_32::StepJit() {
-    return TranslateHaltReason(jit.load()->Step());
+static u32 FpsrFpcrToFpscr(u64 fpsr, u64 fpcr) {
+    auto [s, c] = FpscrToFpsrFpcr(static_cast<u32>(fpsr | fpcr));
+    return s | c;
 }
 
-u32 ARM_Dynarmic_32::GetSvcNumber() const {
-    return svc_swi;
+bool ArmDynarmic32::IsInThumbMode() const {
+    return (m_jit->Cpsr() & 0x20) != 0;
 }
 
-const Kernel::DebugWatchpoint* ARM_Dynarmic_32::HaltedWatchpoint() const {
-    return halted_watchpoint;
+HaltReason ArmDynarmic32::RunThread(Kernel::KThread* thread) {
+    m_jit->ClearExclusiveState();
+    return TranslateHaltReason(m_jit->Run());
 }
 
-void ARM_Dynarmic_32::RewindBreakpointInstruction() {
-    LoadContext(breakpoint_context);
+HaltReason ArmDynarmic32::StepThread(Kernel::KThread* thread) {
+    m_jit->ClearExclusiveState();
+    return TranslateHaltReason(m_jit->Step());
 }
 
-ARM_Dynarmic_32::ARM_Dynarmic_32(System& system_, bool uses_wall_clock_,
-                                 DynarmicExclusiveMonitor& exclusive_monitor_,
-                                 std::size_t core_index_)
-    : ARM_Interface{system_, uses_wall_clock_}, cb(std::make_unique<DynarmicCallbacks32>(*this)),
-      cp15(std::make_shared<DynarmicCP15>(*this)), core_index{core_index_},
-      exclusive_monitor{exclusive_monitor_}, null_jit{MakeJit(nullptr)}, jit{null_jit.get()} {}
+u32 ArmDynarmic32::GetSvcNumber() const {
+    return m_svc_swi;
+}
 
-ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
+void ArmDynarmic32::GetSvcArguments(std::span<uint64_t, 8> args) const {
+    Dynarmic::A32::Jit& j = *m_jit;
+    auto& gpr = j.Regs();
 
-void ARM_Dynarmic_32::SetPC(u64 pc) {
-    jit.load()->Regs()[15] = static_cast<u32>(pc);
+    for (size_t i = 0; i < 8; i++) {
+        args[i] = gpr[i];
+    }
 }
 
-u64 ARM_Dynarmic_32::GetPC() const {
-    return jit.load()->Regs()[15];
-}
+void ArmDynarmic32::SetSvcArguments(std::span<const uint64_t, 8> args) {
+    Dynarmic::A32::Jit& j = *m_jit;
+    auto& gpr = j.Regs();
 
-u64 ARM_Dynarmic_32::GetSP() const {
-    return jit.load()->Regs()[13];
+    for (size_t i = 0; i < 8; i++) {
+        gpr[i] = static_cast<u32>(args[i]);
+    }
 }
 
-u64 ARM_Dynarmic_32::GetReg(int index) const {
-    return jit.load()->Regs()[index];
+const Kernel::DebugWatchpoint* ArmDynarmic32::HaltedWatchpoint() const {
+    return m_halted_watchpoint;
 }
 
-void ARM_Dynarmic_32::SetReg(int index, u64 value) {
-    jit.load()->Regs()[index] = static_cast<u32>(value);
+void ArmDynarmic32::RewindBreakpointInstruction() {
+    this->SetContext(m_breakpoint_context);
 }
 
-u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
-    return {};
+ArmDynarmic32::ArmDynarmic32(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
+                             DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index)
+    : ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor},
+      m_cb(std::make_unique<DynarmicCallbacks32>(*this, process)),
+      m_cp15(std::make_shared<DynarmicCP15>(*this)), m_core_index{core_index} {
+    auto& page_table_impl = process->GetPageTable().GetBasePageTable().GetImpl();
+    m_jit = MakeJit(&page_table_impl);
 }
 
-void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
+ArmDynarmic32::~ArmDynarmic32() = default;
 
-u32 ARM_Dynarmic_32::GetPSTATE() const {
-    return jit.load()->Cpsr();
+void ArmDynarmic32::SetTpidrroEl0(u64 value) {
+    m_cp15->uro = static_cast<u32>(value);
 }
 
-void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
-    jit.load()->SetCpsr(cpsr);
-}
+void ArmDynarmic32::GetContext(Kernel::Svc::ThreadContext& ctx) const {
+    Dynarmic::A32::Jit& j = *m_jit;
+    auto& gpr = j.Regs();
+    auto& fpr = j.ExtRegs();
 
-u64 ARM_Dynarmic_32::GetTlsAddress() const {
-    return cp15->uro;
-}
+    for (size_t i = 0; i < 16; i++) {
+        ctx.r[i] = gpr[i];
+    }
 
-void ARM_Dynarmic_32::SetTlsAddress(u64 address) {
-    cp15->uro = static_cast<u32>(address);
-}
+    ctx.fp = gpr[11];
+    ctx.sp = gpr[13];
+    ctx.lr = gpr[14];
+    ctx.pc = gpr[15];
+    ctx.pstate = j.Cpsr();
 
-u64 ARM_Dynarmic_32::GetTPIDR_EL0() const {
-    return cp15->uprw;
-}
+    static_assert(sizeof(fpr) <= sizeof(ctx.v));
+    std::memcpy(ctx.v.data(), &fpr, sizeof(fpr));
 
-void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
-    cp15->uprw = static_cast<u32>(value);
+    auto [fpsr, fpcr] = FpscrToFpsrFpcr(j.Fpscr());
+    ctx.fpcr = fpcr;
+    ctx.fpsr = fpsr;
+    ctx.tpidr = m_cp15->uprw;
 }
 
-void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) const {
-    Dynarmic::A32::Jit* j = jit.load();
-    ctx.cpu_registers = j->Regs();
-    ctx.extension_registers = j->ExtRegs();
-    ctx.cpsr = j->Cpsr();
-    ctx.fpscr = j->Fpscr();
-}
+void ArmDynarmic32::SetContext(const Kernel::Svc::ThreadContext& ctx) {
+    Dynarmic::A32::Jit& j = *m_jit;
+    auto& gpr = j.Regs();
+    auto& fpr = j.ExtRegs();
 
-void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
-    Dynarmic::A32::Jit* j = jit.load();
-    j->Regs() = ctx.cpu_registers;
-    j->ExtRegs() = ctx.extension_registers;
-    j->SetCpsr(ctx.cpsr);
-    j->SetFpscr(ctx.fpscr);
-}
+    for (size_t i = 0; i < 16; i++) {
+        gpr[i] = static_cast<u32>(ctx.r[i]);
+    }
 
-void ARM_Dynarmic_32::SignalInterrupt() {
-    jit.load()->HaltExecution(BreakLoop);
-}
+    j.SetCpsr(ctx.pstate);
 
-void ARM_Dynarmic_32::ClearInterrupt() {
-    jit.load()->ClearHalt(BreakLoop);
-}
+    static_assert(sizeof(fpr) <= sizeof(ctx.v));
+    std::memcpy(&fpr, ctx.v.data(), sizeof(fpr));
 
-void ARM_Dynarmic_32::ClearInstructionCache() {
-    jit.load()->ClearCache();
+    j.SetFpscr(FpsrFpcrToFpscr(ctx.fpsr, ctx.fpcr));
+    m_cp15->uprw = static_cast<u32>(ctx.tpidr);
 }
 
-void ARM_Dynarmic_32::InvalidateCacheRange(u64 addr, std::size_t size) {
-    jit.load()->InvalidateCacheRange(static_cast<u32>(addr), size);
+void ArmDynarmic32::SignalInterrupt(Kernel::KThread* thread) {
+    m_jit->HaltExecution(BreakLoop);
 }
 
-void ARM_Dynarmic_32::ClearExclusiveState() {
-    jit.load()->ClearExclusiveState();
+void ArmDynarmic32::ClearInstructionCache() {
+    m_jit->ClearCache();
 }
 
-void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
-                                       std::size_t new_address_space_size_in_bits) {
-    ThreadContext32 ctx{};
-    SaveContext(ctx);
-
-    auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
-    auto iter = jit_cache.find(key);
-    if (iter != jit_cache.end()) {
-        jit.store(iter->second.get());
-        LoadContext(ctx);
-        return;
-    }
-    std::shared_ptr new_jit = MakeJit(&page_table);
-    jit.store(new_jit.get());
-    LoadContext(ctx);
-    jit_cache.emplace(key, std::move(new_jit));
+void ArmDynarmic32::InvalidateCacheRange(u64 addr, std::size_t size) {
+    m_jit->InvalidateCacheRange(static_cast<u32>(addr), size);
 }
 
 } // namespace Core
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h
index 92fb3f836..185ac7cbf 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.h
@@ -3,14 +3,8 @@
 
 #pragma once
 
-#include <atomic>
-#include <memory>
-#include <unordered_map>
-
 #include <dynarmic/interface/A32/a32.h>
-#include <dynarmic/interface/A64/a64.h>
-#include "common/common_types.h"
-#include "common/hash.h"
+
 #include "core/arm/arm_interface.h"
 #include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
 
@@ -20,89 +14,63 @@ class Memory;
 
 namespace Core {
 
-class CPUInterruptHandler;
 class DynarmicCallbacks32;
 class DynarmicCP15;
-class DynarmicExclusiveMonitor;
 class System;
 
-class ARM_Dynarmic_32 final : public ARM_Interface {
+class ArmDynarmic32 final : public ArmInterface {
 public:
-    ARM_Dynarmic_32(System& system_, bool uses_wall_clock_,
-                    DynarmicExclusiveMonitor& exclusive_monitor_, std::size_t core_index_);
-    ~ARM_Dynarmic_32() override;
-
-    void SetPC(u64 pc) override;
-    u64 GetPC() const override;
-    u64 GetSP() const override;
-    u64 GetReg(int index) const override;
-    void SetReg(int index, u64 value) override;
-    u128 GetVectorReg(int index) const override;
-    void SetVectorReg(int index, u128 value) override;
-    u32 GetPSTATE() const override;
-    void SetPSTATE(u32 pstate) override;
-    u64 GetTlsAddress() const override;
-    void SetTlsAddress(u64 address) override;
-    void SetTPIDR_EL0(u64 value) override;
-    u64 GetTPIDR_EL0() const override;
-
-    bool IsInThumbMode() const {
-        return (GetPSTATE() & 0x20) != 0;
-    }
+    ArmDynarmic32(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
+                  DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index);
+    ~ArmDynarmic32() override;
 
     Architecture GetArchitecture() const override {
-        return Architecture::Aarch32;
+        return Architecture::AArch32;
     }
-    void SaveContext(ThreadContext32& ctx) const override;
-    void SaveContext(ThreadContext64& ctx) const override {}
-    void LoadContext(const ThreadContext32& ctx) override;
-    void LoadContext(const ThreadContext64& ctx) override {}
 
-    void SignalInterrupt() override;
-    void ClearInterrupt() override;
-    void ClearExclusiveState() override;
+    bool IsInThumbMode() const;
+
+    HaltReason RunThread(Kernel::KThread* thread) override;
+    HaltReason StepThread(Kernel::KThread* thread) override;
+
+    void GetContext(Kernel::Svc::ThreadContext& ctx) const override;
+    void SetContext(const Kernel::Svc::ThreadContext& ctx) override;
+    void SetTpidrroEl0(u64 value) override;
+
+    void GetSvcArguments(std::span<uint64_t, 8> args) const override;
+    void SetSvcArguments(std::span<const uint64_t, 8> args) override;
+    u32 GetSvcNumber() const override;
 
+    void SignalInterrupt(Kernel::KThread* thread) override;
     void ClearInstructionCache() override;
     void InvalidateCacheRange(u64 addr, std::size_t size) override;
-    void PageTableChanged(Common::PageTable& new_page_table,
-                          std::size_t new_address_space_size_in_bits) override;
 
 protected:
-    HaltReason RunJit() override;
-    HaltReason StepJit() override;
-    u32 GetSvcNumber() const override;
     const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
     void RewindBreakpointInstruction() override;
 
 private:
-    std::shared_ptr<Dynarmic::A32::Jit> MakeJit(Common::PageTable* page_table) const;
-
-    static std::vector<BacktraceEntry> GetBacktrace(Core::System& system, u64 fp, u64 lr, u64 pc);
-
-    using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
-    using JitCacheType =
-        std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A32::Jit>, Common::PairHash>;
+    System& m_system;
+    DynarmicExclusiveMonitor& m_exclusive_monitor;
 
+private:
     friend class DynarmicCallbacks32;
     friend class DynarmicCP15;
 
-    std::unique_ptr<DynarmicCallbacks32> cb;
-    JitCacheType jit_cache;
-    std::shared_ptr<DynarmicCP15> cp15;
-    std::size_t core_index;
-    DynarmicExclusiveMonitor& exclusive_monitor;
+    std::shared_ptr<Dynarmic::A32::Jit> MakeJit(Common::PageTable* page_table) const;
 
-    std::shared_ptr<Dynarmic::A32::Jit> null_jit;
+    std::unique_ptr<DynarmicCallbacks32> m_cb{};
+    std::shared_ptr<DynarmicCP15> m_cp15{};
+    std::size_t m_core_index{};
 
-    // A raw pointer here is fine; we never delete Jit instances.
-    std::atomic<Dynarmic::A32::Jit*> jit;
+    std::shared_ptr<Dynarmic::A32::Jit> m_jit{};
 
     // SVC callback
-    u32 svc_swi{};
+    u32 m_svc_swi{};
 
     // Watchpoint info
-    const Kernel::DebugWatchpoint* halted_watchpoint;
-    ThreadContext32 breakpoint_context;
+    const Kernel::DebugWatchpoint* m_halted_watchpoint{};
+    Kernel::Svc::ThreadContext m_breakpoint_context{};
 };
 
 } // namespace Core
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 2e3674b6d..dff14756e 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -1,25 +1,12 @@
 // SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include <cinttypes>
-#include <memory>
-#include <dynarmic/interface/A64/a64.h>
-#include <dynarmic/interface/A64/config.h>
-#include "common/assert.h"
-#include "common/literals.h"
-#include "common/logging/log.h"
-#include "common/page_table.h"
 #include "common/settings.h"
 #include "core/arm/dynarmic/arm_dynarmic.h"
 #include "core/arm/dynarmic/arm_dynarmic_64.h"
 #include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
-#include "core/core.h"
 #include "core/core_timing.h"
-#include "core/debugger/debugger.h"
-#include "core/hardware_properties.h"
 #include "core/hle/kernel/k_process.h"
-#include "core/hle/kernel/svc.h"
-#include "core/memory.h"
 
 namespace Core {
 
@@ -28,92 +15,92 @@ using namespace Common::Literals;
 
 class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
 public:
-    explicit DynarmicCallbacks64(ARM_Dynarmic_64& parent_)
-        : parent{parent_}, memory(parent.system.ApplicationMemory()),
-          debugger_enabled{parent.system.DebuggerEnabled()},
-          check_memory_access{debugger_enabled ||
-                              !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
+    explicit DynarmicCallbacks64(ArmDynarmic64& parent, const Kernel::KProcess* process)
+        : m_parent{parent}, m_memory(process->GetMemory()),
+          m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()},
+          m_check_memory_access{m_debugger_enabled ||
+                                !Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
 
     u8 MemoryRead8(u64 vaddr) override {
         CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
-        return memory.Read8(vaddr);
+        return m_memory.Read8(vaddr);
     }
     u16 MemoryRead16(u64 vaddr) override {
         CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
-        return memory.Read16(vaddr);
+        return m_memory.Read16(vaddr);
     }
     u32 MemoryRead32(u64 vaddr) override {
         CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
-        return memory.Read32(vaddr);
+        return m_memory.Read32(vaddr);
     }
     u64 MemoryRead64(u64 vaddr) override {
         CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
-        return memory.Read64(vaddr);
+        return m_memory.Read64(vaddr);
     }
     Vector MemoryRead128(u64 vaddr) override {
         CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Read);
-        return {memory.Read64(vaddr), memory.Read64(vaddr + 8)};
+        return {m_memory.Read64(vaddr), m_memory.Read64(vaddr + 8)};
     }
     std::optional<u32> MemoryReadCode(u64 vaddr) override {
-        if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
+        if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
             return std::nullopt;
         }
-        return memory.Read32(vaddr);
+        return m_memory.Read32(vaddr);
     }
 
     void MemoryWrite8(u64 vaddr, u8 value) override {
         if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
-            memory.Write8(vaddr, value);
+            m_memory.Write8(vaddr, value);
         }
     }
     void MemoryWrite16(u64 vaddr, u16 value) override {
         if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
-            memory.Write16(vaddr, value);
+            m_memory.Write16(vaddr, value);
         }
     }
     void MemoryWrite32(u64 vaddr, u32 value) override {
         if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
-            memory.Write32(vaddr, value);
+            m_memory.Write32(vaddr, value);
         }
     }
     void MemoryWrite64(u64 vaddr, u64 value) override {
         if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
-            memory.Write64(vaddr, value);
+            m_memory.Write64(vaddr, value);
         }
     }
     void MemoryWrite128(u64 vaddr, Vector value) override {
         if (CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write)) {
-            memory.Write64(vaddr, value[0]);
-            memory.Write64(vaddr + 8, value[1]);
+            m_memory.Write64(vaddr, value[0]);
+            m_memory.Write64(vaddr + 8, value[1]);
         }
     }
 
     bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
         return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive8(vaddr, value, expected);
+               m_memory.WriteExclusive8(vaddr, value, expected);
     }
     bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
         return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive16(vaddr, value, expected);
+               m_memory.WriteExclusive16(vaddr, value, expected);
     }
     bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
         return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive32(vaddr, value, expected);
+               m_memory.WriteExclusive32(vaddr, value, expected);
     }
     bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
         return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive64(vaddr, value, expected);
+               m_memory.WriteExclusive64(vaddr, value, expected);
     }
     bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
         return CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write) &&
-               memory.WriteExclusive128(vaddr, value, expected);
+               m_memory.WriteExclusive128(vaddr, value, expected);
     }
 
     void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
-        parent.LogBacktrace();
+        m_parent.LogBacktrace(m_process);
         LOG_ERROR(Core_ARM,
                   "Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
-                  num_instructions, memory.Read32(pc));
+                  num_instructions, m_memory.Read32(pc));
         ReturnException(pc, PrefetchAbort);
     }
 
@@ -124,11 +111,11 @@ public:
             static constexpr u64 ICACHE_LINE_SIZE = 64;
 
             const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
-            parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+            m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
             break;
         }
         case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
-            parent.system.InvalidateCpuInstructionCaches();
+            m_parent.ClearInstructionCache();
             break;
         case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
         default:
@@ -136,7 +123,7 @@ public:
             break;
         }
 
-        parent.jit.load()->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
+        m_parent.m_jit->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
     }
 
     void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
@@ -152,26 +139,24 @@ public:
             ReturnException(pc, PrefetchAbort);
             return;
         default:
-            if (debugger_enabled) {
+            if (m_debugger_enabled) {
                 ReturnException(pc, InstructionBreakpoint);
                 return;
             }
 
-            parent.LogBacktrace();
+            m_parent.LogBacktrace(m_process);
             LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
-                         static_cast<std::size_t>(exception), pc, memory.Read32(pc));
+                         static_cast<std::size_t>(exception), pc, m_memory.Read32(pc));
         }
     }
 
-    void CallSVC(u32 swi) override {
-        parent.svc_swi = swi;
-        parent.jit.load()->HaltExecution(SupervisorCall);
+    void CallSVC(u32 svc) override {
+        m_parent.m_svc = svc;
+        m_parent.m_jit->HaltExecution(SupervisorCall);
     }
 
     void AddTicks(u64 ticks) override {
-        if (parent.uses_wall_clock) {
-            return;
-        }
+        ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
 
         // Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
         // rough approximation of the amount of executed ticks in the system, it may be thrown off
@@ -182,44 +167,39 @@ public:
         // Always execute at least one tick.
         amortized_ticks = std::max<u64>(amortized_ticks, 1);
 
-        parent.system.CoreTiming().AddTicks(amortized_ticks);
+        m_parent.m_system.CoreTiming().AddTicks(amortized_ticks);
     }
 
     u64 GetTicksRemaining() override {
-        if (parent.uses_wall_clock) {
-            if (!IsInterrupted()) {
-                return minimum_run_cycles;
-            }
-            return 0U;
-        }
+        ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
 
-        return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
+        return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0);
     }
 
     u64 GetCNTPCT() override {
-        return parent.system.CoreTiming().GetClockTicks();
+        return m_parent.m_system.CoreTiming().GetClockTicks();
     }
 
     bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
-        if (!check_memory_access) {
+        if (!m_check_memory_access) {
             return true;
         }
 
-        if (!memory.IsValidVirtualAddressRange(addr, size)) {
+        if (!m_memory.IsValidVirtualAddressRange(addr, size)) {
             LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
                          addr);
-            parent.jit.load()->HaltExecution(PrefetchAbort);
+            m_parent.m_jit->HaltExecution(PrefetchAbort);
             return false;
         }
 
-        if (!debugger_enabled) {
+        if (!m_debugger_enabled) {
             return true;
         }
 
-        const auto match{parent.MatchingWatchpoint(addr, size, type)};
+        const auto match{m_parent.MatchingWatchpoint(addr, size, type)};
         if (match) {
-            parent.halted_watchpoint = match;
-            parent.jit.load()->HaltExecution(DataAbort);
+            m_parent.m_halted_watchpoint = match;
+            m_parent.m_jit->HaltExecution(DataAbort);
             return false;
         }
 
@@ -227,30 +207,27 @@ public:
     }
 
     void ReturnException(u64 pc, Dynarmic::HaltReason hr) {
-        parent.SaveContext(parent.breakpoint_context);
-        parent.breakpoint_context.pc = pc;
-        parent.jit.load()->HaltExecution(hr);
+        m_parent.GetContext(m_parent.m_breakpoint_context);
+        m_parent.m_breakpoint_context.pc = pc;
+        m_parent.m_jit->HaltExecution(hr);
     }
 
-    bool IsInterrupted() {
-        return parent.system.Kernel().PhysicalCore(parent.core_index).IsInterrupted();
-    }
-
-    ARM_Dynarmic_64& parent;
-    Core::Memory::Memory& memory;
-    u64 tpidrro_el0 = 0;
-    u64 tpidr_el0 = 0;
-    const bool debugger_enabled{};
-    const bool check_memory_access{};
-    static constexpr u64 minimum_run_cycles = 10000U;
+    ArmDynarmic64& m_parent;
+    Core::Memory::Memory& m_memory;
+    u64 m_tpidrro_el0{};
+    u64 m_tpidr_el0{};
+    const Kernel::KProcess* m_process{};
+    const bool m_debugger_enabled{};
+    const bool m_check_memory_access{};
+    static constexpr u64 MinimumRunCycles = 10000U;
 };
 
-std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable* page_table,
-                                                             std::size_t address_space_bits) const {
+std::shared_ptr<Dynarmic::A64::Jit> ArmDynarmic64::MakeJit(Common::PageTable* page_table,
+                                                           std::size_t address_space_bits) const {
     Dynarmic::A64::UserConfig config;
 
     // Callbacks
-    config.callbacks = cb.get();
+    config.callbacks = m_cb.get();
 
     // Memory
     if (page_table) {
@@ -271,12 +248,12 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
     }
 
     // Multi-process state
-    config.processor_id = core_index;
-    config.global_monitor = &exclusive_monitor.monitor;
+    config.processor_id = m_core_index;
+    config.global_monitor = &m_exclusive_monitor.monitor;
 
     // System registers
-    config.tpidrro_el0 = &cb->tpidrro_el0;
-    config.tpidr_el0 = &cb->tpidr_el0;
+    config.tpidrro_el0 = &m_cb->m_tpidrro_el0;
+    config.tpidr_el0 = &m_cb->m_tpidr_el0;
     config.dczid_el0 = 4;
     config.ctr_el0 = 0x8444c004;
     config.cntfrq_el0 = Hardware::CNTFREQ;
@@ -285,8 +262,8 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
     config.define_unpredictable_behaviour = true;
 
     // Timing
-    config.wall_clock_cntpct = uses_wall_clock;
-    config.enable_cycle_counting = true;
+    config.wall_clock_cntpct = m_uses_wall_clock;
+    config.enable_cycle_counting = !m_uses_wall_clock;
 
     // Code cache size
 #ifdef ARCHITECTURE_arm64
@@ -296,7 +273,7 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
 #endif
 
     // Allow memory fault handling to work
-    if (system.DebuggerEnabled()) {
+    if (m_system.DebuggerEnabled()) {
         config.check_halt_on_memory_access = true;
     }
 
@@ -384,147 +361,112 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable*
     return std::make_shared<Dynarmic::A64::Jit>(config);
 }
 
-HaltReason ARM_Dynarmic_64::RunJit() {
-    return TranslateHaltReason(jit.load()->Run());
-}
-
-HaltReason ARM_Dynarmic_64::StepJit() {
-    return TranslateHaltReason(jit.load()->Step());
-}
-
-u32 ARM_Dynarmic_64::GetSvcNumber() const {
-    return svc_swi;
-}
-
-const Kernel::DebugWatchpoint* ARM_Dynarmic_64::HaltedWatchpoint() const {
-    return halted_watchpoint;
-}
-
-void ARM_Dynarmic_64::RewindBreakpointInstruction() {
-    LoadContext(breakpoint_context);
-}
-
-ARM_Dynarmic_64::ARM_Dynarmic_64(System& system_, bool uses_wall_clock_,
-                                 DynarmicExclusiveMonitor& exclusive_monitor_,
-                                 std::size_t core_index_)
-    : ARM_Interface{system_, uses_wall_clock_},
-      cb(std::make_unique<DynarmicCallbacks64>(*this)), core_index{core_index_},
-      exclusive_monitor{exclusive_monitor_}, null_jit{MakeJit(nullptr, 48)}, jit{null_jit.get()} {}
-
-ARM_Dynarmic_64::~ARM_Dynarmic_64() = default;
-
-void ARM_Dynarmic_64::SetPC(u64 pc) {
-    jit.load()->SetPC(pc);
-}
-
-u64 ARM_Dynarmic_64::GetPC() const {
-    return jit.load()->GetPC();
+HaltReason ArmDynarmic64::RunThread(Kernel::KThread* thread) {
+    m_jit->ClearExclusiveState();
+    return TranslateHaltReason(m_jit->Run());
 }
 
-u64 ARM_Dynarmic_64::GetSP() const {
-    return jit.load()->GetSP();
+HaltReason ArmDynarmic64::StepThread(Kernel::KThread* thread) {
+    m_jit->ClearExclusiveState();
+    return TranslateHaltReason(m_jit->Step());
 }
 
-u64 ARM_Dynarmic_64::GetReg(int index) const {
-    return jit.load()->GetRegister(index);
+u32 ArmDynarmic64::GetSvcNumber() const {
+    return m_svc;
 }
 
-void ARM_Dynarmic_64::SetReg(int index, u64 value) {
-    jit.load()->SetRegister(index, value);
-}
+void ArmDynarmic64::GetSvcArguments(std::span<uint64_t, 8> args) const {
+    Dynarmic::A64::Jit& j = *m_jit;
 
-u128 ARM_Dynarmic_64::GetVectorReg(int index) const {
-    return jit.load()->GetVector(index);
+    for (size_t i = 0; i < 8; i++) {
+        args[i] = j.GetRegister(i);
+    }
 }
 
-void ARM_Dynarmic_64::SetVectorReg(int index, u128 value) {
-    jit.load()->SetVector(index, value);
-}
+void ArmDynarmic64::SetSvcArguments(std::span<const uint64_t, 8> args) {
+    Dynarmic::A64::Jit& j = *m_jit;
 
-u32 ARM_Dynarmic_64::GetPSTATE() const {
-    return jit.load()->GetPstate();
+    for (size_t i = 0; i < 8; i++) {
+        j.SetRegister(i, args[i]);
+    }
 }
 
-void ARM_Dynarmic_64::SetPSTATE(u32 pstate) {
-    jit.load()->SetPstate(pstate);
+const Kernel::DebugWatchpoint* ArmDynarmic64::HaltedWatchpoint() const {
+    return m_halted_watchpoint;
 }
 
-u64 ARM_Dynarmic_64::GetTlsAddress() const {
-    return cb->tpidrro_el0;
+void ArmDynarmic64::RewindBreakpointInstruction() {
+    this->SetContext(m_breakpoint_context);
 }
 
-void ARM_Dynarmic_64::SetTlsAddress(u64 address) {
-    cb->tpidrro_el0 = address;
+ArmDynarmic64::ArmDynarmic64(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
+                             DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index)
+    : ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor},
+      m_cb(std::make_unique<DynarmicCallbacks64>(*this, process)), m_core_index{core_index} {
+    auto& page_table = process->GetPageTable().GetBasePageTable();
+    auto& page_table_impl = page_table.GetImpl();
+    m_jit = MakeJit(&page_table_impl, page_table.GetAddressSpaceWidth());
 }
 
-u64 ARM_Dynarmic_64::GetTPIDR_EL0() const {
-    return cb->tpidr_el0;
-}
+ArmDynarmic64::~ArmDynarmic64() = default;
 
-void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
-    cb->tpidr_el0 = value;
+void ArmDynarmic64::SetTpidrroEl0(u64 value) {
+    m_cb->m_tpidrro_el0 = value;
 }
 
-void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) const {
-    Dynarmic::A64::Jit* j = jit.load();
-    ctx.cpu_registers = j->GetRegisters();
-    ctx.sp = j->GetSP();
-    ctx.pc = j->GetPC();
-    ctx.pstate = j->GetPstate();
-    ctx.vector_registers = j->GetVectors();
-    ctx.fpcr = j->GetFpcr();
-    ctx.fpsr = j->GetFpsr();
-    ctx.tpidr = cb->tpidr_el0;
-}
+void ArmDynarmic64::GetContext(Kernel::Svc::ThreadContext& ctx) const {
+    Dynarmic::A64::Jit& j = *m_jit;
+    auto gpr = j.GetRegisters();
+    auto fpr = j.GetVectors();
 
-void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
-    Dynarmic::A64::Jit* j = jit.load();
-    j->SetRegisters(ctx.cpu_registers);
-    j->SetSP(ctx.sp);
-    j->SetPC(ctx.pc);
-    j->SetPstate(ctx.pstate);
-    j->SetVectors(ctx.vector_registers);
-    j->SetFpcr(ctx.fpcr);
-    j->SetFpsr(ctx.fpsr);
-    SetTPIDR_EL0(ctx.tpidr);
+    // TODO: this is inconvenient
+    for (size_t i = 0; i < 29; i++) {
+        ctx.r[i] = gpr[i];
+    }
+    ctx.fp = gpr[29];
+    ctx.lr = gpr[30];
+
+    ctx.sp = j.GetSP();
+    ctx.pc = j.GetPC();
+    ctx.pstate = j.GetPstate();
+    ctx.v = fpr;
+    ctx.fpcr = j.GetFpcr();
+    ctx.fpsr = j.GetFpsr();
+    ctx.tpidr = m_cb->m_tpidr_el0;
 }
 
-void ARM_Dynarmic_64::SignalInterrupt() {
-    jit.load()->HaltExecution(BreakLoop);
-}
+void ArmDynarmic64::SetContext(const Kernel::Svc::ThreadContext& ctx) {
+    Dynarmic::A64::Jit& j = *m_jit;
 
-void ARM_Dynarmic_64::ClearInterrupt() {
-    jit.load()->ClearHalt(BreakLoop);
-}
+    // TODO: this is inconvenient
+    std::array<u64, 31> gpr;
 
-void ARM_Dynarmic_64::ClearInstructionCache() {
-    jit.load()->ClearCache();
+    for (size_t i = 0; i < 29; i++) {
+        gpr[i] = ctx.r[i];
+    }
+    gpr[29] = ctx.fp;
+    gpr[30] = ctx.lr;
+
+    j.SetRegisters(gpr);
+    j.SetSP(ctx.sp);
+    j.SetPC(ctx.pc);
+    j.SetPstate(ctx.pstate);
+    j.SetVectors(ctx.v);
+    j.SetFpcr(ctx.fpcr);
+    j.SetFpsr(ctx.fpsr);
+    m_cb->m_tpidr_el0 = ctx.tpidr;
 }
 
-void ARM_Dynarmic_64::InvalidateCacheRange(u64 addr, std::size_t size) {
-    jit.load()->InvalidateCacheRange(addr, size);
+void ArmDynarmic64::SignalInterrupt(Kernel::KThread* thread) {
+    m_jit->HaltExecution(BreakLoop);
 }
 
-void ARM_Dynarmic_64::ClearExclusiveState() {
-    jit.load()->ClearExclusiveState();
+void ArmDynarmic64::ClearInstructionCache() {
+    m_jit->ClearCache();
 }
 
-void ARM_Dynarmic_64::PageTableChanged(Common::PageTable& page_table,
-                                       std::size_t new_address_space_size_in_bits) {
-    ThreadContext64 ctx{};
-    SaveContext(ctx);
-
-    auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
-    auto iter = jit_cache.find(key);
-    if (iter != jit_cache.end()) {
-        jit.store(iter->second.get());
-        LoadContext(ctx);
-        return;
-    }
-    std::shared_ptr new_jit = MakeJit(&page_table, new_address_space_size_in_bits);
-    jit.store(new_jit.get());
-    LoadContext(ctx);
-    jit_cache.emplace(key, std::move(new_jit));
+void ArmDynarmic64::InvalidateCacheRange(u64 addr, std::size_t size) {
+    m_jit->InvalidateCacheRange(addr, size);
 }
 
 } // namespace Core
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h
index 2b88a08e2..4f3dd026f 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.h
@@ -23,76 +23,55 @@ class DynarmicCallbacks64;
 class DynarmicExclusiveMonitor;
 class System;
 
-class ARM_Dynarmic_64 final : public ARM_Interface {
+class ArmDynarmic64 final : public ArmInterface {
 public:
-    ARM_Dynarmic_64(System& system_, bool uses_wall_clock_,
-                    DynarmicExclusiveMonitor& exclusive_monitor_, std::size_t core_index_);
-    ~ARM_Dynarmic_64() override;
-
-    void SetPC(u64 pc) override;
-    u64 GetPC() const override;
-    u64 GetSP() const override;
-    u64 GetReg(int index) const override;
-    void SetReg(int index, u64 value) override;
-    u128 GetVectorReg(int index) const override;
-    void SetVectorReg(int index, u128 value) override;
-    u32 GetPSTATE() const override;
-    void SetPSTATE(u32 pstate) override;
-    u64 GetTlsAddress() const override;
-    void SetTlsAddress(u64 address) override;
-    void SetTPIDR_EL0(u64 value) override;
-    u64 GetTPIDR_EL0() const override;
+    ArmDynarmic64(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
+                  DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index);
+    ~ArmDynarmic64() override;
 
     Architecture GetArchitecture() const override {
-        return Architecture::Aarch64;
+        return Architecture::AArch64;
     }
-    void SaveContext(ThreadContext32& ctx) const override {}
-    void SaveContext(ThreadContext64& ctx) const override;
-    void LoadContext(const ThreadContext32& ctx) override {}
-    void LoadContext(const ThreadContext64& ctx) override;
 
-    void SignalInterrupt() override;
-    void ClearInterrupt() override;
-    void ClearExclusiveState() override;
+    HaltReason RunThread(Kernel::KThread* thread) override;
+    HaltReason StepThread(Kernel::KThread* thread) override;
 
+    void GetContext(Kernel::Svc::ThreadContext& ctx) const override;
+    void SetContext(const Kernel::Svc::ThreadContext& ctx) override;
+    void SetTpidrroEl0(u64 value) override;
+
+    void GetSvcArguments(std::span<uint64_t, 8> args) const override;
+    void SetSvcArguments(std::span<const uint64_t, 8> args) override;
+    u32 GetSvcNumber() const override;
+
+    void SignalInterrupt(Kernel::KThread* thread) override;
     void ClearInstructionCache() override;
     void InvalidateCacheRange(u64 addr, std::size_t size) override;
-    void PageTableChanged(Common::PageTable& new_page_table,
-                          std::size_t new_address_space_size_in_bits) override;
 
 protected:
-    HaltReason RunJit() override;
-    HaltReason StepJit() override;
-    u32 GetSvcNumber() const override;
     const Kernel::DebugWatchpoint* HaltedWatchpoint() const override;
     void RewindBreakpointInstruction() override;
 
 private:
-    std::shared_ptr<Dynarmic::A64::Jit> MakeJit(Common::PageTable* page_table,
-                                                std::size_t address_space_bits) const;
-
-    using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
-    using JitCacheType =
-        std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A64::Jit>, Common::PairHash>;
+    System& m_system;
+    DynarmicExclusiveMonitor& m_exclusive_monitor;
 
+private:
     friend class DynarmicCallbacks64;
-    std::unique_ptr<DynarmicCallbacks64> cb;
-    JitCacheType jit_cache;
-
-    std::size_t core_index;
-    DynarmicExclusiveMonitor& exclusive_monitor;
 
-    std::shared_ptr<Dynarmic::A64::Jit> null_jit;
+    std::shared_ptr<Dynarmic::A64::Jit> MakeJit(Common::PageTable* page_table,
+                                                std::size_t address_space_bits) const;
+    std::unique_ptr<DynarmicCallbacks64> m_cb{};
+    std::size_t m_core_index{};
 
-    // A raw pointer here is fine; we never delete Jit instances.
-    std::atomic<Dynarmic::A64::Jit*> jit;
+    std::shared_ptr<Dynarmic::A64::Jit> m_jit{};
 
     // SVC callback
-    u32 svc_swi{};
+    u32 m_svc{};
 
-    // Breakpoint info
-    const Kernel::DebugWatchpoint* halted_watchpoint;
-    ThreadContext64 breakpoint_context;
+    // Watchpoint info
+    const Kernel::DebugWatchpoint* m_halted_watchpoint{};
+    Kernel::Svc::ThreadContext m_breakpoint_context{};
 };
 
 } // namespace Core
diff --git a/src/core/arm/dynarmic/dynarmic_cp15.cpp b/src/core/arm/dynarmic/dynarmic_cp15.cpp
index 92c548db0..f3eee0d42 100644
--- a/src/core/arm/dynarmic/dynarmic_cp15.cpp
+++ b/src/core/arm/dynarmic/dynarmic_cp15.cpp
@@ -124,8 +124,8 @@ CallbackOrAccessTwoWords DynarmicCP15::CompileGetTwoWords(bool two, unsigned opc
     if (!two && opc == 0 && CRm == CoprocReg::C14) {
         // CNTPCT
         const auto callback = [](void* arg, u32, u32) -> u64 {
-            const auto& parent_arg = *static_cast<ARM_Dynarmic_32*>(arg);
-            return parent_arg.system.CoreTiming().GetClockTicks();
+            const auto& parent_arg = *static_cast<ArmDynarmic32*>(arg);
+            return parent_arg.m_system.CoreTiming().GetClockTicks();
         };
         return Callback{callback, &parent};
     }
diff --git a/src/core/arm/dynarmic/dynarmic_cp15.h b/src/core/arm/dynarmic/dynarmic_cp15.h
index d90b3e568..f3d96b0d8 100644
--- a/src/core/arm/dynarmic/dynarmic_cp15.h
+++ b/src/core/arm/dynarmic/dynarmic_cp15.h
@@ -10,13 +10,13 @@
 
 namespace Core {
 
-class ARM_Dynarmic_32;
+class ArmDynarmic32;
 
 class DynarmicCP15 final : public Dynarmic::A32::Coprocessor {
 public:
     using CoprocReg = Dynarmic::A32::CoprocReg;
 
-    explicit DynarmicCP15(ARM_Dynarmic_32& parent_) : parent{parent_} {}
+    explicit DynarmicCP15(ArmDynarmic32& parent_) : parent{parent_} {}
 
     std::optional<Callback> CompileInternalOperation(bool two, unsigned opc1, CoprocReg CRd,
                                                      CoprocReg CRn, CoprocReg CRm,
@@ -32,11 +32,11 @@ public:
     std::optional<Callback> CompileStoreWords(bool two, bool long_transfer, CoprocReg CRd,
                                               std::optional<u8> option) override;
 
-    ARM_Dynarmic_32& parent;
+    ArmDynarmic32& parent;
     u32 uprw = 0;
     u32 uro = 0;
 
-    friend class ARM_Dynarmic_32;
+    friend class ArmDynarmic32;
 };
 
 } // namespace Core
diff --git a/src/core/arm/dynarmic/dynarmic_exclusive_monitor.h b/src/core/arm/dynarmic/dynarmic_exclusive_monitor.h
index fbfcd8d95..c4f22ec89 100644
--- a/src/core/arm/dynarmic/dynarmic_exclusive_monitor.h
+++ b/src/core/arm/dynarmic/dynarmic_exclusive_monitor.h
@@ -14,8 +14,8 @@ class Memory;
 
 namespace Core {
 
-class ARM_Dynarmic_32;
-class ARM_Dynarmic_64;
+class ArmDynarmic32;
+class ArmDynarmic64;
 
 class DynarmicExclusiveMonitor final : public ExclusiveMonitor {
 public:
@@ -36,8 +36,8 @@ public:
     bool ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) override;
 
 private:
-    friend class ARM_Dynarmic_32;
-    friend class ARM_Dynarmic_64;
+    friend class ArmDynarmic32;
+    friend class ArmDynarmic64;
     Dynarmic::ExclusiveMonitor monitor;
     Core::Memory::Memory& memory;
 };