summaryrefslogtreecommitdiff
path: root/src/core/arm/disassembler
diff options
context:
space:
mode:
authorGravatar Emmanuel Gil Peyrot2016-09-18 09:38:01 +0900
committerGravatar Emmanuel Gil Peyrot2016-09-18 09:38:01 +0900
commitdc8479928c5aee4c6ad6fe4f59006fb604cee701 (patch)
tree569a7f13128450bbab973236615587ff00bced5f /src/core/arm/disassembler
parentTravis: Import Dolphin’s clang-format hook. (diff)
downloadyuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.tar.gz
yuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.tar.xz
yuzu-dc8479928c5aee4c6ad6fe4f59006fb604cee701.zip
Sources: Run clang-format on everything.
Diffstat (limited to 'src/core/arm/disassembler')
-rw-r--r--src/core/arm/disassembler/arm_disasm.cpp1290
-rw-r--r--src/core/arm/disassembler/arm_disasm.h88
-rw-r--r--src/core/arm/disassembler/load_symbol_map.cpp2
3 files changed, 586 insertions, 794 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp
index 5ad1f1c29..b3b9971e8 100644
--- a/src/core/arm/disassembler/arm_disasm.cpp
+++ b/src/core/arm/disassembler/arm_disasm.cpp
@@ -9,401 +9,225 @@
9#include "core/arm/disassembler/arm_disasm.h" 9#include "core/arm/disassembler/arm_disasm.h"
10#include "core/arm/skyeye_common/armsupp.h" 10#include "core/arm/skyeye_common/armsupp.h"
11 11
12static const char *cond_names[] = { 12static const char* cond_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
13 "eq", 13 "hi", "ls", "ge", "lt", "gt", "le", "", "RESERVED"};
14 "ne", 14
15 "cs", 15static const char* opcode_names[] = {
16 "cc", 16 "invalid", "undefined", "adc", "add", "and", "b", "bl", "bic",
17 "mi", 17 "bkpt", "blx", "bx", "cdp", "clrex", "clz", "cmn", "cmp",
18 "pl", 18 "eor", "ldc", "ldm", "ldr", "ldrb", "ldrbt", "ldrex", "ldrexb",
19 "vs", 19 "ldrexd", "ldrexh", "ldrh", "ldrsb", "ldrsh", "ldrt", "mcr", "mla",
20 "vc", 20 "mov", "mrc", "mrs", "msr", "mul", "mvn", "nop", "orr",
21 "hi", 21 "pkh", "pld", "qadd16", "qadd8", "qasx", "qsax", "qsub16", "qsub8",
22 "ls", 22 "rev", "rev16", "revsh", "rsb", "rsc", "sadd16", "sadd8", "sasx",
23 "ge", 23 "sbc", "sel", "sev", "shadd16", "shadd8", "shasx", "shsax", "shsub16",
24 "lt", 24 "shsub8", "smlad", "smlal", "smlald", "smlsd", "smlsld", "smmla", "smmls",
25 "gt", 25 "smmul", "smuad", "smull", "smusd", "ssat", "ssat16", "ssax", "ssub16",
26 "le", 26 "ssub8", "stc", "stm", "str", "strb", "strbt", "strex", "strexb",
27 "", 27 "strexd", "strexh", "strh", "strt", "sub", "swi", "swp", "swpb",
28 "RESERVED" 28 "sxtab", "sxtab16", "sxtah", "sxtb", "sxtb16", "sxth", "teq", "tst",
29}; 29 "uadd16", "uadd8", "uasx", "uhadd16", "uhadd8", "uhasx", "uhsax", "uhsub16",
30 30 "uhsub8", "umlal", "umull", "uqadd16", "uqadd8", "uqasx", "uqsax", "uqsub16",
31static const char *opcode_names[] = { 31 "uqsub8", "usad8", "usada8", "usat", "usat16", "usax", "usub16", "usub8",
32 "invalid", 32 "uxtab", "uxtab16", "uxtah", "uxtb", "uxtb16", "uxth", "wfe", "wfi",
33 "undefined",
34 "adc",
35 "add",
36 "and",
37 "b",
38 "bl",
39 "bic",
40 "bkpt",
41 "blx",
42 "bx",
43 "cdp",
44 "clrex",
45 "clz",
46 "cmn",
47 "cmp",
48 "eor",
49 "ldc",
50 "ldm",
51 "ldr",
52 "ldrb",
53 "ldrbt",
54 "ldrex",
55 "ldrexb",
56 "ldrexd",
57 "ldrexh",
58 "ldrh",
59 "ldrsb",
60 "ldrsh",
61 "ldrt",
62 "mcr",
63 "mla",
64 "mov",
65 "mrc",
66 "mrs",
67 "msr",
68 "mul",
69 "mvn",
70 "nop",
71 "orr",
72 "pkh",
73 "pld",
74 "qadd16",
75 "qadd8",
76 "qasx",
77 "qsax",
78 "qsub16",
79 "qsub8",
80 "rev",
81 "rev16",
82 "revsh",
83 "rsb",
84 "rsc",
85 "sadd16",
86 "sadd8",
87 "sasx",
88 "sbc",
89 "sel",
90 "sev",
91 "shadd16",
92 "shadd8",
93 "shasx",
94 "shsax",
95 "shsub16",
96 "shsub8",
97 "smlad",
98 "smlal",
99 "smlald",
100 "smlsd",
101 "smlsld",
102 "smmla",
103 "smmls",
104 "smmul",
105 "smuad",
106 "smull",
107 "smusd",
108 "ssat",
109 "ssat16",
110 "ssax",
111 "ssub16",
112 "ssub8",
113 "stc",
114 "stm",
115 "str",
116 "strb",
117 "strbt",
118 "strex",
119 "strexb",
120 "strexd",
121 "strexh",
122 "strh",
123 "strt",
124 "sub",
125 "swi",
126 "swp",
127 "swpb",
128 "sxtab",
129 "sxtab16",
130 "sxtah",
131 "sxtb",
132 "sxtb16",
133 "sxth",
134 "teq",
135 "tst",
136 "uadd16",
137 "uadd8",
138 "uasx",
139 "uhadd16",
140 "uhadd8",
141 "uhasx",
142 "uhsax",
143 "uhsub16",
144 "uhsub8",
145 "umlal",
146 "umull",
147 "uqadd16",
148 "uqadd8",
149 "uqasx",
150 "uqsax",
151 "uqsub16",
152 "uqsub8",
153 "usad8",
154 "usada8",
155 "usat",
156 "usat16",
157 "usax",
158 "usub16",
159 "usub8",
160 "uxtab",
161 "uxtab16",
162 "uxtah",
163 "uxtb",
164 "uxtb16",
165 "uxth",
166 "wfe",
167 "wfi",
168 "yield", 33 "yield",
169 34
170 "undefined", 35 "undefined", "adc", "add", "and", "asr", "b", "bic", "bkpt",
171 "adc", 36 "bl", "blx", "bx", "cmn", "cmp", "eor", "ldmia", "ldr",
172 "add", 37 "ldrb", "ldrh", "ldrsb", "ldrsh", "lsl", "lsr", "mov", "mul",
173 "and", 38 "mvn", "neg", "orr", "pop", "push", "ror", "sbc", "stmia",
174 "asr", 39 "str", "strb", "strh", "sub", "swi", "tst",
175 "b", 40
176 "bic", 41 nullptr};
177 "bkpt",
178 "bl",
179 "blx",
180 "bx",
181 "cmn",
182 "cmp",
183 "eor",
184 "ldmia",
185 "ldr",
186 "ldrb",
187 "ldrh",
188 "ldrsb",
189 "ldrsh",
190 "lsl",
191 "lsr",
192 "mov",
193 "mul",
194 "mvn",
195 "neg",
196 "orr",
197 "pop",
198 "push",
199 "ror",
200 "sbc",
201 "stmia",
202 "str",
203 "strb",
204 "strh",
205 "sub",
206 "swi",
207 "tst",
208
209 nullptr
210};
211 42
212// Indexed by the shift type (bits 6-5) 43// Indexed by the shift type (bits 6-5)
213static const char *shift_names[] = { 44static const char* shift_names[] = {"LSL", "LSR", "ASR", "ROR"};
214 "LSL",
215 "LSR",
216 "ASR",
217 "ROR"
218};
219 45
220static const char* cond_to_str(u32 cond) { 46static const char* cond_to_str(u32 cond) {
221 return cond_names[cond]; 47 return cond_names[cond];
222} 48}
223 49
224std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) 50std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) {
225{
226 Opcode opcode = Decode(insn); 51 Opcode opcode = Decode(insn);
227 switch (opcode) { 52 switch (opcode) {
228 case OP_INVALID: 53 case OP_INVALID:
229 return "Invalid"; 54 return "Invalid";
230 case OP_UNDEFINED: 55 case OP_UNDEFINED:
231 return "Undefined"; 56 return "Undefined";
232 case OP_ADC: 57 case OP_ADC:
233 case OP_ADD: 58 case OP_ADD:
234 case OP_AND: 59 case OP_AND:
235 case OP_BIC: 60 case OP_BIC:
236 case OP_CMN: 61 case OP_CMN:
237 case OP_CMP: 62 case OP_CMP:
238 case OP_EOR: 63 case OP_EOR:
239 case OP_MOV: 64 case OP_MOV:
240 case OP_MVN: 65 case OP_MVN:
241 case OP_ORR: 66 case OP_ORR:
242 case OP_RSB: 67 case OP_RSB:
243 case OP_RSC: 68 case OP_RSC:
244 case OP_SBC: 69 case OP_SBC:
245 case OP_SUB: 70 case OP_SUB:
246 case OP_TEQ: 71 case OP_TEQ:
247 case OP_TST: 72 case OP_TST:
248 return DisassembleALU(opcode, insn); 73 return DisassembleALU(opcode, insn);
249 case OP_B: 74 case OP_B:
250 case OP_BL: 75 case OP_BL:
251 return DisassembleBranch(addr, opcode, insn); 76 return DisassembleBranch(addr, opcode, insn);
252 case OP_BKPT: 77 case OP_BKPT:
253 return DisassembleBKPT(insn); 78 return DisassembleBKPT(insn);
254 case OP_BLX: 79 case OP_BLX:
255 // not supported yet 80 // not supported yet
256 break; 81 break;
257 case OP_BX: 82 case OP_BX:
258 return DisassembleBX(insn); 83 return DisassembleBX(insn);
259 case OP_CDP: 84 case OP_CDP:
260 return "cdp"; 85 return "cdp";
261 case OP_CLREX: 86 case OP_CLREX:
262 return "clrex"; 87 return "clrex";
263 case OP_CLZ: 88 case OP_CLZ:
264 return DisassembleCLZ(insn); 89 return DisassembleCLZ(insn);
265 case OP_LDC: 90 case OP_LDC:
266 return "ldc"; 91 return "ldc";
267 case OP_LDM: 92 case OP_LDM:
268 case OP_STM: 93 case OP_STM:
269 return DisassembleMemblock(opcode, insn); 94 return DisassembleMemblock(opcode, insn);
270 case OP_LDR: 95 case OP_LDR:
271 case OP_LDRB: 96 case OP_LDRB:
272 case OP_LDRBT: 97 case OP_LDRBT:
273 case OP_LDRT: 98 case OP_LDRT:
274 case OP_STR: 99 case OP_STR:
275 case OP_STRB: 100 case OP_STRB:
276 case OP_STRBT: 101 case OP_STRBT:
277 case OP_STRT: 102 case OP_STRT:
278 return DisassembleMem(insn); 103 return DisassembleMem(insn);
279 case OP_LDREX: 104 case OP_LDREX:
280 case OP_LDREXB: 105 case OP_LDREXB:
281 case OP_LDREXD: 106 case OP_LDREXD:
282 case OP_LDREXH: 107 case OP_LDREXH:
283 case OP_STREX: 108 case OP_STREX:
284 case OP_STREXB: 109 case OP_STREXB:
285 case OP_STREXD: 110 case OP_STREXD:
286 case OP_STREXH: 111 case OP_STREXH:
287 return DisassembleREX(opcode, insn); 112 return DisassembleREX(opcode, insn);
288 case OP_LDRH: 113 case OP_LDRH:
289 case OP_LDRSB: 114 case OP_LDRSB:
290 case OP_LDRSH: 115 case OP_LDRSH:
291 case OP_STRH: 116 case OP_STRH:
292 return DisassembleMemHalf(insn); 117 return DisassembleMemHalf(insn);
293 case OP_MCR: 118 case OP_MCR:
294 case OP_MRC: 119 case OP_MRC:
295 return DisassembleMCR(opcode, insn); 120 return DisassembleMCR(opcode, insn);
296 case OP_MLA: 121 case OP_MLA:
297 return DisassembleMLA(opcode, insn); 122 return DisassembleMLA(opcode, insn);
298 case OP_MRS: 123 case OP_MRS:
299 return DisassembleMRS(insn); 124 return DisassembleMRS(insn);
300 case OP_MSR: 125 case OP_MSR:
301 return DisassembleMSR(insn); 126 return DisassembleMSR(insn);
302 case OP_MUL: 127 case OP_MUL:
303 return DisassembleMUL(opcode, insn); 128 return DisassembleMUL(opcode, insn);
304 case OP_NOP: 129 case OP_NOP:
305 case OP_SEV: 130 case OP_SEV:
306 case OP_WFE: 131 case OP_WFE:
307 case OP_WFI: 132 case OP_WFI:
308 case OP_YIELD: 133 case OP_YIELD:
309 return DisassembleNoOperands(opcode, insn); 134 return DisassembleNoOperands(opcode, insn);
310 case OP_PKH: 135 case OP_PKH:
311 return DisassemblePKH(insn); 136 return DisassemblePKH(insn);
312 case OP_PLD: 137 case OP_PLD:
313 return DisassemblePLD(insn); 138 return DisassemblePLD(insn);
314 case OP_QADD16: 139 case OP_QADD16:
315 case OP_QADD8: 140 case OP_QADD8:
316 case OP_QASX: 141 case OP_QASX:
317 case OP_QSAX: 142 case OP_QSAX:
318 case OP_QSUB16: 143 case OP_QSUB16:
319 case OP_QSUB8: 144 case OP_QSUB8:
320 case OP_SADD16: 145 case OP_SADD16:
321 case OP_SADD8: 146 case OP_SADD8:
322 case OP_SASX: 147 case OP_SASX:
323 case OP_SHADD16: 148 case OP_SHADD16:
324 case OP_SHADD8: 149 case OP_SHADD8:
325 case OP_SHASX: 150 case OP_SHASX:
326 case OP_SHSAX: 151 case OP_SHSAX:
327 case OP_SHSUB16: 152 case OP_SHSUB16:
328 case OP_SHSUB8: 153 case OP_SHSUB8:
329 case OP_SSAX: 154 case OP_SSAX:
330 case OP_SSUB16: 155 case OP_SSUB16:
331 case OP_SSUB8: 156 case OP_SSUB8:
332 case OP_UADD16: 157 case OP_UADD16:
333 case OP_UADD8: 158 case OP_UADD8:
334 case OP_UASX: 159 case OP_UASX:
335 case OP_UHADD16: 160 case OP_UHADD16:
336 case OP_UHADD8: 161 case OP_UHADD8:
337 case OP_UHASX: 162 case OP_UHASX:
338 case OP_UHSAX: 163 case OP_UHSAX:
339 case OP_UHSUB16: 164 case OP_UHSUB16:
340 case OP_UHSUB8: 165 case OP_UHSUB8:
341 case OP_UQADD16: 166 case OP_UQADD16:
342 case OP_UQADD8: 167 case OP_UQADD8:
343 case OP_UQASX: 168 case OP_UQASX:
344 case OP_UQSAX: 169 case OP_UQSAX:
345 case OP_UQSUB16: 170 case OP_UQSUB16:
346 case OP_UQSUB8: 171 case OP_UQSUB8:
347 case OP_USAX: 172 case OP_USAX:
348 case OP_USUB16: 173 case OP_USUB16:
349 case OP_USUB8: 174 case OP_USUB8:
350 return DisassembleParallelAddSub(opcode, insn); 175 return DisassembleParallelAddSub(opcode, insn);
351 case OP_REV: 176 case OP_REV:
352 case OP_REV16: 177 case OP_REV16:
353 case OP_REVSH: 178 case OP_REVSH:
354 return DisassembleREV(opcode, insn); 179 return DisassembleREV(opcode, insn);
355 case OP_SEL: 180 case OP_SEL:
356 return DisassembleSEL(insn); 181 return DisassembleSEL(insn);
357 case OP_SMLAD: 182 case OP_SMLAD:
358 case OP_SMLALD: 183 case OP_SMLALD:
359 case OP_SMLSD: 184 case OP_SMLSD:
360 case OP_SMLSLD: 185 case OP_SMLSLD:
361 case OP_SMMLA: 186 case OP_SMMLA:
362 case OP_SMMLS: 187 case OP_SMMLS:
363 case OP_SMMUL: 188 case OP_SMMUL:
364 case OP_SMUAD: 189 case OP_SMUAD:
365 case OP_SMUSD: 190 case OP_SMUSD:
366 case OP_USAD8: 191 case OP_USAD8:
367 case OP_USADA8: 192 case OP_USADA8:
368 return DisassembleMediaMulDiv(opcode, insn); 193 return DisassembleMediaMulDiv(opcode, insn);
369 case OP_SSAT: 194 case OP_SSAT:
370 case OP_SSAT16: 195 case OP_SSAT16:
371 case OP_USAT: 196 case OP_USAT:
372 case OP_USAT16: 197 case OP_USAT16:
373 return DisassembleSAT(opcode, insn); 198 return DisassembleSAT(opcode, insn);
374 case OP_STC: 199 case OP_STC:
375 return "stc"; 200 return "stc";
376 case OP_SWI: 201 case OP_SWI:
377 return DisassembleSWI(insn); 202 return DisassembleSWI(insn);
378 case OP_SWP: 203 case OP_SWP:
379 case OP_SWPB: 204 case OP_SWPB:
380 return DisassembleSWP(opcode, insn); 205 return DisassembleSWP(opcode, insn);
381 case OP_SXTAB: 206 case OP_SXTAB:
382 case OP_SXTAB16: 207 case OP_SXTAB16:
383 case OP_SXTAH: 208 case OP_SXTAH:
384 case OP_SXTB: 209 case OP_SXTB:
385 case OP_SXTB16: 210 case OP_SXTB16:
386 case OP_SXTH: 211 case OP_SXTH:
387 case OP_UXTAB: 212 case OP_UXTAB:
388 case OP_UXTAB16: 213 case OP_UXTAB16:
389 case OP_UXTAH: 214 case OP_UXTAH:
390 case OP_UXTB: 215 case OP_UXTB:
391 case OP_UXTB16: 216 case OP_UXTB16:
392 case OP_UXTH: 217 case OP_UXTH:
393 return DisassembleXT(opcode, insn); 218 return DisassembleXT(opcode, insn);
394 case OP_UMLAL: 219 case OP_UMLAL:
395 case OP_UMULL: 220 case OP_UMULL:
396 case OP_SMLAL: 221 case OP_SMLAL:
397 case OP_SMULL: 222 case OP_SMULL:
398 return DisassembleUMLAL(opcode, insn); 223 return DisassembleUMLAL(opcode, insn);
399 default: 224 default:
400 return "Error"; 225 return "Error";
401 } 226 }
402 return nullptr; 227 return nullptr;
403} 228}
404 229
405std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) 230std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) {
406{
407 static const u8 kNoOperand1 = 1; 231 static const u8 kNoOperand1 = 1;
408 static const u8 kNoDest = 2; 232 static const u8 kNoDest = 2;
409 static const u8 kNoSbit = 4; 233 static const u8 kNoSbit = 4;
@@ -421,18 +245,18 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
421 245
422 const char* opname = opcode_names[opcode]; 246 const char* opname = opcode_names[opcode];
423 switch (opcode) { 247 switch (opcode) {
424 case OP_CMN: 248 case OP_CMN:
425 case OP_CMP: 249 case OP_CMP:
426 case OP_TEQ: 250 case OP_TEQ:
427 case OP_TST: 251 case OP_TST:
428 flags = kNoDest | kNoSbit; 252 flags = kNoDest | kNoSbit;
429 break; 253 break;
430 case OP_MOV: 254 case OP_MOV:
431 case OP_MVN: 255 case OP_MVN:
432 flags = kNoOperand1; 256 flags = kNoOperand1;
433 break; 257 break;
434 default: 258 default:
435 break; 259 break;
436 } 260 }
437 261
438 // The "mov" instruction ignores the first operand (rn). 262 // The "mov" instruction ignores the first operand (rn).
@@ -448,13 +272,13 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
448 rd_str = Common::StringFromFormat("r%d, ", rd); 272 rd_str = Common::StringFromFormat("r%d, ", rd);
449 } 273 }
450 274
451 const char *sbit_str = ""; 275 const char* sbit_str = "";
452 if (bit_s && !(flags & kNoSbit)) 276 if (bit_s && !(flags & kNoSbit))
453 sbit_str = "s"; 277 sbit_str = "s";
454 278
455 if (is_immed) { 279 if (is_immed) {
456 return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", 280 return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", opname, cond_to_str(cond),
457 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed); 281 sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
458 } 282 }
459 283
460 u8 shift_is_reg = (insn >> 4) & 1; 284 u8 shift_is_reg = (insn >> 4) & 1;
@@ -468,30 +292,28 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
468 rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2)); 292 rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
469 293
470 if (!shift_is_reg && shift_type == 0 && shift_amount == 0) { 294 if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
471 return Common::StringFromFormat("%s%s%s\t%s%sr%d", 295 return Common::StringFromFormat("%s%s%s\t%s%sr%d", opname, cond_to_str(cond), sbit_str,
472 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); 296 rd_str.c_str(), rn_str.c_str(), rm);
473 } 297 }
474 298
475 const char *shift_name = shift_names[shift_type]; 299 const char* shift_name = shift_names[shift_type];
476 if (shift_is_reg) { 300 if (shift_is_reg) {
477 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", 301 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", opname, cond_to_str(cond),
478 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, 302 sbit_str, rd_str.c_str(), rn_str.c_str(), rm, shift_name,
479 shift_name, rs); 303 rs);
480 } 304 }
481 if (shift_amount == 0) { 305 if (shift_amount == 0) {
482 if (shift_type == 3) { 306 if (shift_type == 3) {
483 return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", 307 return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", opname, cond_to_str(cond),
484 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); 308 sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
485 } 309 }
486 shift_amount = 32; 310 shift_amount = 32;
487 } 311 }
488 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", 312 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", opname, cond_to_str(cond), sbit_str,
489 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, 313 rd_str.c_str(), rn_str.c_str(), rm, shift_name, shift_amount);
490 shift_name, shift_amount);
491} 314}
492 315
493std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) 316std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) {
494{
495 u8 cond = (insn >> 28) & 0xf; 317 u8 cond = (insn >> 28) & 0xf;
496 u32 offset = insn & 0xffffff; 318 u32 offset = insn & 0xffffff;
497 // Sign-extend the 24-bit offset 319 // Sign-extend the 24-bit offset
@@ -502,26 +324,23 @@ std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn)
502 offset <<= 2; 324 offset <<= 2;
503 offset += 8; 325 offset += 8;
504 addr += offset; 326 addr += offset;
505 const char *opname = opcode_names[opcode]; 327 const char* opname = opcode_names[opcode];
506 return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr); 328 return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
507} 329}
508 330
509std::string ARM_Disasm::DisassembleBX(u32 insn) 331std::string ARM_Disasm::DisassembleBX(u32 insn) {
510{
511 u8 cond = (insn >> 28) & 0xf; 332 u8 cond = (insn >> 28) & 0xf;
512 u8 rn = insn & 0xf; 333 u8 rn = insn & 0xf;
513 return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn); 334 return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
514} 335}
515 336
516std::string ARM_Disasm::DisassembleBKPT(u32 insn) 337std::string ARM_Disasm::DisassembleBKPT(u32 insn) {
517{
518 u8 cond = (insn >> 28) & 0xf; 338 u8 cond = (insn >> 28) & 0xf;
519 u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf); 339 u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
520 return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed); 340 return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
521} 341}
522 342
523std::string ARM_Disasm::DisassembleCLZ(u32 insn) 343std::string ARM_Disasm::DisassembleCLZ(u32 insn) {
524{
525 u8 cond = (insn >> 28) & 0xf; 344 u8 cond = (insn >> 28) & 0xf;
526 u8 rd = (insn >> 12) & 0xf; 345 u8 rd = (insn >> 12) & 0xf;
527 u8 rm = insn & 0xf; 346 u8 rm = insn & 0xf;
@@ -545,9 +364,8 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
545 } 364 }
546 365
547 std::string ext_reg = ""; 366 std::string ext_reg = "";
548 std::unordered_set<Opcode, std::hash<int>> with_ext_reg = { 367 std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {OP_SMLAD, OP_SMLSD, OP_SMMLA,
549 OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8 368 OP_SMMLS, OP_USADA8};
550 };
551 if (with_ext_reg.find(opcode) != with_ext_reg.end()) 369 if (with_ext_reg.find(opcode) != with_ext_reg.end())
552 ext_reg = Common::StringFromFormat(", r%u", ra); 370 ext_reg = Common::StringFromFormat(", r%u", ra);
553 371
@@ -560,8 +378,7 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
560 ext_reg.c_str()); 378 ext_reg.c_str());
561} 379}
562 380
563std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) 381std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) {
564{
565 std::string tmp_list; 382 std::string tmp_list;
566 383
567 u8 cond = (insn >> 28) & 0xf; 384 u8 cond = (insn >> 28) & 0xf;
@@ -572,17 +389,17 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
572 u8 rn = (insn >> 16) & 0xf; 389 u8 rn = (insn >> 16) & 0xf;
573 u16 reg_list = insn & 0xffff; 390 u16 reg_list = insn & 0xffff;
574 391
575 const char *opname = opcode_names[opcode]; 392 const char* opname = opcode_names[opcode];
576 393
577 const char *bang = ""; 394 const char* bang = "";
578 if (write_back) 395 if (write_back)
579 bang = "!"; 396 bang = "!";
580 397
581 const char *carret = ""; 398 const char* carret = "";
582 if (bit_s) 399 if (bit_s)
583 carret = "^"; 400 carret = "^";
584 401
585 const char *comma = ""; 402 const char* comma = "";
586 tmp_list[0] = 0; 403 tmp_list[0] = 0;
587 for (int ii = 0; ii < 16; ++ii) { 404 for (int ii = 0; ii < 16; ++ii) {
588 if (reg_list & (1 << ii)) { 405 if (reg_list & (1 << ii)) {
@@ -591,7 +408,7 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
591 } 408 }
592 } 409 }
593 410
594 const char *addr_mode = ""; 411 const char* addr_mode = "";
595 if (is_pre) { 412 if (is_pre) {
596 if (is_up) { 413 if (is_up) {
597 addr_mode = "ib"; 414 addr_mode = "ib";
@@ -606,12 +423,11 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
606 } 423 }
607 } 424 }
608 425
609 return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", 426 return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", opname, cond_to_str(cond), addr_mode,
610 opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret); 427 rn, bang, tmp_list.c_str(), carret);
611} 428}
612 429
613std::string ARM_Disasm::DisassembleMem(u32 insn) 430std::string ARM_Disasm::DisassembleMem(u32 insn) {
614{
615 u8 cond = (insn >> 28) & 0xf; 431 u8 cond = (insn >> 28) & 0xf;
616 u8 is_reg = (insn >> 25) & 0x1; 432 u8 is_reg = (insn >> 25) & 0x1;
617 u8 is_load = (insn >> 20) & 0x1; 433 u8 is_load = (insn >> 20) & 0x1;
@@ -623,38 +439,40 @@ std::string ARM_Disasm::DisassembleMem(u32 insn)
623 u8 rd = (insn >> 12) & 0xf; 439 u8 rd = (insn >> 12) & 0xf;
624 u16 offset = insn & 0xfff; 440 u16 offset = insn & 0xfff;
625 441
626 const char *opname = "ldr"; 442 const char* opname = "ldr";
627 if (!is_load) 443 if (!is_load)
628 opname = "str"; 444 opname = "str";
629 445
630 const char *bang = ""; 446 const char* bang = "";
631 if (write_back) 447 if (write_back)
632 bang = "!"; 448 bang = "!";
633 449
634 const char *minus = ""; 450 const char* minus = "";
635 if (is_up == 0) 451 if (is_up == 0)
636 minus = "-"; 452 minus = "-";
637 453
638 const char *byte = ""; 454 const char* byte = "";
639 if (is_byte) 455 if (is_byte)
640 byte = "b"; 456 byte = "b";
641 457
642 if (is_reg == 0) { 458 if (is_reg == 0) {
643 if (is_pre) { 459 if (is_pre) {
644 if (offset == 0) { 460 if (offset == 0) {
645 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", 461 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
646 opname, cond_to_str(cond), byte, rd, rn); 462 byte, rd, rn);
647 } else { 463 } else {
648 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", 464 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
649 opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang); 465 cond_to_str(cond), byte, rd, rn, minus, offset,
466 bang);
650 } 467 }
651 } else { 468 } else {
652 const char *transfer = ""; 469 const char* transfer = "";
653 if (write_back) 470 if (write_back)
654 transfer = "t"; 471 transfer = "t";
655 472
656 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", 473 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", opname,
657 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset); 474 cond_to_str(cond), byte, transfer, rd, rn, minus,
475 offset);
658 } 476 }
659 } 477 }
660 478
@@ -662,48 +480,47 @@ std::string ARM_Disasm::DisassembleMem(u32 insn)
662 u8 shift_type = (insn >> 5) & 0x3; 480 u8 shift_type = (insn >> 5) & 0x3;
663 u8 shift_amount = (insn >> 7) & 0x1f; 481 u8 shift_amount = (insn >> 7) & 0x1f;
664 482
665 const char *shift_name = shift_names[shift_type]; 483 const char* shift_name = shift_names[shift_type];
666 484
667 if (is_pre) { 485 if (is_pre) {
668 if (shift_amount == 0) { 486 if (shift_amount == 0) {
669 if (shift_type == 0) { 487 if (shift_type == 0) {
670 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", 488 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname,
671 opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); 489 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
672 } 490 }
673 if (shift_type == 3) { 491 if (shift_type == 3) {
674 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", 492 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", opname,
675 opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); 493 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
676 } 494 }
677 shift_amount = 32; 495 shift_amount = 32;
678 } 496 }
679 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", 497 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", opname,
680 opname, cond_to_str(cond), byte, rd, rn, minus, rm, 498 cond_to_str(cond), byte, rd, rn, minus, rm, shift_name,
681 shift_name, shift_amount, bang); 499 shift_amount, bang);
682 } 500 }
683 501
684 const char *transfer = ""; 502 const char* transfer = "";
685 if (write_back) 503 if (write_back)
686 transfer = "t"; 504 transfer = "t";
687 505
688 if (shift_amount == 0) { 506 if (shift_amount == 0) {
689 if (shift_type == 0) { 507 if (shift_type == 0) {
690 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", 508 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", opname,
691 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); 509 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
692 } 510 }
693 if (shift_type == 3) { 511 if (shift_type == 3) {
694 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", 512 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", opname,
695 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); 513 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
696 } 514 }
697 shift_amount = 32; 515 shift_amount = 32;
698 } 516 }
699 517
700 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", 518 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", opname,
701 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm, 519 cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
702 shift_name, shift_amount); 520 shift_name, shift_amount);
703} 521}
704 522
705std::string ARM_Disasm::DisassembleMemHalf(u32 insn) 523std::string ARM_Disasm::DisassembleMemHalf(u32 insn) {
706{
707 u8 cond = (insn >> 28) & 0xf; 524 u8 cond = (insn >> 28) & 0xf;
708 u8 is_load = (insn >> 20) & 0x1; 525 u8 is_load = (insn >> 20) & 0x1;
709 u8 write_back = (insn >> 21) & 0x1; 526 u8 write_back = (insn >> 21) & 0x1;
@@ -716,11 +533,11 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
716 u8 rm = insn & 0xf; 533 u8 rm = insn & 0xf;
717 u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf); 534 u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
718 535
719 const char *opname = "ldr"; 536 const char* opname = "ldr";
720 if (is_load == 0) 537 if (is_load == 0)
721 opname = "str"; 538 opname = "str";
722 539
723 const char *width = ""; 540 const char* width = "";
724 if (bits_65 == 1) 541 if (bits_65 == 1)
725 width = "h"; 542 width = "h";
726 else if (bits_65 == 2) 543 else if (bits_65 == 2)
@@ -728,38 +545,39 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
728 else 545 else
729 width = "sh"; 546 width = "sh";
730 547
731 const char *bang = ""; 548 const char* bang = "";
732 if (write_back) 549 if (write_back)
733 bang = "!"; 550 bang = "!";
734 const char *minus = ""; 551 const char* minus = "";
735 if (is_up == 0) 552 if (is_up == 0)
736 minus = "-"; 553 minus = "-";
737 554
738 if (is_immed) { 555 if (is_immed) {
739 if (is_pre) { 556 if (is_pre) {
740 if (offset == 0) { 557 if (offset == 0) {
741 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond), width, rd, rn); 558 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
559 width, rd, rn);
742 } else { 560 } else {
743 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", 561 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
744 opname, cond_to_str(cond), width, rd, rn, minus, offset, bang); 562 cond_to_str(cond), width, rd, rn, minus, offset,
563 bang);
745 } 564 }
746 } else { 565 } else {
747 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", 566 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", opname, cond_to_str(cond),
748 opname, cond_to_str(cond), width, rd, rn, minus, offset); 567 width, rd, rn, minus, offset);
749 } 568 }
750 } 569 }
751 570
752 if (is_pre) { 571 if (is_pre) {
753 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", 572 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, cond_to_str(cond),
754 opname, cond_to_str(cond), width, rd, rn, minus, rm, bang); 573 width, rd, rn, minus, rm, bang);
755 } else { 574 } else {
756 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", 575 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", opname, cond_to_str(cond),
757 opname, cond_to_str(cond), width, rd, rn, minus, rm); 576 width, rd, rn, minus, rm);
758 } 577 }
759} 578}
760 579
761std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) 580std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) {
762{
763 u8 cond = (insn >> 28) & 0xf; 581 u8 cond = (insn >> 28) & 0xf;
764 u8 crn = (insn >> 16) & 0xf; 582 u8 crn = (insn >> 16) & 0xf;
765 u8 crd = (insn >> 12) & 0xf; 583 u8 crd = (insn >> 12) & 0xf;
@@ -767,13 +585,12 @@ std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn)
767 u8 opcode2 = (insn >> 5) & 0x7; 585 u8 opcode2 = (insn >> 5) & 0x7;
768 u8 crm = insn & 0xf; 586 u8 crm = insn & 0xf;
769 587
770 const char *opname = opcode_names[opcode]; 588 const char* opname = opcode_names[opcode];
771 return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", 589 return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", opname, cond_to_str(cond),
772 opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2); 590 cpnum, crd, crn, crm, opcode2);
773} 591}
774 592
775std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) 593std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) {
776{
777 u8 cond = (insn >> 28) & 0xf; 594 u8 cond = (insn >> 28) & 0xf;
778 u8 rd = (insn >> 16) & 0xf; 595 u8 rd = (insn >> 16) & 0xf;
779 u8 rn = (insn >> 12) & 0xf; 596 u8 rn = (insn >> 12) & 0xf;
@@ -781,13 +598,12 @@ std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn)
781 u8 rm = insn & 0xf; 598 u8 rm = insn & 0xf;
782 u8 bit_s = (insn >> 20) & 1; 599 u8 bit_s = (insn >> 20) & 1;
783 600
784 const char *opname = opcode_names[opcode]; 601 const char* opname = opcode_names[opcode];
785 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", 602 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
786 opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn); 603 bit_s ? "s" : "", rd, rm, rs, rn);
787} 604}
788 605
789std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) 606std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) {
790{
791 u8 cond = (insn >> 28) & 0xf; 607 u8 cond = (insn >> 28) & 0xf;
792 u8 rdhi = (insn >> 16) & 0xf; 608 u8 rdhi = (insn >> 16) & 0xf;
793 u8 rdlo = (insn >> 12) & 0xf; 609 u8 rdlo = (insn >> 12) & 0xf;
@@ -795,26 +611,24 @@ std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn)
795 u8 rm = insn & 0xf; 611 u8 rm = insn & 0xf;
796 u8 bit_s = (insn >> 20) & 1; 612 u8 bit_s = (insn >> 20) & 1;
797 613
798 const char *opname = opcode_names[opcode]; 614 const char* opname = opcode_names[opcode];
799 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", 615 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
800 opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs); 616 bit_s ? "s" : "", rdlo, rdhi, rm, rs);
801} 617}
802 618
803std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) 619std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) {
804{
805 u8 cond = (insn >> 28) & 0xf; 620 u8 cond = (insn >> 28) & 0xf;
806 u8 rd = (insn >> 16) & 0xf; 621 u8 rd = (insn >> 16) & 0xf;
807 u8 rs = (insn >> 8) & 0xf; 622 u8 rs = (insn >> 8) & 0xf;
808 u8 rm = insn & 0xf; 623 u8 rm = insn & 0xf;
809 u8 bit_s = (insn >> 20) & 1; 624 u8 bit_s = (insn >> 20) & 1;
810 625
811 const char *opname = opcode_names[opcode]; 626 const char* opname = opcode_names[opcode];
812 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", 627 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", opname, cond_to_str(cond),
813 opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs); 628 bit_s ? "s" : "", rd, rm, rs);
814} 629}
815 630
816std::string ARM_Disasm::DisassembleMRS(u32 insn) 631std::string ARM_Disasm::DisassembleMRS(u32 insn) {
817{
818 u8 cond = (insn >> 28) & 0xf; 632 u8 cond = (insn >> 28) & 0xf;
819 u8 rd = (insn >> 12) & 0xf; 633 u8 rd = (insn >> 12) & 0xf;
820 u8 ps = (insn >> 22) & 1; 634 u8 ps = (insn >> 22) & 1;
@@ -822,8 +636,7 @@ std::string ARM_Disasm::DisassembleMRS(u32 insn)
822 return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr"); 636 return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
823} 637}
824 638
825std::string ARM_Disasm::DisassembleMSR(u32 insn) 639std::string ARM_Disasm::DisassembleMSR(u32 insn) {
826{
827 char flags[8]; 640 char flags[8];
828 int flag_index = 0; 641 int flag_index = 0;
829 u8 cond = (insn >> 28) & 0xf; 642 u8 cond = (insn >> 28) & 0xf;
@@ -846,18 +659,17 @@ std::string ARM_Disasm::DisassembleMSR(u32 insn)
846 u8 rotate = (insn >> 8) & 0xf; 659 u8 rotate = (insn >> 8) & 0xf;
847 u8 rotate2 = rotate << 1; 660 u8 rotate2 = rotate << 1;
848 u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2)); 661 u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
849 return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", 662 return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", cond_to_str(cond),
850 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val); 663 pd ? "spsr" : "cpsr", flags, rotated_val);
851 } 664 }
852 665
853 u8 rm = insn & 0xf; 666 u8 rm = insn & 0xf;
854 667
855 return Common::StringFromFormat("msr%s\t%s_%s, r%d", 668 return Common::StringFromFormat("msr%s\t%s_%s, r%d", cond_to_str(cond), pd ? "spsr" : "cpsr",
856 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm); 669 flags, rm);
857} 670}
858 671
859std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) 672std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) {
860{
861 u32 cond = BITS(insn, 28, 31); 673 u32 cond = BITS(insn, 28, 31);
862 return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond)); 674 return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
863} 675}
@@ -872,8 +684,7 @@ std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
872 rd, rn, rm); 684 rd, rn, rm);
873} 685}
874 686
875std::string ARM_Disasm::DisassemblePKH(u32 insn) 687std::string ARM_Disasm::DisassemblePKH(u32 insn) {
876{
877 u32 cond = BITS(insn, 28, 31); 688 u32 cond = BITS(insn, 28, 31);
878 u32 rn = BITS(insn, 16, 19); 689 u32 rn = BITS(insn, 16, 19);
879 u32 rd = BITS(insn, 12, 15); 690 u32 rd = BITS(insn, 12, 15);
@@ -896,13 +707,12 @@ std::string ARM_Disasm::DisassemblePKH(u32 insn)
896 rd, rn, rm, shift.c_str()); 707 rd, rn, rm, shift.c_str());
897} 708}
898 709
899std::string ARM_Disasm::DisassemblePLD(u32 insn) 710std::string ARM_Disasm::DisassemblePLD(u32 insn) {
900{
901 u8 is_reg = (insn >> 25) & 0x1; 711 u8 is_reg = (insn >> 25) & 0x1;
902 u8 is_up = (insn >> 23) & 0x1; 712 u8 is_up = (insn >> 23) & 0x1;
903 u8 rn = (insn >> 16) & 0xf; 713 u8 rn = (insn >> 16) & 0xf;
904 714
905 const char *minus = ""; 715 const char* minus = "";
906 if (is_up == 0) 716 if (is_up == 0)
907 minus = "-"; 717 minus = "-";
908 718
@@ -924,8 +734,8 @@ std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
924 u32 rd = BITS(insn, 12, 15); 734 u32 rd = BITS(insn, 12, 15);
925 u32 rm = BITS(insn, 0, 3); 735 u32 rm = BITS(insn, 0, 3);
926 736
927 return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), 737 return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), rd,
928 rd, rm); 738 rm);
929} 739}
930 740
931std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) { 741std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
@@ -935,26 +745,26 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
935 u32 cond = BITS(insn, 28, 31); 745 u32 cond = BITS(insn, 28, 31);
936 746
937 switch (opcode) { 747 switch (opcode) {
938 case OP_STREX: 748 case OP_STREX:
939 case OP_STREXB: 749 case OP_STREXB:
940 case OP_STREXH: 750 case OP_STREXH:
941 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], 751 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
942 cond_to_str(cond), rd, rt, rn); 752 cond_to_str(cond), rd, rt, rn);
943 case OP_STREXD: 753 case OP_STREXD:
944 return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode], 754 return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
945 cond_to_str(cond), rd, rt, rt + 1, rn); 755 cond_to_str(cond), rd, rt, rt + 1, rn);
946 756
947 // for LDREX instructions, rd corresponds to Rt from reference manual 757 // for LDREX instructions, rd corresponds to Rt from reference manual
948 case OP_LDREX: 758 case OP_LDREX:
949 case OP_LDREXB: 759 case OP_LDREXB:
950 case OP_LDREXH: 760 case OP_LDREXH:
951 return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], 761 return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], cond_to_str(cond),
952 cond_to_str(cond), rd, rn); 762 rd, rn);
953 case OP_LDREXD: 763 case OP_LDREXD:
954 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], 764 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
955 cond_to_str(cond), rd, rd + 1, rn); 765 cond_to_str(cond), rd, rd + 1, rn);
956 default: 766 default:
957 return opcode_names[OP_UNDEFINED]; 767 return opcode_names[OP_UNDEFINED];
958 } 768 }
959} 769}
960 770
@@ -982,8 +792,8 @@ std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
982 if (opcode == OP_SSAT || opcode == OP_SSAT16) 792 if (opcode == OP_SSAT || opcode == OP_SSAT16)
983 sat_imm++; 793 sat_imm++;
984 794
985 return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], cond_to_str(cond), rd, 795 return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode],
986 sat_imm, rn, shift_part.c_str()); 796 cond_to_str(cond), rd, sat_imm, rn, shift_part.c_str());
987} 797}
988 798
989std::string ARM_Disasm::DisassembleSEL(u32 insn) { 799std::string ARM_Disasm::DisassembleSEL(u32 insn) {
@@ -996,27 +806,24 @@ std::string ARM_Disasm::DisassembleSEL(u32 insn) {
996 rd, rn, rm); 806 rd, rn, rm);
997} 807}
998 808
999std::string ARM_Disasm::DisassembleSWI(u32 insn) 809std::string ARM_Disasm::DisassembleSWI(u32 insn) {
1000{
1001 u8 cond = (insn >> 28) & 0xf; 810 u8 cond = (insn >> 28) & 0xf;
1002 u32 sysnum = insn & 0x00ffffff; 811 u32 sysnum = insn & 0x00ffffff;
1003 812
1004 return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum); 813 return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
1005} 814}
1006 815
1007std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) 816std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) {
1008{
1009 u8 cond = (insn >> 28) & 0xf; 817 u8 cond = (insn >> 28) & 0xf;
1010 u8 rn = (insn >> 16) & 0xf; 818 u8 rn = (insn >> 16) & 0xf;
1011 u8 rd = (insn >> 12) & 0xf; 819 u8 rd = (insn >> 12) & 0xf;
1012 u8 rm = insn & 0xf; 820 u8 rm = insn & 0xf;
1013 821
1014 const char *opname = opcode_names[opcode]; 822 const char* opname = opcode_names[opcode];
1015 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn); 823 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
1016} 824}
1017 825
1018std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) 826std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) {
1019{
1020 u32 cond = BITS(insn, 28, 31); 827 u32 cond = BITS(insn, 28, 31);
1021 u32 rn = BITS(insn, 16, 19); 828 u32 rn = BITS(insn, 16, 19);
1022 u32 rd = BITS(insn, 12, 15); 829 u32 rd = BITS(insn, 12, 15);
@@ -1025,9 +832,7 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
1025 832
1026 std::string rn_part = ""; 833 std::string rn_part = "";
1027 static std::unordered_set<Opcode, std::hash<int>> extend_with_add = { 834 static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
1028 OP_SXTAB, OP_SXTAB16, OP_SXTAH, 835 OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_UXTAB, OP_UXTAB16, OP_UXTAH};
1029 OP_UXTAB, OP_UXTAB16, OP_UXTAH
1030 };
1031 if (extend_with_add.find(opcode) != extend_with_add.end()) 836 if (extend_with_add.find(opcode) != extend_with_add.end())
1032 rn_part = ", r" + std::to_string(rn); 837 rn_part = ", r" + std::to_string(rn);
1033 838
@@ -1042,14 +847,14 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
1042Opcode ARM_Disasm::Decode(u32 insn) { 847Opcode ARM_Disasm::Decode(u32 insn) {
1043 u32 bits27_26 = (insn >> 26) & 0x3; 848 u32 bits27_26 = (insn >> 26) & 0x3;
1044 switch (bits27_26) { 849 switch (bits27_26) {
1045 case 0x0: 850 case 0x0:
1046 return Decode00(insn); 851 return Decode00(insn);
1047 case 0x1: 852 case 0x1:
1048 return Decode01(insn); 853 return Decode01(insn);
1049 case 0x2: 854 case 0x2:
1050 return Decode10(insn); 855 return Decode10(insn);
1051 case 0x3: 856 case 0x3:
1052 return Decode11(insn); 857 return Decode11(insn);
1053 } 858 }
1054 return OP_INVALID; 859 return OP_INVALID;
1055} 860}
@@ -1198,28 +1003,28 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
1198 u32 op = BITS(insn, 20, 23); 1003 u32 op = BITS(insn, 20, 23);
1199 u32 bit22 = BIT(insn, 22); 1004 u32 bit22 = BIT(insn, 22);
1200 switch (op) { 1005 switch (op) {
1201 case 0x0: 1006 case 0x0:
1202 if (bit22) 1007 if (bit22)
1203 return OP_SWPB; 1008 return OP_SWPB;
1204 return OP_SWP; 1009 return OP_SWP;
1205 case 0x8: 1010 case 0x8:
1206 return OP_STREX; 1011 return OP_STREX;
1207 case 0x9: 1012 case 0x9:
1208 return OP_LDREX; 1013 return OP_LDREX;
1209 case 0xA: 1014 case 0xA:
1210 return OP_STREXD; 1015 return OP_STREXD;
1211 case 0xB: 1016 case 0xB:
1212 return OP_LDREXD; 1017 return OP_LDREXD;
1213 case 0xC: 1018 case 0xC:
1214 return OP_STREXB; 1019 return OP_STREXB;
1215 case 0xD: 1020 case 0xD:
1216 return OP_LDREXB; 1021 return OP_LDREXB;
1217 case 0xE: 1022 case 0xE:
1218 return OP_STREXH; 1023 return OP_STREXH;
1219 case 0xF: 1024 case 0xF:
1220 return OP_LDREXH; 1025 return OP_LDREXH;
1221 default: 1026 default:
1222 return OP_UNDEFINED; 1027 return OP_UNDEFINED;
1223 } 1028 }
1224} 1029}
1225 1030
@@ -1240,27 +1045,14 @@ Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
1240 1045
1241 static std::vector<Opcode> opcodes = { 1046 static std::vector<Opcode> opcodes = {
1242 // op1 = 0 1047 // op1 = 0
1243 OP_SADD16, OP_UADD16, 1048 OP_SADD16, OP_UADD16, OP_SASX, OP_UASX, OP_SSAX, OP_USAX, OP_SSUB16, OP_USUB16, OP_SADD8,
1244 OP_SASX, OP_UASX, 1049 OP_UADD8, OP_SSUB8, OP_USUB8,
1245 OP_SSAX, OP_USAX,
1246 OP_SSUB16, OP_USUB16,
1247 OP_SADD8, OP_UADD8,
1248 OP_SSUB8, OP_USUB8,
1249 // op1 = 1 1050 // op1 = 1
1250 OP_QADD16, OP_UQADD16, 1051 OP_QADD16, OP_UQADD16, OP_QASX, OP_UQASX, OP_QSAX, OP_UQSAX, OP_QSUB16, OP_UQSUB16,
1251 OP_QASX, OP_UQASX, 1052 OP_QADD8, OP_UQADD8, OP_QSUB8, OP_UQSUB8,
1252 OP_QSAX, OP_UQSAX,
1253 OP_QSUB16, OP_UQSUB16,
1254 OP_QADD8, OP_UQADD8,
1255 OP_QSUB8, OP_UQSUB8,
1256 // op1 = 2 1053 // op1 = 2
1257 OP_SHADD16, OP_UHADD16, 1054 OP_SHADD16, OP_UHADD16, OP_SHASX, OP_UHASX, OP_SHSAX, OP_UHSAX, OP_SHSUB16, OP_UHSUB16,
1258 OP_SHASX, OP_UHASX, 1055 OP_SHADD8, OP_UHADD8, OP_SHSUB8, OP_UHSUB8};
1259 OP_SHSAX, OP_UHSAX,
1260 OP_SHSUB16, OP_UHSUB16,
1261 OP_SHADD8, OP_UHADD8,
1262 OP_SHSUB8, OP_UHSUB8
1263 };
1264 1056
1265 u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned; 1057 u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
1266 return opcodes[opcode_index]; 1058 return opcodes[opcode_index];
@@ -1272,66 +1064,66 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
1272 u32 op2 = BITS(insn, 5, 7); 1064 u32 op2 = BITS(insn, 5, 7);
1273 1065
1274 switch (op1) { 1066 switch (op1) {
1275 case 0x0: 1067 case 0x0:
1276 if (BIT(op2, 0) == 0) 1068 if (BIT(op2, 0) == 0)
1277 return OP_PKH; 1069 return OP_PKH;
1278 if (op2 == 0x3 && a != 0xf) 1070 if (op2 == 0x3 && a != 0xf)
1279 return OP_SXTAB16; 1071 return OP_SXTAB16;
1280 if (op2 == 0x3 && a == 0xf) 1072 if (op2 == 0x3 && a == 0xf)
1281 return OP_SXTB16; 1073 return OP_SXTB16;
1282 if (op2 == 0x5) 1074 if (op2 == 0x5)
1283 return OP_SEL; 1075 return OP_SEL;
1284 break; 1076 break;
1285 case 0x2: 1077 case 0x2:
1286 if (BIT(op2, 0) == 0) 1078 if (BIT(op2, 0) == 0)
1287 return OP_SSAT; 1079 return OP_SSAT;
1288 if (op2 == 0x1) 1080 if (op2 == 0x1)
1289 return OP_SSAT16; 1081 return OP_SSAT16;
1290 if (op2 == 0x3 && a != 0xf) 1082 if (op2 == 0x3 && a != 0xf)
1291 return OP_SXTAB; 1083 return OP_SXTAB;
1292 if (op2 == 0x3 && a == 0xf) 1084 if (op2 == 0x3 && a == 0xf)
1293 return OP_SXTB; 1085 return OP_SXTB;
1294 break; 1086 break;
1295 case 0x3: 1087 case 0x3:
1296 if (op2 == 0x1) 1088 if (op2 == 0x1)
1297 return OP_REV; 1089 return OP_REV;
1298 if (BIT(op2, 0) == 0) 1090 if (BIT(op2, 0) == 0)
1299 return OP_SSAT; 1091 return OP_SSAT;
1300 if (op2 == 0x3 && a != 0xf) 1092 if (op2 == 0x3 && a != 0xf)
1301 return OP_SXTAH; 1093 return OP_SXTAH;
1302 if (op2 == 0x3 && a == 0xf) 1094 if (op2 == 0x3 && a == 0xf)
1303 return OP_SXTH; 1095 return OP_SXTH;
1304 if (op2 == 0x5) 1096 if (op2 == 0x5)
1305 return OP_REV16; 1097 return OP_REV16;
1306 break; 1098 break;
1307 case 0x4: 1099 case 0x4:
1308 if (op2 == 0x3 && a != 0xf) 1100 if (op2 == 0x3 && a != 0xf)
1309 return OP_UXTAB16; 1101 return OP_UXTAB16;
1310 if (op2 == 0x3 && a == 0xf) 1102 if (op2 == 0x3 && a == 0xf)
1311 return OP_UXTB16; 1103 return OP_UXTB16;
1312 break; 1104 break;
1313 case 0x6: 1105 case 0x6:
1314 if (BIT(op2, 0) == 0) 1106 if (BIT(op2, 0) == 0)
1315 return OP_USAT; 1107 return OP_USAT;
1316 if (op2 == 0x1) 1108 if (op2 == 0x1)
1317 return OP_USAT16; 1109 return OP_USAT16;
1318 if (op2 == 0x3 && a != 0xf) 1110 if (op2 == 0x3 && a != 0xf)
1319 return OP_UXTAB; 1111 return OP_UXTAB;
1320 if (op2 == 0x3 && a == 0xf) 1112 if (op2 == 0x3 && a == 0xf)
1321 return OP_UXTB; 1113 return OP_UXTB;
1322 break; 1114 break;
1323 case 0x7: 1115 case 0x7:
1324 if (BIT(op2, 0) == 0) 1116 if (BIT(op2, 0) == 0)
1325 return OP_USAT; 1117 return OP_USAT;
1326 if (op2 == 0x3 && a != 0xf) 1118 if (op2 == 0x3 && a != 0xf)
1327 return OP_UXTAH; 1119 return OP_UXTAH;
1328 if (op2 == 0x3 && a == 0xf) 1120 if (op2 == 0x3 && a == 0xf)
1329 return OP_UXTH; 1121 return OP_UXTH;
1330 if (op2 == 0x5) 1122 if (op2 == 0x5)
1331 return OP_REVSH; 1123 return OP_REVSH;
1332 break; 1124 break;
1333 default: 1125 default:
1334 break; 1126 break;
1335 } 1127 }
1336 1128
1337 return OP_UNDEFINED; 1129 return OP_UNDEFINED;
@@ -1378,18 +1170,18 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
1378 1170
1379 if (op == 0 && op1 == 0) { 1171 if (op == 0 && op1 == 0) {
1380 switch (op2) { 1172 switch (op2) {
1381 case 0x0: 1173 case 0x0:
1382 return OP_NOP; 1174 return OP_NOP;
1383 case 0x1: 1175 case 0x1:
1384 return OP_YIELD; 1176 return OP_YIELD;
1385 case 0x2: 1177 case 0x2:
1386 return OP_WFE; 1178 return OP_WFE;
1387 case 0x3: 1179 case 0x3:
1388 return OP_WFI; 1180 return OP_WFI;
1389 case 0x4: 1181 case 0x4:
1390 return OP_SEV; 1182 return OP_SEV;
1391 default: 1183 default:
1392 return OP_UNDEFINED; 1184 return OP_UNDEFINED;
1393 } 1185 }
1394 } 1186 }
1395 1187
@@ -1402,37 +1194,37 @@ Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
1402 u32 a = BITS(insn, 12, 15); 1194 u32 a = BITS(insn, 12, 15);
1403 1195
1404 switch (op1) { 1196 switch (op1) {
1405 case 0x0: 1197 case 0x0:
1406 if (op2_h == 0x0) { 1198 if (op2_h == 0x0) {
1407 if (a != 0xf) 1199 if (a != 0xf)
1408 return OP_SMLAD; 1200 return OP_SMLAD;
1409 else 1201 else
1410 return OP_SMUAD; 1202 return OP_SMUAD;
1411 } else if (op2_h == 0x1) { 1203 } else if (op2_h == 0x1) {
1412 if (a != 0xf) 1204 if (a != 0xf)
1413 return OP_SMLSD; 1205 return OP_SMLSD;
1414 else 1206 else
1415 return OP_SMUSD; 1207 return OP_SMUSD;
1416 } 1208 }
1417 break; 1209 break;
1418 case 0x4: 1210 case 0x4:
1419 if (op2_h == 0x0) 1211 if (op2_h == 0x0)
1420 return OP_SMLALD; 1212 return OP_SMLALD;
1421 else if (op2_h == 0x1) 1213 else if (op2_h == 0x1)
1422 return OP_SMLSLD; 1214 return OP_SMLSLD;
1423 break; 1215 break;
1424 case 0x5: 1216 case 0x5:
1425 if (op2_h == 0x0) { 1217 if (op2_h == 0x0) {
1426 if (a != 0xf) 1218 if (a != 0xf)
1427 return OP_SMMLA; 1219 return OP_SMMLA;
1428 else 1220 else
1429 return OP_SMMUL; 1221 return OP_SMMUL;
1430 } else if (op2_h == 0x3) { 1222 } else if (op2_h == 0x3) {
1431 return OP_SMMLS; 1223 return OP_SMMLS;
1432 } 1224 }
1433 break; 1225 break;
1434 default: 1226 default:
1435 break; 1227 break;
1436 } 1228 }
1437 1229
1438 return OP_UNDEFINED; 1230 return OP_UNDEFINED;
@@ -1444,23 +1236,23 @@ Opcode ARM_Disasm::DecodeMedia(u32 insn) {
1444 u32 op2 = BITS(insn, 5, 7); 1236 u32 op2 = BITS(insn, 5, 7);
1445 1237
1446 switch (BITS(op1, 3, 4)) { 1238 switch (BITS(op1, 3, 4)) {
1447 case 0x0: 1239 case 0x0:
1448 // unsigned and signed parallel addition and subtraction 1240 // unsigned and signed parallel addition and subtraction
1449 return DecodeParallelAddSub(insn); 1241 return DecodeParallelAddSub(insn);
1450 case 0x1: 1242 case 0x1:
1451 // Packing, unpacking, saturation, and reversal 1243 // Packing, unpacking, saturation, and reversal
1452 return DecodePackingSaturationReversal(insn); 1244 return DecodePackingSaturationReversal(insn);
1453 case 0x2: 1245 case 0x2:
1454 // Signed multiply, signed and unsigned divide 1246 // Signed multiply, signed and unsigned divide
1455 return DecodeMediaMulDiv(insn); 1247 return DecodeMediaMulDiv(insn);
1456 case 0x3: 1248 case 0x3:
1457 if (op2 == 0 && rd == 0xf) 1249 if (op2 == 0 && rd == 0xf)
1458 return OP_USAD8; 1250 return OP_USAD8;
1459 if (op2 == 0 && rd != 0xf) 1251 if (op2 == 0 && rd != 0xf)
1460 return OP_USADA8; 1252 return OP_USADA8;
1461 break; 1253 break;
1462 default: 1254 default:
1463 break; 1255 break;
1464 } 1256 }
1465 1257
1466 return OP_UNDEFINED; 1258 return OP_UNDEFINED;
@@ -1508,46 +1300,46 @@ Opcode ARM_Disasm::DecodeALU(u32 insn) {
1508 return OP_UNDEFINED; 1300 return OP_UNDEFINED;
1509 } 1301 }
1510 switch (opcode) { 1302 switch (opcode) {
1511 case 0x0: 1303 case 0x0:
1512 return OP_AND; 1304 return OP_AND;
1513 case 0x1: 1305 case 0x1:
1514 return OP_EOR; 1306 return OP_EOR;
1515 case 0x2: 1307 case 0x2:
1516 return OP_SUB; 1308 return OP_SUB;
1517 case 0x3: 1309 case 0x3:
1518 return OP_RSB; 1310 return OP_RSB;
1519 case 0x4: 1311 case 0x4:
1520 return OP_ADD; 1312 return OP_ADD;
1521 case 0x5: 1313 case 0x5:
1522 return OP_ADC; 1314 return OP_ADC;
1523 case 0x6: 1315 case 0x6:
1524 return OP_SBC; 1316 return OP_SBC;
1525 case 0x7: 1317 case 0x7:
1526 return OP_RSC; 1318 return OP_RSC;
1527 case 0x8: 1319 case 0x8:
1528 if (bit_s) 1320 if (bit_s)
1529 return OP_TST; 1321 return OP_TST;
1530 return OP_MRS; 1322 return OP_MRS;
1531 case 0x9: 1323 case 0x9:
1532 if (bit_s) 1324 if (bit_s)
1533 return OP_TEQ; 1325 return OP_TEQ;
1534 return OP_MSR; 1326 return OP_MSR;
1535 case 0xa: 1327 case 0xa:
1536 if (bit_s) 1328 if (bit_s)
1537 return OP_CMP; 1329 return OP_CMP;
1538 return OP_MRS; 1330 return OP_MRS;
1539 case 0xb: 1331 case 0xb:
1540 if (bit_s) 1332 if (bit_s)
1541 return OP_CMN; 1333 return OP_CMN;
1542 return OP_MSR; 1334 return OP_MSR;
1543 case 0xc: 1335 case 0xc:
1544 return OP_ORR; 1336 return OP_ORR;
1545 case 0xd: 1337 case 0xd:
1546 return OP_MOV; 1338 return OP_MOV;
1547 case 0xe: 1339 case 0xe:
1548 return OP_BIC; 1340 return OP_BIC;
1549 case 0xf: 1341 case 0xf:
1550 return OP_MVN; 1342 return OP_MVN;
1551 } 1343 }
1552 // Unreachable 1344 // Unreachable
1553 return OP_INVALID; 1345 return OP_INVALID;
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h
index 53d9c6a74..031f973d6 100644
--- a/src/core/arm/disassembler/arm_disasm.h
+++ b/src/core/arm/disassembler/arm_disasm.h
@@ -187,53 +187,53 @@ enum Opcode {
187 OP_THUMB_SWI, 187 OP_THUMB_SWI,
188 OP_THUMB_TST, 188 OP_THUMB_TST,
189 189
190 OP_END // must be last 190 OP_END // must be last
191}; 191};
192 192
193class ARM_Disasm { 193class ARM_Disasm {
194 public: 194public:
195 static std::string Disassemble(u32 addr, u32 insn); 195 static std::string Disassemble(u32 addr, u32 insn);
196 static Opcode Decode(u32 insn); 196 static Opcode Decode(u32 insn);
197 197
198 private: 198private:
199 static Opcode Decode00(u32 insn); 199 static Opcode Decode00(u32 insn);
200 static Opcode Decode01(u32 insn); 200 static Opcode Decode01(u32 insn);
201 static Opcode Decode10(u32 insn); 201 static Opcode Decode10(u32 insn);
202 static Opcode Decode11(u32 insn); 202 static Opcode Decode11(u32 insn);
203 static Opcode DecodeSyncPrimitive(u32 insn); 203 static Opcode DecodeSyncPrimitive(u32 insn);
204 static Opcode DecodeParallelAddSub(u32 insn); 204 static Opcode DecodeParallelAddSub(u32 insn);
205 static Opcode DecodePackingSaturationReversal(u32 insn); 205 static Opcode DecodePackingSaturationReversal(u32 insn);
206 static Opcode DecodeMUL(u32 insn); 206 static Opcode DecodeMUL(u32 insn);
207 static Opcode DecodeMSRImmAndHints(u32 insn); 207 static Opcode DecodeMSRImmAndHints(u32 insn);
208 static Opcode DecodeMediaMulDiv(u32 insn); 208 static Opcode DecodeMediaMulDiv(u32 insn);
209 static Opcode DecodeMedia(u32 insn); 209 static Opcode DecodeMedia(u32 insn);
210 static Opcode DecodeLDRH(u32 insn); 210 static Opcode DecodeLDRH(u32 insn);
211 static Opcode DecodeALU(u32 insn); 211 static Opcode DecodeALU(u32 insn);
212 212
213 static std::string DisassembleALU(Opcode opcode, u32 insn); 213 static std::string DisassembleALU(Opcode opcode, u32 insn);
214 static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn); 214 static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
215 static std::string DisassembleBX(u32 insn); 215 static std::string DisassembleBX(u32 insn);
216 static std::string DisassembleBKPT(u32 insn); 216 static std::string DisassembleBKPT(u32 insn);
217 static std::string DisassembleCLZ(u32 insn); 217 static std::string DisassembleCLZ(u32 insn);
218 static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn); 218 static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
219 static std::string DisassembleMemblock(Opcode opcode, u32 insn); 219 static std::string DisassembleMemblock(Opcode opcode, u32 insn);
220 static std::string DisassembleMem(u32 insn); 220 static std::string DisassembleMem(u32 insn);
221 static std::string DisassembleMemHalf(u32 insn); 221 static std::string DisassembleMemHalf(u32 insn);
222 static std::string DisassembleMCR(Opcode opcode, u32 insn); 222 static std::string DisassembleMCR(Opcode opcode, u32 insn);
223 static std::string DisassembleMLA(Opcode opcode, u32 insn); 223 static std::string DisassembleMLA(Opcode opcode, u32 insn);
224 static std::string DisassembleUMLAL(Opcode opcode, u32 insn); 224 static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
225 static std::string DisassembleMUL(Opcode opcode, u32 insn); 225 static std::string DisassembleMUL(Opcode opcode, u32 insn);
226 static std::string DisassembleMRS(u32 insn); 226 static std::string DisassembleMRS(u32 insn);
227 static std::string DisassembleMSR(u32 insn); 227 static std::string DisassembleMSR(u32 insn);
228 static std::string DisassembleNoOperands(Opcode opcode, u32 insn); 228 static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
229 static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn); 229 static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
230 static std::string DisassemblePKH(u32 insn); 230 static std::string DisassemblePKH(u32 insn);
231 static std::string DisassemblePLD(u32 insn); 231 static std::string DisassemblePLD(u32 insn);
232 static std::string DisassembleREV(Opcode opcode, u32 insn); 232 static std::string DisassembleREV(Opcode opcode, u32 insn);
233 static std::string DisassembleREX(Opcode opcode, u32 insn); 233 static std::string DisassembleREX(Opcode opcode, u32 insn);
234 static std::string DisassembleSAT(Opcode opcode, u32 insn); 234 static std::string DisassembleSAT(Opcode opcode, u32 insn);
235 static std::string DisassembleSEL(u32 insn); 235 static std::string DisassembleSEL(u32 insn);
236 static std::string DisassembleSWI(u32 insn); 236 static std::string DisassembleSWI(u32 insn);
237 static std::string DisassembleSWP(Opcode opcode, u32 insn); 237 static std::string DisassembleSWP(Opcode opcode, u32 insn);
238 static std::string DisassembleXT(Opcode opcode, u32 insn); 238 static std::string DisassembleXT(Opcode opcode, u32 insn);
239}; 239};
diff --git a/src/core/arm/disassembler/load_symbol_map.cpp b/src/core/arm/disassembler/load_symbol_map.cpp
index eb20bf6f7..58e8e6fa1 100644
--- a/src/core/arm/disassembler/load_symbol_map.cpp
+++ b/src/core/arm/disassembler/load_symbol_map.cpp
@@ -6,8 +6,8 @@
6#include <string> 6#include <string>
7#include <vector> 7#include <vector>
8 8
9#include "common/symbols.h"
10#include "common/file_util.h" 9#include "common/file_util.h"
10#include "common/symbols.h"
11 11
12#include "core/arm/disassembler/load_symbol_map.h" 12#include "core/arm/disassembler/load_symbol_map.h"
13 13
HIC SVNT DRACONES