summaryrefslogtreecommitdiff
path: root/src/core/arm/disassembler
diff options
context:
space:
mode:
authorGravatar Yuri Kunde Schlesner2016-09-21 11:29:48 -0700
committerGravatar GitHub2016-09-21 11:29:48 -0700
commitd5d2ca8058a0f1c00ab7ca9fe2c058ba47546c0a (patch)
tree8a22ca73ff838f3f0090b29a548ae81087fc90ed /src/core/arm/disassembler
parentREADME: Specify master branch for Travis CI badge (diff)
parentFix Travis clang-format check (diff)
downloadyuzu-d5d2ca8058a0f1c00ab7ca9fe2c058ba47546c0a.tar.gz
yuzu-d5d2ca8058a0f1c00ab7ca9fe2c058ba47546c0a.tar.xz
yuzu-d5d2ca8058a0f1c00ab7ca9fe2c058ba47546c0a.zip
Merge pull request #2086 from linkmauve/clang-format
Add clang-format as part of our {commit,travis}-time checks
Diffstat (limited to 'src/core/arm/disassembler')
-rw-r--r--src/core/arm/disassembler/arm_disasm.cpp1292
-rw-r--r--src/core/arm/disassembler/arm_disasm.h89
-rw-r--r--src/core/arm/disassembler/load_symbol_map.cpp4
3 files changed, 586 insertions, 799 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp
index 5ad1f1c29..05d6ed1fb 100644
--- a/src/core/arm/disassembler/arm_disasm.cpp
+++ b/src/core/arm/disassembler/arm_disasm.cpp
@@ -2,408 +2,230 @@
2 2
3#include <string> 3#include <string>
4#include <unordered_set> 4#include <unordered_set>
5
6#include "common/common_types.h" 5#include "common/common_types.h"
7#include "common/string_util.h" 6#include "common/string_util.h"
8
9#include "core/arm/disassembler/arm_disasm.h" 7#include "core/arm/disassembler/arm_disasm.h"
10#include "core/arm/skyeye_common/armsupp.h" 8#include "core/arm/skyeye_common/armsupp.h"
11 9
12static const char *cond_names[] = { 10static const char* cond_names[] = {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
13 "eq", 11 "hi", "ls", "ge", "lt", "gt", "le", "", "RESERVED"};
14 "ne", 12
15 "cs", 13static const char* opcode_names[] = {
16 "cc", 14 "invalid", "undefined", "adc", "add", "and", "b", "bl", "bic",
17 "mi", 15 "bkpt", "blx", "bx", "cdp", "clrex", "clz", "cmn", "cmp",
18 "pl", 16 "eor", "ldc", "ldm", "ldr", "ldrb", "ldrbt", "ldrex", "ldrexb",
19 "vs", 17 "ldrexd", "ldrexh", "ldrh", "ldrsb", "ldrsh", "ldrt", "mcr", "mla",
20 "vc", 18 "mov", "mrc", "mrs", "msr", "mul", "mvn", "nop", "orr",
21 "hi", 19 "pkh", "pld", "qadd16", "qadd8", "qasx", "qsax", "qsub16", "qsub8",
22 "ls", 20 "rev", "rev16", "revsh", "rsb", "rsc", "sadd16", "sadd8", "sasx",
23 "ge", 21 "sbc", "sel", "sev", "shadd16", "shadd8", "shasx", "shsax", "shsub16",
24 "lt", 22 "shsub8", "smlad", "smlal", "smlald", "smlsd", "smlsld", "smmla", "smmls",
25 "gt", 23 "smmul", "smuad", "smull", "smusd", "ssat", "ssat16", "ssax", "ssub16",
26 "le", 24 "ssub8", "stc", "stm", "str", "strb", "strbt", "strex", "strexb",
27 "", 25 "strexd", "strexh", "strh", "strt", "sub", "swi", "swp", "swpb",
28 "RESERVED" 26 "sxtab", "sxtab16", "sxtah", "sxtb", "sxtb16", "sxth", "teq", "tst",
29}; 27 "uadd16", "uadd8", "uasx", "uhadd16", "uhadd8", "uhasx", "uhsax", "uhsub16",
30 28 "uhsub8", "umlal", "umull", "uqadd16", "uqadd8", "uqasx", "uqsax", "uqsub16",
31static const char *opcode_names[] = { 29 "uqsub8", "usad8", "usada8", "usat", "usat16", "usax", "usub16", "usub8",
32 "invalid", 30 "uxtab", "uxtab16", "uxtah", "uxtb", "uxtb16", "uxth", "wfe", "wfi",
33 "undefined",
34 "adc",
35 "add",
36 "and",
37 "b",
38 "bl",
39 "bic",
40 "bkpt",
41 "blx",
42 "bx",
43 "cdp",
44 "clrex",
45 "clz",
46 "cmn",
47 "cmp",
48 "eor",
49 "ldc",
50 "ldm",
51 "ldr",
52 "ldrb",
53 "ldrbt",
54 "ldrex",
55 "ldrexb",
56 "ldrexd",
57 "ldrexh",
58 "ldrh",
59 "ldrsb",
60 "ldrsh",
61 "ldrt",
62 "mcr",
63 "mla",
64 "mov",
65 "mrc",
66 "mrs",
67 "msr",
68 "mul",
69 "mvn",
70 "nop",
71 "orr",
72 "pkh",
73 "pld",
74 "qadd16",
75 "qadd8",
76 "qasx",
77 "qsax",
78 "qsub16",
79 "qsub8",
80 "rev",
81 "rev16",
82 "revsh",
83 "rsb",
84 "rsc",
85 "sadd16",
86 "sadd8",
87 "sasx",
88 "sbc",
89 "sel",
90 "sev",
91 "shadd16",
92 "shadd8",
93 "shasx",
94 "shsax",
95 "shsub16",
96 "shsub8",
97 "smlad",
98 "smlal",
99 "smlald",
100 "smlsd",
101 "smlsld",
102 "smmla",
103 "smmls",
104 "smmul",
105 "smuad",
106 "smull",
107 "smusd",
108 "ssat",
109 "ssat16",
110 "ssax",
111 "ssub16",
112 "ssub8",
113 "stc",
114 "stm",
115 "str",
116 "strb",
117 "strbt",
118 "strex",
119 "strexb",
120 "strexd",
121 "strexh",
122 "strh",
123 "strt",
124 "sub",
125 "swi",
126 "swp",
127 "swpb",
128 "sxtab",
129 "sxtab16",
130 "sxtah",
131 "sxtb",
132 "sxtb16",
133 "sxth",
134 "teq",
135 "tst",
136 "uadd16",
137 "uadd8",
138 "uasx",
139 "uhadd16",
140 "uhadd8",
141 "uhasx",
142 "uhsax",
143 "uhsub16",
144 "uhsub8",
145 "umlal",
146 "umull",
147 "uqadd16",
148 "uqadd8",
149 "uqasx",
150 "uqsax",
151 "uqsub16",
152 "uqsub8",
153 "usad8",
154 "usada8",
155 "usat",
156 "usat16",
157 "usax",
158 "usub16",
159 "usub8",
160 "uxtab",
161 "uxtab16",
162 "uxtah",
163 "uxtb",
164 "uxtb16",
165 "uxth",
166 "wfe",
167 "wfi",
168 "yield", 31 "yield",
169 32
170 "undefined", 33 "undefined", "adc", "add", "and", "asr", "b", "bic", "bkpt",
171 "adc", 34 "bl", "blx", "bx", "cmn", "cmp", "eor", "ldmia", "ldr",
172 "add", 35 "ldrb", "ldrh", "ldrsb", "ldrsh", "lsl", "lsr", "mov", "mul",
173 "and", 36 "mvn", "neg", "orr", "pop", "push", "ror", "sbc", "stmia",
174 "asr", 37 "str", "strb", "strh", "sub", "swi", "tst",
175 "b", 38
176 "bic", 39 nullptr};
177 "bkpt",
178 "bl",
179 "blx",
180 "bx",
181 "cmn",
182 "cmp",
183 "eor",
184 "ldmia",
185 "ldr",
186 "ldrb",
187 "ldrh",
188 "ldrsb",
189 "ldrsh",
190 "lsl",
191 "lsr",
192 "mov",
193 "mul",
194 "mvn",
195 "neg",
196 "orr",
197 "pop",
198 "push",
199 "ror",
200 "sbc",
201 "stmia",
202 "str",
203 "strb",
204 "strh",
205 "sub",
206 "swi",
207 "tst",
208
209 nullptr
210};
211 40
212// Indexed by the shift type (bits 6-5) 41// Indexed by the shift type (bits 6-5)
213static const char *shift_names[] = { 42static const char* shift_names[] = {"LSL", "LSR", "ASR", "ROR"};
214 "LSL",
215 "LSR",
216 "ASR",
217 "ROR"
218};
219 43
220static const char* cond_to_str(u32 cond) { 44static const char* cond_to_str(u32 cond) {
221 return cond_names[cond]; 45 return cond_names[cond];
222} 46}
223 47
224std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) 48std::string ARM_Disasm::Disassemble(u32 addr, u32 insn) {
225{
226 Opcode opcode = Decode(insn); 49 Opcode opcode = Decode(insn);
227 switch (opcode) { 50 switch (opcode) {
228 case OP_INVALID: 51 case OP_INVALID:
229 return "Invalid"; 52 return "Invalid";
230 case OP_UNDEFINED: 53 case OP_UNDEFINED:
231 return "Undefined"; 54 return "Undefined";
232 case OP_ADC: 55 case OP_ADC:
233 case OP_ADD: 56 case OP_ADD:
234 case OP_AND: 57 case OP_AND:
235 case OP_BIC: 58 case OP_BIC:
236 case OP_CMN: 59 case OP_CMN:
237 case OP_CMP: 60 case OP_CMP:
238 case OP_EOR: 61 case OP_EOR:
239 case OP_MOV: 62 case OP_MOV:
240 case OP_MVN: 63 case OP_MVN:
241 case OP_ORR: 64 case OP_ORR:
242 case OP_RSB: 65 case OP_RSB:
243 case OP_RSC: 66 case OP_RSC:
244 case OP_SBC: 67 case OP_SBC:
245 case OP_SUB: 68 case OP_SUB:
246 case OP_TEQ: 69 case OP_TEQ:
247 case OP_TST: 70 case OP_TST:
248 return DisassembleALU(opcode, insn); 71 return DisassembleALU(opcode, insn);
249 case OP_B: 72 case OP_B:
250 case OP_BL: 73 case OP_BL:
251 return DisassembleBranch(addr, opcode, insn); 74 return DisassembleBranch(addr, opcode, insn);
252 case OP_BKPT: 75 case OP_BKPT:
253 return DisassembleBKPT(insn); 76 return DisassembleBKPT(insn);
254 case OP_BLX: 77 case OP_BLX:
255 // not supported yet 78 // not supported yet
256 break; 79 break;
257 case OP_BX: 80 case OP_BX:
258 return DisassembleBX(insn); 81 return DisassembleBX(insn);
259 case OP_CDP: 82 case OP_CDP:
260 return "cdp"; 83 return "cdp";
261 case OP_CLREX: 84 case OP_CLREX:
262 return "clrex"; 85 return "clrex";
263 case OP_CLZ: 86 case OP_CLZ:
264 return DisassembleCLZ(insn); 87 return DisassembleCLZ(insn);
265 case OP_LDC: 88 case OP_LDC:
266 return "ldc"; 89 return "ldc";
267 case OP_LDM: 90 case OP_LDM:
268 case OP_STM: 91 case OP_STM:
269 return DisassembleMemblock(opcode, insn); 92 return DisassembleMemblock(opcode, insn);
270 case OP_LDR: 93 case OP_LDR:
271 case OP_LDRB: 94 case OP_LDRB:
272 case OP_LDRBT: 95 case OP_LDRBT:
273 case OP_LDRT: 96 case OP_LDRT:
274 case OP_STR: 97 case OP_STR:
275 case OP_STRB: 98 case OP_STRB:
276 case OP_STRBT: 99 case OP_STRBT:
277 case OP_STRT: 100 case OP_STRT:
278 return DisassembleMem(insn); 101 return DisassembleMem(insn);
279 case OP_LDREX: 102 case OP_LDREX:
280 case OP_LDREXB: 103 case OP_LDREXB:
281 case OP_LDREXD: 104 case OP_LDREXD:
282 case OP_LDREXH: 105 case OP_LDREXH:
283 case OP_STREX: 106 case OP_STREX:
284 case OP_STREXB: 107 case OP_STREXB:
285 case OP_STREXD: 108 case OP_STREXD:
286 case OP_STREXH: 109 case OP_STREXH:
287 return DisassembleREX(opcode, insn); 110 return DisassembleREX(opcode, insn);
288 case OP_LDRH: 111 case OP_LDRH:
289 case OP_LDRSB: 112 case OP_LDRSB:
290 case OP_LDRSH: 113 case OP_LDRSH:
291 case OP_STRH: 114 case OP_STRH:
292 return DisassembleMemHalf(insn); 115 return DisassembleMemHalf(insn);
293 case OP_MCR: 116 case OP_MCR:
294 case OP_MRC: 117 case OP_MRC:
295 return DisassembleMCR(opcode, insn); 118 return DisassembleMCR(opcode, insn);
296 case OP_MLA: 119 case OP_MLA:
297 return DisassembleMLA(opcode, insn); 120 return DisassembleMLA(opcode, insn);
298 case OP_MRS: 121 case OP_MRS:
299 return DisassembleMRS(insn); 122 return DisassembleMRS(insn);
300 case OP_MSR: 123 case OP_MSR:
301 return DisassembleMSR(insn); 124 return DisassembleMSR(insn);
302 case OP_MUL: 125 case OP_MUL:
303 return DisassembleMUL(opcode, insn); 126 return DisassembleMUL(opcode, insn);
304 case OP_NOP: 127 case OP_NOP:
305 case OP_SEV: 128 case OP_SEV:
306 case OP_WFE: 129 case OP_WFE:
307 case OP_WFI: 130 case OP_WFI:
308 case OP_YIELD: 131 case OP_YIELD:
309 return DisassembleNoOperands(opcode, insn); 132 return DisassembleNoOperands(opcode, insn);
310 case OP_PKH: 133 case OP_PKH:
311 return DisassemblePKH(insn); 134 return DisassemblePKH(insn);
312 case OP_PLD: 135 case OP_PLD:
313 return DisassemblePLD(insn); 136 return DisassemblePLD(insn);
314 case OP_QADD16: 137 case OP_QADD16:
315 case OP_QADD8: 138 case OP_QADD8:
316 case OP_QASX: 139 case OP_QASX:
317 case OP_QSAX: 140 case OP_QSAX:
318 case OP_QSUB16: 141 case OP_QSUB16:
319 case OP_QSUB8: 142 case OP_QSUB8:
320 case OP_SADD16: 143 case OP_SADD16:
321 case OP_SADD8: 144 case OP_SADD8:
322 case OP_SASX: 145 case OP_SASX:
323 case OP_SHADD16: 146 case OP_SHADD16:
324 case OP_SHADD8: 147 case OP_SHADD8:
325 case OP_SHASX: 148 case OP_SHASX:
326 case OP_SHSAX: 149 case OP_SHSAX:
327 case OP_SHSUB16: 150 case OP_SHSUB16:
328 case OP_SHSUB8: 151 case OP_SHSUB8:
329 case OP_SSAX: 152 case OP_SSAX:
330 case OP_SSUB16: 153 case OP_SSUB16:
331 case OP_SSUB8: 154 case OP_SSUB8:
332 case OP_UADD16: 155 case OP_UADD16:
333 case OP_UADD8: 156 case OP_UADD8:
334 case OP_UASX: 157 case OP_UASX:
335 case OP_UHADD16: 158 case OP_UHADD16:
336 case OP_UHADD8: 159 case OP_UHADD8:
337 case OP_UHASX: 160 case OP_UHASX:
338 case OP_UHSAX: 161 case OP_UHSAX:
339 case OP_UHSUB16: 162 case OP_UHSUB16:
340 case OP_UHSUB8: 163 case OP_UHSUB8:
341 case OP_UQADD16: 164 case OP_UQADD16:
342 case OP_UQADD8: 165 case OP_UQADD8:
343 case OP_UQASX: 166 case OP_UQASX:
344 case OP_UQSAX: 167 case OP_UQSAX:
345 case OP_UQSUB16: 168 case OP_UQSUB16:
346 case OP_UQSUB8: 169 case OP_UQSUB8:
347 case OP_USAX: 170 case OP_USAX:
348 case OP_USUB16: 171 case OP_USUB16:
349 case OP_USUB8: 172 case OP_USUB8:
350 return DisassembleParallelAddSub(opcode, insn); 173 return DisassembleParallelAddSub(opcode, insn);
351 case OP_REV: 174 case OP_REV:
352 case OP_REV16: 175 case OP_REV16:
353 case OP_REVSH: 176 case OP_REVSH:
354 return DisassembleREV(opcode, insn); 177 return DisassembleREV(opcode, insn);
355 case OP_SEL: 178 case OP_SEL:
356 return DisassembleSEL(insn); 179 return DisassembleSEL(insn);
357 case OP_SMLAD: 180 case OP_SMLAD:
358 case OP_SMLALD: 181 case OP_SMLALD:
359 case OP_SMLSD: 182 case OP_SMLSD:
360 case OP_SMLSLD: 183 case OP_SMLSLD:
361 case OP_SMMLA: 184 case OP_SMMLA:
362 case OP_SMMLS: 185 case OP_SMMLS:
363 case OP_SMMUL: 186 case OP_SMMUL:
364 case OP_SMUAD: 187 case OP_SMUAD:
365 case OP_SMUSD: 188 case OP_SMUSD:
366 case OP_USAD8: 189 case OP_USAD8:
367 case OP_USADA8: 190 case OP_USADA8:
368 return DisassembleMediaMulDiv(opcode, insn); 191 return DisassembleMediaMulDiv(opcode, insn);
369 case OP_SSAT: 192 case OP_SSAT:
370 case OP_SSAT16: 193 case OP_SSAT16:
371 case OP_USAT: 194 case OP_USAT:
372 case OP_USAT16: 195 case OP_USAT16:
373 return DisassembleSAT(opcode, insn); 196 return DisassembleSAT(opcode, insn);
374 case OP_STC: 197 case OP_STC:
375 return "stc"; 198 return "stc";
376 case OP_SWI: 199 case OP_SWI:
377 return DisassembleSWI(insn); 200 return DisassembleSWI(insn);
378 case OP_SWP: 201 case OP_SWP:
379 case OP_SWPB: 202 case OP_SWPB:
380 return DisassembleSWP(opcode, insn); 203 return DisassembleSWP(opcode, insn);
381 case OP_SXTAB: 204 case OP_SXTAB:
382 case OP_SXTAB16: 205 case OP_SXTAB16:
383 case OP_SXTAH: 206 case OP_SXTAH:
384 case OP_SXTB: 207 case OP_SXTB:
385 case OP_SXTB16: 208 case OP_SXTB16:
386 case OP_SXTH: 209 case OP_SXTH:
387 case OP_UXTAB: 210 case OP_UXTAB:
388 case OP_UXTAB16: 211 case OP_UXTAB16:
389 case OP_UXTAH: 212 case OP_UXTAH:
390 case OP_UXTB: 213 case OP_UXTB:
391 case OP_UXTB16: 214 case OP_UXTB16:
392 case OP_UXTH: 215 case OP_UXTH:
393 return DisassembleXT(opcode, insn); 216 return DisassembleXT(opcode, insn);
394 case OP_UMLAL: 217 case OP_UMLAL:
395 case OP_UMULL: 218 case OP_UMULL:
396 case OP_SMLAL: 219 case OP_SMLAL:
397 case OP_SMULL: 220 case OP_SMULL:
398 return DisassembleUMLAL(opcode, insn); 221 return DisassembleUMLAL(opcode, insn);
399 default: 222 default:
400 return "Error"; 223 return "Error";
401 } 224 }
402 return nullptr; 225 return nullptr;
403} 226}
404 227
405std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) 228std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn) {
406{
407 static const u8 kNoOperand1 = 1; 229 static const u8 kNoOperand1 = 1;
408 static const u8 kNoDest = 2; 230 static const u8 kNoDest = 2;
409 static const u8 kNoSbit = 4; 231 static const u8 kNoSbit = 4;
@@ -421,18 +243,18 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
421 243
422 const char* opname = opcode_names[opcode]; 244 const char* opname = opcode_names[opcode];
423 switch (opcode) { 245 switch (opcode) {
424 case OP_CMN: 246 case OP_CMN:
425 case OP_CMP: 247 case OP_CMP:
426 case OP_TEQ: 248 case OP_TEQ:
427 case OP_TST: 249 case OP_TST:
428 flags = kNoDest | kNoSbit; 250 flags = kNoDest | kNoSbit;
429 break; 251 break;
430 case OP_MOV: 252 case OP_MOV:
431 case OP_MVN: 253 case OP_MVN:
432 flags = kNoOperand1; 254 flags = kNoOperand1;
433 break; 255 break;
434 default: 256 default:
435 break; 257 break;
436 } 258 }
437 259
438 // The "mov" instruction ignores the first operand (rn). 260 // The "mov" instruction ignores the first operand (rn).
@@ -448,13 +270,13 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
448 rd_str = Common::StringFromFormat("r%d, ", rd); 270 rd_str = Common::StringFromFormat("r%d, ", rd);
449 } 271 }
450 272
451 const char *sbit_str = ""; 273 const char* sbit_str = "";
452 if (bit_s && !(flags & kNoSbit)) 274 if (bit_s && !(flags & kNoSbit))
453 sbit_str = "s"; 275 sbit_str = "s";
454 276
455 if (is_immed) { 277 if (is_immed) {
456 return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", 278 return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x", opname, cond_to_str(cond),
457 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed); 279 sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
458 } 280 }
459 281
460 u8 shift_is_reg = (insn >> 4) & 1; 282 u8 shift_is_reg = (insn >> 4) & 1;
@@ -468,30 +290,28 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
468 rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2)); 290 rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
469 291
470 if (!shift_is_reg && shift_type == 0 && shift_amount == 0) { 292 if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
471 return Common::StringFromFormat("%s%s%s\t%s%sr%d", 293 return Common::StringFromFormat("%s%s%s\t%s%sr%d", opname, cond_to_str(cond), sbit_str,
472 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); 294 rd_str.c_str(), rn_str.c_str(), rm);
473 } 295 }
474 296
475 const char *shift_name = shift_names[shift_type]; 297 const char* shift_name = shift_names[shift_type];
476 if (shift_is_reg) { 298 if (shift_is_reg) {
477 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", 299 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d", opname, cond_to_str(cond),
478 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, 300 sbit_str, rd_str.c_str(), rn_str.c_str(), rm, shift_name,
479 shift_name, rs); 301 rs);
480 } 302 }
481 if (shift_amount == 0) { 303 if (shift_amount == 0) {
482 if (shift_type == 3) { 304 if (shift_type == 3) {
483 return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", 305 return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX", opname, cond_to_str(cond),
484 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm); 306 sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
485 } 307 }
486 shift_amount = 32; 308 shift_amount = 32;
487 } 309 }
488 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", 310 return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u", opname, cond_to_str(cond), sbit_str,
489 opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm, 311 rd_str.c_str(), rn_str.c_str(), rm, shift_name, shift_amount);
490 shift_name, shift_amount);
491} 312}
492 313
493std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) 314std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn) {
494{
495 u8 cond = (insn >> 28) & 0xf; 315 u8 cond = (insn >> 28) & 0xf;
496 u32 offset = insn & 0xffffff; 316 u32 offset = insn & 0xffffff;
497 // Sign-extend the 24-bit offset 317 // Sign-extend the 24-bit offset
@@ -502,26 +322,23 @@ std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn)
502 offset <<= 2; 322 offset <<= 2;
503 offset += 8; 323 offset += 8;
504 addr += offset; 324 addr += offset;
505 const char *opname = opcode_names[opcode]; 325 const char* opname = opcode_names[opcode];
506 return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr); 326 return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
507} 327}
508 328
509std::string ARM_Disasm::DisassembleBX(u32 insn) 329std::string ARM_Disasm::DisassembleBX(u32 insn) {
510{
511 u8 cond = (insn >> 28) & 0xf; 330 u8 cond = (insn >> 28) & 0xf;
512 u8 rn = insn & 0xf; 331 u8 rn = insn & 0xf;
513 return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn); 332 return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
514} 333}
515 334
516std::string ARM_Disasm::DisassembleBKPT(u32 insn) 335std::string ARM_Disasm::DisassembleBKPT(u32 insn) {
517{
518 u8 cond = (insn >> 28) & 0xf; 336 u8 cond = (insn >> 28) & 0xf;
519 u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf); 337 u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
520 return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed); 338 return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
521} 339}
522 340
523std::string ARM_Disasm::DisassembleCLZ(u32 insn) 341std::string ARM_Disasm::DisassembleCLZ(u32 insn) {
524{
525 u8 cond = (insn >> 28) & 0xf; 342 u8 cond = (insn >> 28) & 0xf;
526 u8 rd = (insn >> 12) & 0xf; 343 u8 rd = (insn >> 12) & 0xf;
527 u8 rm = insn & 0xf; 344 u8 rm = insn & 0xf;
@@ -545,9 +362,8 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
545 } 362 }
546 363
547 std::string ext_reg = ""; 364 std::string ext_reg = "";
548 std::unordered_set<Opcode, std::hash<int>> with_ext_reg = { 365 std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {OP_SMLAD, OP_SMLSD, OP_SMMLA,
549 OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8 366 OP_SMMLS, OP_USADA8};
550 };
551 if (with_ext_reg.find(opcode) != with_ext_reg.end()) 367 if (with_ext_reg.find(opcode) != with_ext_reg.end())
552 ext_reg = Common::StringFromFormat(", r%u", ra); 368 ext_reg = Common::StringFromFormat(", r%u", ra);
553 369
@@ -560,8 +376,7 @@ std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
560 ext_reg.c_str()); 376 ext_reg.c_str());
561} 377}
562 378
563std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) 379std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn) {
564{
565 std::string tmp_list; 380 std::string tmp_list;
566 381
567 u8 cond = (insn >> 28) & 0xf; 382 u8 cond = (insn >> 28) & 0xf;
@@ -572,17 +387,17 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
572 u8 rn = (insn >> 16) & 0xf; 387 u8 rn = (insn >> 16) & 0xf;
573 u16 reg_list = insn & 0xffff; 388 u16 reg_list = insn & 0xffff;
574 389
575 const char *opname = opcode_names[opcode]; 390 const char* opname = opcode_names[opcode];
576 391
577 const char *bang = ""; 392 const char* bang = "";
578 if (write_back) 393 if (write_back)
579 bang = "!"; 394 bang = "!";
580 395
581 const char *carret = ""; 396 const char* carret = "";
582 if (bit_s) 397 if (bit_s)
583 carret = "^"; 398 carret = "^";
584 399
585 const char *comma = ""; 400 const char* comma = "";
586 tmp_list[0] = 0; 401 tmp_list[0] = 0;
587 for (int ii = 0; ii < 16; ++ii) { 402 for (int ii = 0; ii < 16; ++ii) {
588 if (reg_list & (1 << ii)) { 403 if (reg_list & (1 << ii)) {
@@ -591,7 +406,7 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
591 } 406 }
592 } 407 }
593 408
594 const char *addr_mode = ""; 409 const char* addr_mode = "";
595 if (is_pre) { 410 if (is_pre) {
596 if (is_up) { 411 if (is_up) {
597 addr_mode = "ib"; 412 addr_mode = "ib";
@@ -606,12 +421,11 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
606 } 421 }
607 } 422 }
608 423
609 return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", 424 return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s", opname, cond_to_str(cond), addr_mode,
610 opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret); 425 rn, bang, tmp_list.c_str(), carret);
611} 426}
612 427
613std::string ARM_Disasm::DisassembleMem(u32 insn) 428std::string ARM_Disasm::DisassembleMem(u32 insn) {
614{
615 u8 cond = (insn >> 28) & 0xf; 429 u8 cond = (insn >> 28) & 0xf;
616 u8 is_reg = (insn >> 25) & 0x1; 430 u8 is_reg = (insn >> 25) & 0x1;
617 u8 is_load = (insn >> 20) & 0x1; 431 u8 is_load = (insn >> 20) & 0x1;
@@ -623,38 +437,40 @@ std::string ARM_Disasm::DisassembleMem(u32 insn)
623 u8 rd = (insn >> 12) & 0xf; 437 u8 rd = (insn >> 12) & 0xf;
624 u16 offset = insn & 0xfff; 438 u16 offset = insn & 0xfff;
625 439
626 const char *opname = "ldr"; 440 const char* opname = "ldr";
627 if (!is_load) 441 if (!is_load)
628 opname = "str"; 442 opname = "str";
629 443
630 const char *bang = ""; 444 const char* bang = "";
631 if (write_back) 445 if (write_back)
632 bang = "!"; 446 bang = "!";
633 447
634 const char *minus = ""; 448 const char* minus = "";
635 if (is_up == 0) 449 if (is_up == 0)
636 minus = "-"; 450 minus = "-";
637 451
638 const char *byte = ""; 452 const char* byte = "";
639 if (is_byte) 453 if (is_byte)
640 byte = "b"; 454 byte = "b";
641 455
642 if (is_reg == 0) { 456 if (is_reg == 0) {
643 if (is_pre) { 457 if (is_pre) {
644 if (offset == 0) { 458 if (offset == 0) {
645 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", 459 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
646 opname, cond_to_str(cond), byte, rd, rn); 460 byte, rd, rn);
647 } else { 461 } else {
648 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", 462 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
649 opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang); 463 cond_to_str(cond), byte, rd, rn, minus, offset,
464 bang);
650 } 465 }
651 } else { 466 } else {
652 const char *transfer = ""; 467 const char* transfer = "";
653 if (write_back) 468 if (write_back)
654 transfer = "t"; 469 transfer = "t";
655 470
656 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", 471 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u", opname,
657 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset); 472 cond_to_str(cond), byte, transfer, rd, rn, minus,
473 offset);
658 } 474 }
659 } 475 }
660 476
@@ -662,48 +478,47 @@ std::string ARM_Disasm::DisassembleMem(u32 insn)
662 u8 shift_type = (insn >> 5) & 0x3; 478 u8 shift_type = (insn >> 5) & 0x3;
663 u8 shift_amount = (insn >> 7) & 0x1f; 479 u8 shift_amount = (insn >> 7) & 0x1f;
664 480
665 const char *shift_name = shift_names[shift_type]; 481 const char* shift_name = shift_names[shift_type];
666 482
667 if (is_pre) { 483 if (is_pre) {
668 if (shift_amount == 0) { 484 if (shift_amount == 0) {
669 if (shift_type == 0) { 485 if (shift_type == 0) {
670 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", 486 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname,
671 opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); 487 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
672 } 488 }
673 if (shift_type == 3) { 489 if (shift_type == 3) {
674 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", 490 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s", opname,
675 opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang); 491 cond_to_str(cond), byte, rd, rn, minus, rm, bang);
676 } 492 }
677 shift_amount = 32; 493 shift_amount = 32;
678 } 494 }
679 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", 495 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s", opname,
680 opname, cond_to_str(cond), byte, rd, rn, minus, rm, 496 cond_to_str(cond), byte, rd, rn, minus, rm, shift_name,
681 shift_name, shift_amount, bang); 497 shift_amount, bang);
682 } 498 }
683 499
684 const char *transfer = ""; 500 const char* transfer = "";
685 if (write_back) 501 if (write_back)
686 transfer = "t"; 502 transfer = "t";
687 503
688 if (shift_amount == 0) { 504 if (shift_amount == 0) {
689 if (shift_type == 0) { 505 if (shift_type == 0) {
690 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", 506 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d", opname,
691 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); 507 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
692 } 508 }
693 if (shift_type == 3) { 509 if (shift_type == 3) {
694 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", 510 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX", opname,
695 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm); 511 cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
696 } 512 }
697 shift_amount = 32; 513 shift_amount = 32;
698 } 514 }
699 515
700 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", 516 return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u", opname,
701 opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm, 517 cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
702 shift_name, shift_amount); 518 shift_name, shift_amount);
703} 519}
704 520
705std::string ARM_Disasm::DisassembleMemHalf(u32 insn) 521std::string ARM_Disasm::DisassembleMemHalf(u32 insn) {
706{
707 u8 cond = (insn >> 28) & 0xf; 522 u8 cond = (insn >> 28) & 0xf;
708 u8 is_load = (insn >> 20) & 0x1; 523 u8 is_load = (insn >> 20) & 0x1;
709 u8 write_back = (insn >> 21) & 0x1; 524 u8 write_back = (insn >> 21) & 0x1;
@@ -716,11 +531,11 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
716 u8 rm = insn & 0xf; 531 u8 rm = insn & 0xf;
717 u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf); 532 u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
718 533
719 const char *opname = "ldr"; 534 const char* opname = "ldr";
720 if (is_load == 0) 535 if (is_load == 0)
721 opname = "str"; 536 opname = "str";
722 537
723 const char *width = ""; 538 const char* width = "";
724 if (bits_65 == 1) 539 if (bits_65 == 1)
725 width = "h"; 540 width = "h";
726 else if (bits_65 == 2) 541 else if (bits_65 == 2)
@@ -728,38 +543,39 @@ std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
728 else 543 else
729 width = "sh"; 544 width = "sh";
730 545
731 const char *bang = ""; 546 const char* bang = "";
732 if (write_back) 547 if (write_back)
733 bang = "!"; 548 bang = "!";
734 const char *minus = ""; 549 const char* minus = "";
735 if (is_up == 0) 550 if (is_up == 0)
736 minus = "-"; 551 minus = "-";
737 552
738 if (is_immed) { 553 if (is_immed) {
739 if (is_pre) { 554 if (is_pre) {
740 if (offset == 0) { 555 if (offset == 0) {
741 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond), width, rd, rn); 556 return Common::StringFromFormat("%s%s%s\tr%d, [r%d]", opname, cond_to_str(cond),
557 width, rd, rn);
742 } else { 558 } else {
743 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", 559 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s", opname,
744 opname, cond_to_str(cond), width, rd, rn, minus, offset, bang); 560 cond_to_str(cond), width, rd, rn, minus, offset,
561 bang);
745 } 562 }
746 } else { 563 } else {
747 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", 564 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], #%s%u", opname, cond_to_str(cond),
748 opname, cond_to_str(cond), width, rd, rn, minus, offset); 565 width, rd, rn, minus, offset);
749 } 566 }
750 } 567 }
751 568
752 if (is_pre) { 569 if (is_pre) {
753 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", 570 return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s", opname, cond_to_str(cond),
754 opname, cond_to_str(cond), width, rd, rn, minus, rm, bang); 571 width, rd, rn, minus, rm, bang);
755 } else { 572 } else {
756 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", 573 return Common::StringFromFormat("%s%s%s\tr%d, [r%d], %sr%d", opname, cond_to_str(cond),
757 opname, cond_to_str(cond), width, rd, rn, minus, rm); 574 width, rd, rn, minus, rm);
758 } 575 }
759} 576}
760 577
761std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) 578std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn) {
762{
763 u8 cond = (insn >> 28) & 0xf; 579 u8 cond = (insn >> 28) & 0xf;
764 u8 crn = (insn >> 16) & 0xf; 580 u8 crn = (insn >> 16) & 0xf;
765 u8 crd = (insn >> 12) & 0xf; 581 u8 crd = (insn >> 12) & 0xf;
@@ -767,13 +583,12 @@ std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn)
767 u8 opcode2 = (insn >> 5) & 0x7; 583 u8 opcode2 = (insn >> 5) & 0x7;
768 u8 crm = insn & 0xf; 584 u8 crm = insn & 0xf;
769 585
770 const char *opname = opcode_names[opcode]; 586 const char* opname = opcode_names[opcode];
771 return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", 587 return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}", opname, cond_to_str(cond),
772 opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2); 588 cpnum, crd, crn, crm, opcode2);
773} 589}
774 590
775std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) 591std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn) {
776{
777 u8 cond = (insn >> 28) & 0xf; 592 u8 cond = (insn >> 28) & 0xf;
778 u8 rd = (insn >> 16) & 0xf; 593 u8 rd = (insn >> 16) & 0xf;
779 u8 rn = (insn >> 12) & 0xf; 594 u8 rn = (insn >> 12) & 0xf;
@@ -781,13 +596,12 @@ std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn)
781 u8 rm = insn & 0xf; 596 u8 rm = insn & 0xf;
782 u8 bit_s = (insn >> 20) & 1; 597 u8 bit_s = (insn >> 20) & 1;
783 598
784 const char *opname = opcode_names[opcode]; 599 const char* opname = opcode_names[opcode];
785 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", 600 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
786 opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn); 601 bit_s ? "s" : "", rd, rm, rs, rn);
787} 602}
788 603
789std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) 604std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn) {
790{
791 u8 cond = (insn >> 28) & 0xf; 605 u8 cond = (insn >> 28) & 0xf;
792 u8 rdhi = (insn >> 16) & 0xf; 606 u8 rdhi = (insn >> 16) & 0xf;
793 u8 rdlo = (insn >> 12) & 0xf; 607 u8 rdlo = (insn >> 12) & 0xf;
@@ -795,26 +609,24 @@ std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn)
795 u8 rm = insn & 0xf; 609 u8 rm = insn & 0xf;
796 u8 bit_s = (insn >> 20) & 1; 610 u8 bit_s = (insn >> 20) & 1;
797 611
798 const char *opname = opcode_names[opcode]; 612 const char* opname = opcode_names[opcode];
799 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", 613 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d", opname, cond_to_str(cond),
800 opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs); 614 bit_s ? "s" : "", rdlo, rdhi, rm, rs);
801} 615}
802 616
803std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) 617std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn) {
804{
805 u8 cond = (insn >> 28) & 0xf; 618 u8 cond = (insn >> 28) & 0xf;
806 u8 rd = (insn >> 16) & 0xf; 619 u8 rd = (insn >> 16) & 0xf;
807 u8 rs = (insn >> 8) & 0xf; 620 u8 rs = (insn >> 8) & 0xf;
808 u8 rm = insn & 0xf; 621 u8 rm = insn & 0xf;
809 u8 bit_s = (insn >> 20) & 1; 622 u8 bit_s = (insn >> 20) & 1;
810 623
811 const char *opname = opcode_names[opcode]; 624 const char* opname = opcode_names[opcode];
812 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", 625 return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d", opname, cond_to_str(cond),
813 opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs); 626 bit_s ? "s" : "", rd, rm, rs);
814} 627}
815 628
816std::string ARM_Disasm::DisassembleMRS(u32 insn) 629std::string ARM_Disasm::DisassembleMRS(u32 insn) {
817{
818 u8 cond = (insn >> 28) & 0xf; 630 u8 cond = (insn >> 28) & 0xf;
819 u8 rd = (insn >> 12) & 0xf; 631 u8 rd = (insn >> 12) & 0xf;
820 u8 ps = (insn >> 22) & 1; 632 u8 ps = (insn >> 22) & 1;
@@ -822,8 +634,7 @@ std::string ARM_Disasm::DisassembleMRS(u32 insn)
822 return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr"); 634 return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
823} 635}
824 636
825std::string ARM_Disasm::DisassembleMSR(u32 insn) 637std::string ARM_Disasm::DisassembleMSR(u32 insn) {
826{
827 char flags[8]; 638 char flags[8];
828 int flag_index = 0; 639 int flag_index = 0;
829 u8 cond = (insn >> 28) & 0xf; 640 u8 cond = (insn >> 28) & 0xf;
@@ -846,18 +657,17 @@ std::string ARM_Disasm::DisassembleMSR(u32 insn)
846 u8 rotate = (insn >> 8) & 0xf; 657 u8 rotate = (insn >> 8) & 0xf;
847 u8 rotate2 = rotate << 1; 658 u8 rotate2 = rotate << 1;
848 u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2)); 659 u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
849 return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", 660 return Common::StringFromFormat("msr%s\t%s_%s, #0x%x", cond_to_str(cond),
850 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val); 661 pd ? "spsr" : "cpsr", flags, rotated_val);
851 } 662 }
852 663
853 u8 rm = insn & 0xf; 664 u8 rm = insn & 0xf;
854 665
855 return Common::StringFromFormat("msr%s\t%s_%s, r%d", 666 return Common::StringFromFormat("msr%s\t%s_%s, r%d", cond_to_str(cond), pd ? "spsr" : "cpsr",
856 cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm); 667 flags, rm);
857} 668}
858 669
859std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) 670std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn) {
860{
861 u32 cond = BITS(insn, 28, 31); 671 u32 cond = BITS(insn, 28, 31);
862 return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond)); 672 return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
863} 673}
@@ -872,8 +682,7 @@ std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
872 rd, rn, rm); 682 rd, rn, rm);
873} 683}
874 684
875std::string ARM_Disasm::DisassemblePKH(u32 insn) 685std::string ARM_Disasm::DisassemblePKH(u32 insn) {
876{
877 u32 cond = BITS(insn, 28, 31); 686 u32 cond = BITS(insn, 28, 31);
878 u32 rn = BITS(insn, 16, 19); 687 u32 rn = BITS(insn, 16, 19);
879 u32 rd = BITS(insn, 12, 15); 688 u32 rd = BITS(insn, 12, 15);
@@ -896,13 +705,12 @@ std::string ARM_Disasm::DisassemblePKH(u32 insn)
896 rd, rn, rm, shift.c_str()); 705 rd, rn, rm, shift.c_str());
897} 706}
898 707
899std::string ARM_Disasm::DisassemblePLD(u32 insn) 708std::string ARM_Disasm::DisassemblePLD(u32 insn) {
900{
901 u8 is_reg = (insn >> 25) & 0x1; 709 u8 is_reg = (insn >> 25) & 0x1;
902 u8 is_up = (insn >> 23) & 0x1; 710 u8 is_up = (insn >> 23) & 0x1;
903 u8 rn = (insn >> 16) & 0xf; 711 u8 rn = (insn >> 16) & 0xf;
904 712
905 const char *minus = ""; 713 const char* minus = "";
906 if (is_up == 0) 714 if (is_up == 0)
907 minus = "-"; 715 minus = "-";
908 716
@@ -924,8 +732,8 @@ std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
924 u32 rd = BITS(insn, 12, 15); 732 u32 rd = BITS(insn, 12, 15);
925 u32 rm = BITS(insn, 0, 3); 733 u32 rm = BITS(insn, 0, 3);
926 734
927 return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), 735 return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond), rd,
928 rd, rm); 736 rm);
929} 737}
930 738
931std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) { 739std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
@@ -935,26 +743,26 @@ std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
935 u32 cond = BITS(insn, 28, 31); 743 u32 cond = BITS(insn, 28, 31);
936 744
937 switch (opcode) { 745 switch (opcode) {
938 case OP_STREX: 746 case OP_STREX:
939 case OP_STREXB: 747 case OP_STREXB:
940 case OP_STREXH: 748 case OP_STREXH:
941 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], 749 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
942 cond_to_str(cond), rd, rt, rn); 750 cond_to_str(cond), rd, rt, rn);
943 case OP_STREXD: 751 case OP_STREXD:
944 return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode], 752 return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
945 cond_to_str(cond), rd, rt, rt + 1, rn); 753 cond_to_str(cond), rd, rt, rt + 1, rn);
946 754
947 // for LDREX instructions, rd corresponds to Rt from reference manual 755 // for LDREX instructions, rd corresponds to Rt from reference manual
948 case OP_LDREX: 756 case OP_LDREX:
949 case OP_LDREXB: 757 case OP_LDREXB:
950 case OP_LDREXH: 758 case OP_LDREXH:
951 return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], 759 return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode], cond_to_str(cond),
952 cond_to_str(cond), rd, rn); 760 rd, rn);
953 case OP_LDREXD: 761 case OP_LDREXD:
954 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode], 762 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
955 cond_to_str(cond), rd, rd + 1, rn); 763 cond_to_str(cond), rd, rd + 1, rn);
956 default: 764 default:
957 return opcode_names[OP_UNDEFINED]; 765 return opcode_names[OP_UNDEFINED];
958 } 766 }
959} 767}
960 768
@@ -982,8 +790,8 @@ std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
982 if (opcode == OP_SSAT || opcode == OP_SSAT16) 790 if (opcode == OP_SSAT || opcode == OP_SSAT16)
983 sat_imm++; 791 sat_imm++;
984 792
985 return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], cond_to_str(cond), rd, 793 return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode],
986 sat_imm, rn, shift_part.c_str()); 794 cond_to_str(cond), rd, sat_imm, rn, shift_part.c_str());
987} 795}
988 796
989std::string ARM_Disasm::DisassembleSEL(u32 insn) { 797std::string ARM_Disasm::DisassembleSEL(u32 insn) {
@@ -996,27 +804,24 @@ std::string ARM_Disasm::DisassembleSEL(u32 insn) {
996 rd, rn, rm); 804 rd, rn, rm);
997} 805}
998 806
999std::string ARM_Disasm::DisassembleSWI(u32 insn) 807std::string ARM_Disasm::DisassembleSWI(u32 insn) {
1000{
1001 u8 cond = (insn >> 28) & 0xf; 808 u8 cond = (insn >> 28) & 0xf;
1002 u32 sysnum = insn & 0x00ffffff; 809 u32 sysnum = insn & 0x00ffffff;
1003 810
1004 return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum); 811 return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
1005} 812}
1006 813
1007std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) 814std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn) {
1008{
1009 u8 cond = (insn >> 28) & 0xf; 815 u8 cond = (insn >> 28) & 0xf;
1010 u8 rn = (insn >> 16) & 0xf; 816 u8 rn = (insn >> 16) & 0xf;
1011 u8 rd = (insn >> 12) & 0xf; 817 u8 rd = (insn >> 12) & 0xf;
1012 u8 rm = insn & 0xf; 818 u8 rm = insn & 0xf;
1013 819
1014 const char *opname = opcode_names[opcode]; 820 const char* opname = opcode_names[opcode];
1015 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn); 821 return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
1016} 822}
1017 823
1018std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) 824std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn) {
1019{
1020 u32 cond = BITS(insn, 28, 31); 825 u32 cond = BITS(insn, 28, 31);
1021 u32 rn = BITS(insn, 16, 19); 826 u32 rn = BITS(insn, 16, 19);
1022 u32 rd = BITS(insn, 12, 15); 827 u32 rd = BITS(insn, 12, 15);
@@ -1025,9 +830,7 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
1025 830
1026 std::string rn_part = ""; 831 std::string rn_part = "";
1027 static std::unordered_set<Opcode, std::hash<int>> extend_with_add = { 832 static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
1028 OP_SXTAB, OP_SXTAB16, OP_SXTAH, 833 OP_SXTAB, OP_SXTAB16, OP_SXTAH, OP_UXTAB, OP_UXTAB16, OP_UXTAH};
1029 OP_UXTAB, OP_UXTAB16, OP_UXTAH
1030 };
1031 if (extend_with_add.find(opcode) != extend_with_add.end()) 834 if (extend_with_add.find(opcode) != extend_with_add.end())
1032 rn_part = ", r" + std::to_string(rn); 835 rn_part = ", r" + std::to_string(rn);
1033 836
@@ -1042,14 +845,14 @@ std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
1042Opcode ARM_Disasm::Decode(u32 insn) { 845Opcode ARM_Disasm::Decode(u32 insn) {
1043 u32 bits27_26 = (insn >> 26) & 0x3; 846 u32 bits27_26 = (insn >> 26) & 0x3;
1044 switch (bits27_26) { 847 switch (bits27_26) {
1045 case 0x0: 848 case 0x0:
1046 return Decode00(insn); 849 return Decode00(insn);
1047 case 0x1: 850 case 0x1:
1048 return Decode01(insn); 851 return Decode01(insn);
1049 case 0x2: 852 case 0x2:
1050 return Decode10(insn); 853 return Decode10(insn);
1051 case 0x3: 854 case 0x3:
1052 return Decode11(insn); 855 return Decode11(insn);
1053 } 856 }
1054 return OP_INVALID; 857 return OP_INVALID;
1055} 858}
@@ -1198,28 +1001,28 @@ Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
1198 u32 op = BITS(insn, 20, 23); 1001 u32 op = BITS(insn, 20, 23);
1199 u32 bit22 = BIT(insn, 22); 1002 u32 bit22 = BIT(insn, 22);
1200 switch (op) { 1003 switch (op) {
1201 case 0x0: 1004 case 0x0:
1202 if (bit22) 1005 if (bit22)
1203 return OP_SWPB; 1006 return OP_SWPB;
1204 return OP_SWP; 1007 return OP_SWP;
1205 case 0x8: 1008 case 0x8:
1206 return OP_STREX; 1009 return OP_STREX;
1207 case 0x9: 1010 case 0x9:
1208 return OP_LDREX; 1011 return OP_LDREX;
1209 case 0xA: 1012 case 0xA:
1210 return OP_STREXD; 1013 return OP_STREXD;
1211 case 0xB: 1014 case 0xB:
1212 return OP_LDREXD; 1015 return OP_LDREXD;
1213 case 0xC: 1016 case 0xC:
1214 return OP_STREXB; 1017 return OP_STREXB;
1215 case 0xD: 1018 case 0xD:
1216 return OP_LDREXB; 1019 return OP_LDREXB;
1217 case 0xE: 1020 case 0xE:
1218 return OP_STREXH; 1021 return OP_STREXH;
1219 case 0xF: 1022 case 0xF:
1220 return OP_LDREXH; 1023 return OP_LDREXH;
1221 default: 1024 default:
1222 return OP_UNDEFINED; 1025 return OP_UNDEFINED;
1223 } 1026 }
1224} 1027}
1225 1028
@@ -1240,27 +1043,14 @@ Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
1240 1043
1241 static std::vector<Opcode> opcodes = { 1044 static std::vector<Opcode> opcodes = {
1242 // op1 = 0 1045 // op1 = 0
1243 OP_SADD16, OP_UADD16, 1046 OP_SADD16, OP_UADD16, OP_SASX, OP_UASX, OP_SSAX, OP_USAX, OP_SSUB16, OP_USUB16, OP_SADD8,
1244 OP_SASX, OP_UASX, 1047 OP_UADD8, OP_SSUB8, OP_USUB8,
1245 OP_SSAX, OP_USAX,
1246 OP_SSUB16, OP_USUB16,
1247 OP_SADD8, OP_UADD8,
1248 OP_SSUB8, OP_USUB8,
1249 // op1 = 1 1048 // op1 = 1
1250 OP_QADD16, OP_UQADD16, 1049 OP_QADD16, OP_UQADD16, OP_QASX, OP_UQASX, OP_QSAX, OP_UQSAX, OP_QSUB16, OP_UQSUB16,
1251 OP_QASX, OP_UQASX, 1050 OP_QADD8, OP_UQADD8, OP_QSUB8, OP_UQSUB8,
1252 OP_QSAX, OP_UQSAX,
1253 OP_QSUB16, OP_UQSUB16,
1254 OP_QADD8, OP_UQADD8,
1255 OP_QSUB8, OP_UQSUB8,
1256 // op1 = 2 1051 // op1 = 2
1257 OP_SHADD16, OP_UHADD16, 1052 OP_SHADD16, OP_UHADD16, OP_SHASX, OP_UHASX, OP_SHSAX, OP_UHSAX, OP_SHSUB16, OP_UHSUB16,
1258 OP_SHASX, OP_UHASX, 1053 OP_SHADD8, OP_UHADD8, OP_SHSUB8, OP_UHSUB8};
1259 OP_SHSAX, OP_UHSAX,
1260 OP_SHSUB16, OP_UHSUB16,
1261 OP_SHADD8, OP_UHADD8,
1262 OP_SHSUB8, OP_UHSUB8
1263 };
1264 1054
1265 u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned; 1055 u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
1266 return opcodes[opcode_index]; 1056 return opcodes[opcode_index];
@@ -1272,66 +1062,66 @@ Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
1272 u32 op2 = BITS(insn, 5, 7); 1062 u32 op2 = BITS(insn, 5, 7);
1273 1063
1274 switch (op1) { 1064 switch (op1) {
1275 case 0x0: 1065 case 0x0:
1276 if (BIT(op2, 0) == 0) 1066 if (BIT(op2, 0) == 0)
1277 return OP_PKH; 1067 return OP_PKH;
1278 if (op2 == 0x3 && a != 0xf) 1068 if (op2 == 0x3 && a != 0xf)
1279 return OP_SXTAB16; 1069 return OP_SXTAB16;
1280 if (op2 == 0x3 && a == 0xf) 1070 if (op2 == 0x3 && a == 0xf)
1281 return OP_SXTB16; 1071 return OP_SXTB16;
1282 if (op2 == 0x5) 1072 if (op2 == 0x5)
1283 return OP_SEL; 1073 return OP_SEL;
1284 break; 1074 break;
1285 case 0x2: 1075 case 0x2:
1286 if (BIT(op2, 0) == 0) 1076 if (BIT(op2, 0) == 0)
1287 return OP_SSAT; 1077 return OP_SSAT;
1288 if (op2 == 0x1) 1078 if (op2 == 0x1)
1289 return OP_SSAT16; 1079 return OP_SSAT16;
1290 if (op2 == 0x3 && a != 0xf) 1080 if (op2 == 0x3 && a != 0xf)
1291 return OP_SXTAB; 1081 return OP_SXTAB;
1292 if (op2 == 0x3 && a == 0xf) 1082 if (op2 == 0x3 && a == 0xf)
1293 return OP_SXTB; 1083 return OP_SXTB;
1294 break; 1084 break;
1295 case 0x3: 1085 case 0x3:
1296 if (op2 == 0x1) 1086 if (op2 == 0x1)
1297 return OP_REV; 1087 return OP_REV;
1298 if (BIT(op2, 0) == 0) 1088 if (BIT(op2, 0) == 0)
1299 return OP_SSAT; 1089 return OP_SSAT;
1300 if (op2 == 0x3 && a != 0xf) 1090 if (op2 == 0x3 && a != 0xf)
1301 return OP_SXTAH; 1091 return OP_SXTAH;
1302 if (op2 == 0x3 && a == 0xf) 1092 if (op2 == 0x3 && a == 0xf)
1303 return OP_SXTH; 1093 return OP_SXTH;
1304 if (op2 == 0x5) 1094 if (op2 == 0x5)
1305 return OP_REV16; 1095 return OP_REV16;
1306 break; 1096 break;
1307 case 0x4: 1097 case 0x4:
1308 if (op2 == 0x3 && a != 0xf) 1098 if (op2 == 0x3 && a != 0xf)
1309 return OP_UXTAB16; 1099 return OP_UXTAB16;
1310 if (op2 == 0x3 && a == 0xf) 1100 if (op2 == 0x3 && a == 0xf)
1311 return OP_UXTB16; 1101 return OP_UXTB16;
1312 break; 1102 break;
1313 case 0x6: 1103 case 0x6:
1314 if (BIT(op2, 0) == 0) 1104 if (BIT(op2, 0) == 0)
1315 return OP_USAT; 1105 return OP_USAT;
1316 if (op2 == 0x1) 1106 if (op2 == 0x1)
1317 return OP_USAT16; 1107 return OP_USAT16;
1318 if (op2 == 0x3 && a != 0xf) 1108 if (op2 == 0x3 && a != 0xf)
1319 return OP_UXTAB; 1109 return OP_UXTAB;
1320 if (op2 == 0x3 && a == 0xf) 1110 if (op2 == 0x3 && a == 0xf)
1321 return OP_UXTB; 1111 return OP_UXTB;
1322 break; 1112 break;
1323 case 0x7: 1113 case 0x7:
1324 if (BIT(op2, 0) == 0) 1114 if (BIT(op2, 0) == 0)
1325 return OP_USAT; 1115 return OP_USAT;
1326 if (op2 == 0x3 && a != 0xf) 1116 if (op2 == 0x3 && a != 0xf)
1327 return OP_UXTAH; 1117 return OP_UXTAH;
1328 if (op2 == 0x3 && a == 0xf) 1118 if (op2 == 0x3 && a == 0xf)
1329 return OP_UXTH; 1119 return OP_UXTH;
1330 if (op2 == 0x5) 1120 if (op2 == 0x5)
1331 return OP_REVSH; 1121 return OP_REVSH;
1332 break; 1122 break;
1333 default: 1123 default:
1334 break; 1124 break;
1335 } 1125 }
1336 1126
1337 return OP_UNDEFINED; 1127 return OP_UNDEFINED;
@@ -1378,18 +1168,18 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
1378 1168
1379 if (op == 0 && op1 == 0) { 1169 if (op == 0 && op1 == 0) {
1380 switch (op2) { 1170 switch (op2) {
1381 case 0x0: 1171 case 0x0:
1382 return OP_NOP; 1172 return OP_NOP;
1383 case 0x1: 1173 case 0x1:
1384 return OP_YIELD; 1174 return OP_YIELD;
1385 case 0x2: 1175 case 0x2:
1386 return OP_WFE; 1176 return OP_WFE;
1387 case 0x3: 1177 case 0x3:
1388 return OP_WFI; 1178 return OP_WFI;
1389 case 0x4: 1179 case 0x4:
1390 return OP_SEV; 1180 return OP_SEV;
1391 default: 1181 default:
1392 return OP_UNDEFINED; 1182 return OP_UNDEFINED;
1393 } 1183 }
1394 } 1184 }
1395 1185
@@ -1402,37 +1192,37 @@ Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
1402 u32 a = BITS(insn, 12, 15); 1192 u32 a = BITS(insn, 12, 15);
1403 1193
1404 switch (op1) { 1194 switch (op1) {
1405 case 0x0: 1195 case 0x0:
1406 if (op2_h == 0x0) { 1196 if (op2_h == 0x0) {
1407 if (a != 0xf) 1197 if (a != 0xf)
1408 return OP_SMLAD; 1198 return OP_SMLAD;
1409 else 1199 else
1410 return OP_SMUAD; 1200 return OP_SMUAD;
1411 } else if (op2_h == 0x1) { 1201 } else if (op2_h == 0x1) {
1412 if (a != 0xf) 1202 if (a != 0xf)
1413 return OP_SMLSD; 1203 return OP_SMLSD;
1414 else 1204 else
1415 return OP_SMUSD; 1205 return OP_SMUSD;
1416 } 1206 }
1417 break; 1207 break;
1418 case 0x4: 1208 case 0x4:
1419 if (op2_h == 0x0) 1209 if (op2_h == 0x0)
1420 return OP_SMLALD; 1210 return OP_SMLALD;
1421 else if (op2_h == 0x1) 1211 else if (op2_h == 0x1)
1422 return OP_SMLSLD; 1212 return OP_SMLSLD;
1423 break; 1213 break;
1424 case 0x5: 1214 case 0x5:
1425 if (op2_h == 0x0) { 1215 if (op2_h == 0x0) {
1426 if (a != 0xf) 1216 if (a != 0xf)
1427 return OP_SMMLA; 1217 return OP_SMMLA;
1428 else 1218 else
1429 return OP_SMMUL; 1219 return OP_SMMUL;
1430 } else if (op2_h == 0x3) { 1220 } else if (op2_h == 0x3) {
1431 return OP_SMMLS; 1221 return OP_SMMLS;
1432 } 1222 }
1433 break; 1223 break;
1434 default: 1224 default:
1435 break; 1225 break;
1436 } 1226 }
1437 1227
1438 return OP_UNDEFINED; 1228 return OP_UNDEFINED;
@@ -1444,23 +1234,23 @@ Opcode ARM_Disasm::DecodeMedia(u32 insn) {
1444 u32 op2 = BITS(insn, 5, 7); 1234 u32 op2 = BITS(insn, 5, 7);
1445 1235
1446 switch (BITS(op1, 3, 4)) { 1236 switch (BITS(op1, 3, 4)) {
1447 case 0x0: 1237 case 0x0:
1448 // unsigned and signed parallel addition and subtraction 1238 // unsigned and signed parallel addition and subtraction
1449 return DecodeParallelAddSub(insn); 1239 return DecodeParallelAddSub(insn);
1450 case 0x1: 1240 case 0x1:
1451 // Packing, unpacking, saturation, and reversal 1241 // Packing, unpacking, saturation, and reversal
1452 return DecodePackingSaturationReversal(insn); 1242 return DecodePackingSaturationReversal(insn);
1453 case 0x2: 1243 case 0x2:
1454 // Signed multiply, signed and unsigned divide 1244 // Signed multiply, signed and unsigned divide
1455 return DecodeMediaMulDiv(insn); 1245 return DecodeMediaMulDiv(insn);
1456 case 0x3: 1246 case 0x3:
1457 if (op2 == 0 && rd == 0xf) 1247 if (op2 == 0 && rd == 0xf)
1458 return OP_USAD8; 1248 return OP_USAD8;
1459 if (op2 == 0 && rd != 0xf) 1249 if (op2 == 0 && rd != 0xf)
1460 return OP_USADA8; 1250 return OP_USADA8;
1461 break; 1251 break;
1462 default: 1252 default:
1463 break; 1253 break;
1464 } 1254 }
1465 1255
1466 return OP_UNDEFINED; 1256 return OP_UNDEFINED;
@@ -1508,46 +1298,46 @@ Opcode ARM_Disasm::DecodeALU(u32 insn) {
1508 return OP_UNDEFINED; 1298 return OP_UNDEFINED;
1509 } 1299 }
1510 switch (opcode) { 1300 switch (opcode) {
1511 case 0x0: 1301 case 0x0:
1512 return OP_AND; 1302 return OP_AND;
1513 case 0x1: 1303 case 0x1:
1514 return OP_EOR; 1304 return OP_EOR;
1515 case 0x2: 1305 case 0x2:
1516 return OP_SUB; 1306 return OP_SUB;
1517 case 0x3: 1307 case 0x3:
1518 return OP_RSB; 1308 return OP_RSB;
1519 case 0x4: 1309 case 0x4:
1520 return OP_ADD; 1310 return OP_ADD;
1521 case 0x5: 1311 case 0x5:
1522 return OP_ADC; 1312 return OP_ADC;
1523 case 0x6: 1313 case 0x6:
1524 return OP_SBC; 1314 return OP_SBC;
1525 case 0x7: 1315 case 0x7:
1526 return OP_RSC; 1316 return OP_RSC;
1527 case 0x8: 1317 case 0x8:
1528 if (bit_s) 1318 if (bit_s)
1529 return OP_TST; 1319 return OP_TST;
1530 return OP_MRS; 1320 return OP_MRS;
1531 case 0x9: 1321 case 0x9:
1532 if (bit_s) 1322 if (bit_s)
1533 return OP_TEQ; 1323 return OP_TEQ;
1534 return OP_MSR; 1324 return OP_MSR;
1535 case 0xa: 1325 case 0xa:
1536 if (bit_s) 1326 if (bit_s)
1537 return OP_CMP; 1327 return OP_CMP;
1538 return OP_MRS; 1328 return OP_MRS;
1539 case 0xb: 1329 case 0xb:
1540 if (bit_s) 1330 if (bit_s)
1541 return OP_CMN; 1331 return OP_CMN;
1542 return OP_MSR; 1332 return OP_MSR;
1543 case 0xc: 1333 case 0xc:
1544 return OP_ORR; 1334 return OP_ORR;
1545 case 0xd: 1335 case 0xd:
1546 return OP_MOV; 1336 return OP_MOV;
1547 case 0xe: 1337 case 0xe:
1548 return OP_BIC; 1338 return OP_BIC;
1549 case 0xf: 1339 case 0xf:
1550 return OP_MVN; 1340 return OP_MVN;
1551 } 1341 }
1552 // Unreachable 1342 // Unreachable
1553 return OP_INVALID; 1343 return OP_INVALID;
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h
index 53d9c6a74..300e228ed 100644
--- a/src/core/arm/disassembler/arm_disasm.h
+++ b/src/core/arm/disassembler/arm_disasm.h
@@ -3,7 +3,6 @@
3#pragma once 3#pragma once
4 4
5#include <string> 5#include <string>
6
7#include "common/common_types.h" 6#include "common/common_types.h"
8 7
9// Note: this list of opcodes must match the list used to initialize 8// Note: this list of opcodes must match the list used to initialize
@@ -187,53 +186,53 @@ enum Opcode {
187 OP_THUMB_SWI, 186 OP_THUMB_SWI,
188 OP_THUMB_TST, 187 OP_THUMB_TST,
189 188
190 OP_END // must be last 189 OP_END // must be last
191}; 190};
192 191
193class ARM_Disasm { 192class ARM_Disasm {
194 public: 193public:
195 static std::string Disassemble(u32 addr, u32 insn); 194 static std::string Disassemble(u32 addr, u32 insn);
196 static Opcode Decode(u32 insn); 195 static Opcode Decode(u32 insn);
197 196
198 private: 197private:
199 static Opcode Decode00(u32 insn); 198 static Opcode Decode00(u32 insn);
200 static Opcode Decode01(u32 insn); 199 static Opcode Decode01(u32 insn);
201 static Opcode Decode10(u32 insn); 200 static Opcode Decode10(u32 insn);
202 static Opcode Decode11(u32 insn); 201 static Opcode Decode11(u32 insn);
203 static Opcode DecodeSyncPrimitive(u32 insn); 202 static Opcode DecodeSyncPrimitive(u32 insn);
204 static Opcode DecodeParallelAddSub(u32 insn); 203 static Opcode DecodeParallelAddSub(u32 insn);
205 static Opcode DecodePackingSaturationReversal(u32 insn); 204 static Opcode DecodePackingSaturationReversal(u32 insn);
206 static Opcode DecodeMUL(u32 insn); 205 static Opcode DecodeMUL(u32 insn);
207 static Opcode DecodeMSRImmAndHints(u32 insn); 206 static Opcode DecodeMSRImmAndHints(u32 insn);
208 static Opcode DecodeMediaMulDiv(u32 insn); 207 static Opcode DecodeMediaMulDiv(u32 insn);
209 static Opcode DecodeMedia(u32 insn); 208 static Opcode DecodeMedia(u32 insn);
210 static Opcode DecodeLDRH(u32 insn); 209 static Opcode DecodeLDRH(u32 insn);
211 static Opcode DecodeALU(u32 insn); 210 static Opcode DecodeALU(u32 insn);
212 211
213 static std::string DisassembleALU(Opcode opcode, u32 insn); 212 static std::string DisassembleALU(Opcode opcode, u32 insn);
214 static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn); 213 static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
215 static std::string DisassembleBX(u32 insn); 214 static std::string DisassembleBX(u32 insn);
216 static std::string DisassembleBKPT(u32 insn); 215 static std::string DisassembleBKPT(u32 insn);
217 static std::string DisassembleCLZ(u32 insn); 216 static std::string DisassembleCLZ(u32 insn);
218 static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn); 217 static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
219 static std::string DisassembleMemblock(Opcode opcode, u32 insn); 218 static std::string DisassembleMemblock(Opcode opcode, u32 insn);
220 static std::string DisassembleMem(u32 insn); 219 static std::string DisassembleMem(u32 insn);
221 static std::string DisassembleMemHalf(u32 insn); 220 static std::string DisassembleMemHalf(u32 insn);
222 static std::string DisassembleMCR(Opcode opcode, u32 insn); 221 static std::string DisassembleMCR(Opcode opcode, u32 insn);
223 static std::string DisassembleMLA(Opcode opcode, u32 insn); 222 static std::string DisassembleMLA(Opcode opcode, u32 insn);
224 static std::string DisassembleUMLAL(Opcode opcode, u32 insn); 223 static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
225 static std::string DisassembleMUL(Opcode opcode, u32 insn); 224 static std::string DisassembleMUL(Opcode opcode, u32 insn);
226 static std::string DisassembleMRS(u32 insn); 225 static std::string DisassembleMRS(u32 insn);
227 static std::string DisassembleMSR(u32 insn); 226 static std::string DisassembleMSR(u32 insn);
228 static std::string DisassembleNoOperands(Opcode opcode, u32 insn); 227 static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
229 static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn); 228 static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
230 static std::string DisassemblePKH(u32 insn); 229 static std::string DisassemblePKH(u32 insn);
231 static std::string DisassemblePLD(u32 insn); 230 static std::string DisassemblePLD(u32 insn);
232 static std::string DisassembleREV(Opcode opcode, u32 insn); 231 static std::string DisassembleREV(Opcode opcode, u32 insn);
233 static std::string DisassembleREX(Opcode opcode, u32 insn); 232 static std::string DisassembleREX(Opcode opcode, u32 insn);
234 static std::string DisassembleSAT(Opcode opcode, u32 insn); 233 static std::string DisassembleSAT(Opcode opcode, u32 insn);
235 static std::string DisassembleSEL(u32 insn); 234 static std::string DisassembleSEL(u32 insn);
236 static std::string DisassembleSWI(u32 insn); 235 static std::string DisassembleSWI(u32 insn);
237 static std::string DisassembleSWP(Opcode opcode, u32 insn); 236 static std::string DisassembleSWP(Opcode opcode, u32 insn);
238 static std::string DisassembleXT(Opcode opcode, u32 insn); 237 static std::string DisassembleXT(Opcode opcode, u32 insn);
239}; 238};
diff --git a/src/core/arm/disassembler/load_symbol_map.cpp b/src/core/arm/disassembler/load_symbol_map.cpp
index eb20bf6f7..6863c103a 100644
--- a/src/core/arm/disassembler/load_symbol_map.cpp
+++ b/src/core/arm/disassembler/load_symbol_map.cpp
@@ -5,10 +5,8 @@
5#include <sstream> 5#include <sstream>
6#include <string> 6#include <string>
7#include <vector> 7#include <vector>
8
9#include "common/symbols.h"
10#include "common/file_util.h" 8#include "common/file_util.h"
11 9#include "common/symbols.h"
12#include "core/arm/disassembler/load_symbol_map.h" 10#include "core/arm/disassembler/load_symbol_map.h"
13 11
14/* 12/*
HIC SVNT DRACONES