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| author | 2015-08-06 19:53:20 -0400 | |
|---|---|---|
| committer | 2015-08-06 19:55:41 -0400 | |
| commit | 59d5358068986fe275a2d96b2b63eff5c04f91e5 (patch) | |
| tree | 620861d008aa05b9545fec2f908b90a3140a5d25 /src/core/arm/disassembler | |
| parent | Merge pull request #1007 from lioncash/pc (diff) | |
| download | yuzu-59d5358068986fe275a2d96b2b63eff5c04f91e5.tar.gz yuzu-59d5358068986fe275a2d96b2b63eff5c04f91e5.tar.xz yuzu-59d5358068986fe275a2d96b2b63eff5c04f91e5.zip | |
arm_disasm: Remove unnecessary code
This part of disassembly only determines the opcode, there's no need for offset calculation here.
Diffstat (limited to 'src/core/arm/disassembler')
| -rw-r--r-- | src/core/arm/disassembler/arm_disasm.cpp | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp index f6d44d85a..aaf47b3f0 100644 --- a/src/core/arm/disassembler/arm_disasm.cpp +++ b/src/core/arm/disassembler/arm_disasm.cpp | |||
| @@ -779,20 +779,12 @@ Opcode ARM_Disasm::Decode10(uint32_t insn) { | |||
| 779 | return OP_LDM; | 779 | return OP_LDM; |
| 780 | return OP_STM; | 780 | return OP_STM; |
| 781 | } | 781 | } |
| 782 | // Branch or Branch with link | ||
| 783 | uint8_t is_link = (insn >> 24) & 1; | ||
| 784 | uint32_t offset = insn & 0xffffff; | ||
| 785 | 782 | ||
| 786 | // Sign-extend the 24-bit offset | 783 | // Branch with link |
| 787 | if ((offset >> 23) & 1) | 784 | if ((insn >> 24) & 1) |
| 788 | offset |= 0xff000000; | 785 | return OP_BL; |
| 789 | 786 | ||
| 790 | // Pre-compute the left-shift and the prefetch offset | 787 | return OP_B; |
| 791 | offset <<= 2; | ||
| 792 | offset += 8; | ||
| 793 | if (is_link == 0) | ||
| 794 | return OP_B; | ||
| 795 | return OP_BL; | ||
| 796 | } | 788 | } |
| 797 | 789 | ||
| 798 | Opcode ARM_Disasm::Decode11(uint32_t insn) { | 790 | Opcode ARM_Disasm::Decode11(uint32_t insn) { |