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authorGravatar bunnei2015-08-20 18:48:09 -0400
committerGravatar bunnei2015-08-20 18:48:09 -0400
commitd8908aef6389c83590e5f6fa3a9dc5ea5fe8fced (patch)
tree8496228fd7bb7ccc83b43fca79aa64de585d90ae /src/common
parentMerge pull request #1035 from darkf/mingw-fix (diff)
parentemitter: Remove unnecessary defines (diff)
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Merge pull request #1056 from lioncash/emitter
emitter: Minor cleanup
Diffstat (limited to 'src/common')
-rw-r--r--src/common/x64/emitter.cpp746
-rw-r--r--src/common/x64/emitter.h849
2 files changed, 773 insertions, 822 deletions
diff --git a/src/common/x64/emitter.cpp b/src/common/x64/emitter.cpp
index 4b79acd1f..cf31f8d69 100644
--- a/src/common/x64/emitter.cpp
+++ b/src/common/x64/emitter.cpp
@@ -15,6 +15,7 @@
15// Official SVN repository and contact information can be found at 15// Official SVN repository and contact information can be found at
16// http://code.google.com/p/dolphin-emu/ 16// http://code.google.com/p/dolphin-emu/
17 17
18#include <cinttypes>
18#include <cstring> 19#include <cstring>
19 20
20#include "common/assert.h" 21#include "common/assert.h"
@@ -25,11 +26,6 @@
25#include "cpu_detect.h" 26#include "cpu_detect.h"
26#include "emitter.h" 27#include "emitter.h"
27 28
28#define PRIx64 "llx"
29
30// Minimize the diff against Dolphin
31#define DYNA_REC JIT
32
33namespace Gen 29namespace Gen
34{ 30{
35 31
@@ -374,7 +370,7 @@ void XEmitter::Rex(int w, int r, int x, int b)
374 Write8(rx); 370 Write8(rx);
375} 371}
376 372
377void XEmitter::JMP(const u8 *addr, bool force5Bytes) 373void XEmitter::JMP(const u8* addr, bool force5Bytes)
378{ 374{
379 u64 fn = (u64)addr; 375 u64 fn = (u64)addr;
380 if (!force5Bytes) 376 if (!force5Bytes)
@@ -398,7 +394,7 @@ void XEmitter::JMP(const u8 *addr, bool force5Bytes)
398 } 394 }
399} 395}
400 396
401void XEmitter::JMPptr(const OpArg &arg2) 397void XEmitter::JMPptr(const OpArg& arg2)
402{ 398{
403 OpArg arg = arg2; 399 OpArg arg = arg2;
404 if (arg.IsImm()) ASSERT_MSG(0, "JMPptr - Imm argument"); 400 if (arg.IsImm()) ASSERT_MSG(0, "JMPptr - Imm argument");
@@ -425,7 +421,7 @@ void XEmitter::CALLptr(OpArg arg)
425 arg.WriteRest(this); 421 arg.WriteRest(this);
426} 422}
427 423
428void XEmitter::CALL(const void *fnptr) 424void XEmitter::CALL(const void* fnptr)
429{ 425{
430 u64 distance = u64(fnptr) - (u64(code) + 5); 426 u64 distance = u64(fnptr) - (u64(code) + 5);
431 ASSERT_MSG( 427 ASSERT_MSG(
@@ -496,7 +492,7 @@ void XEmitter::J_CC(CCFlags conditionCode, const u8* addr, bool force5bytes)
496 } 492 }
497} 493}
498 494
499void XEmitter::SetJumpTarget(const FixupBranch &branch) 495void XEmitter::SetJumpTarget(const FixupBranch& branch)
500{ 496{
501 if (branch.type == 0) 497 if (branch.type == 0)
502 { 498 {
@@ -512,30 +508,6 @@ void XEmitter::SetJumpTarget(const FixupBranch &branch)
512 } 508 }
513} 509}
514 510
515// INC/DEC considered harmful on newer CPUs due to partial flag set.
516// Use ADD, SUB instead.
517
518/*
519void XEmitter::INC(int bits, OpArg arg)
520{
521 if (arg.IsImm()) ASSERT_MSG(0, "INC - Imm argument");
522 arg.operandReg = 0;
523 if (bits == 16) {Write8(0x66);}
524 arg.WriteRex(this, bits, bits);
525 Write8(bits == 8 ? 0xFE : 0xFF);
526 arg.WriteRest(this);
527}
528void XEmitter::DEC(int bits, OpArg arg)
529{
530 if (arg.IsImm()) ASSERT_MSG(0, "DEC - Imm argument");
531 arg.operandReg = 1;
532 if (bits == 16) {Write8(0x66);}
533 arg.WriteRex(this, bits, bits);
534 Write8(bits == 8 ? 0xFE : 0xFF);
535 arg.WriteRest(this);
536}
537*/
538
539//Single byte opcodes 511//Single byte opcodes
540//There is no PUSHAD/POPAD in 64-bit mode. 512//There is no PUSHAD/POPAD in 64-bit mode.
541void XEmitter::INT3() {Write8(0xCC);} 513void XEmitter::INT3() {Write8(0xCC);}
@@ -667,7 +639,7 @@ void XEmitter::CBW(int bits)
667void XEmitter::PUSH(X64Reg reg) {WriteSimple1Byte(32, 0x50, reg);} 639void XEmitter::PUSH(X64Reg reg) {WriteSimple1Byte(32, 0x50, reg);}
668void XEmitter::POP(X64Reg reg) {WriteSimple1Byte(32, 0x58, reg);} 640void XEmitter::POP(X64Reg reg) {WriteSimple1Byte(32, 0x58, reg);}
669 641
670void XEmitter::PUSH(int bits, const OpArg &reg) 642void XEmitter::PUSH(int bits, const OpArg& reg)
671{ 643{
672 if (reg.IsSimpleReg()) 644 if (reg.IsSimpleReg())
673 PUSH(reg.GetSimpleReg()); 645 PUSH(reg.GetSimpleReg());
@@ -703,7 +675,7 @@ void XEmitter::PUSH(int bits, const OpArg &reg)
703 } 675 }
704} 676}
705 677
706void XEmitter::POP(int /*bits*/, const OpArg &reg) 678void XEmitter::POP(int /*bits*/, const OpArg& reg)
707{ 679{
708 if (reg.IsSimpleReg()) 680 if (reg.IsSimpleReg())
709 POP(reg.GetSimpleReg()); 681 POP(reg.GetSimpleReg());
@@ -791,12 +763,12 @@ void XEmitter::WriteMulDivType(int bits, OpArg src, int ext)
791 src.WriteRest(this); 763 src.WriteRest(this);
792} 764}
793 765
794void XEmitter::MUL(int bits, OpArg src) {WriteMulDivType(bits, src, 4);} 766void XEmitter::MUL(int bits, const OpArg& src) {WriteMulDivType(bits, src, 4);}
795void XEmitter::DIV(int bits, OpArg src) {WriteMulDivType(bits, src, 6);} 767void XEmitter::DIV(int bits, const OpArg& src) {WriteMulDivType(bits, src, 6);}
796void XEmitter::IMUL(int bits, OpArg src) {WriteMulDivType(bits, src, 5);} 768void XEmitter::IMUL(int bits, const OpArg& src) {WriteMulDivType(bits, src, 5);}
797void XEmitter::IDIV(int bits, OpArg src) {WriteMulDivType(bits, src, 7);} 769void XEmitter::IDIV(int bits, const OpArg& src) {WriteMulDivType(bits, src, 7);}
798void XEmitter::NEG(int bits, OpArg src) {WriteMulDivType(bits, src, 3);} 770void XEmitter::NEG(int bits, const OpArg& src) {WriteMulDivType(bits, src, 3);}
799void XEmitter::NOT(int bits, OpArg src) {WriteMulDivType(bits, src, 2);} 771void XEmitter::NOT(int bits, const OpArg& src) {WriteMulDivType(bits, src, 2);}
800 772
801void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep) 773void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep)
802{ 774{
@@ -813,24 +785,24 @@ void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bo
813 src.WriteRest(this); 785 src.WriteRest(this);
814} 786}
815 787
816void XEmitter::MOVNTI(int bits, OpArg dest, X64Reg src) 788void XEmitter::MOVNTI(int bits, const OpArg& dest, X64Reg src)
817{ 789{
818 if (bits <= 16) 790 if (bits <= 16)
819 ASSERT_MSG(0, "MOVNTI - bits<=16"); 791 ASSERT_MSG(0, "MOVNTI - bits<=16");
820 WriteBitSearchType(bits, src, dest, 0xC3); 792 WriteBitSearchType(bits, src, dest, 0xC3);
821} 793}
822 794
823void XEmitter::BSF(int bits, X64Reg dest, OpArg src) {WriteBitSearchType(bits,dest,src,0xBC);} //bottom bit to top bit 795void XEmitter::BSF(int bits, X64Reg dest, const OpArg& src) {WriteBitSearchType(bits,dest,src,0xBC);} // Bottom bit to top bit
824void XEmitter::BSR(int bits, X64Reg dest, OpArg src) {WriteBitSearchType(bits,dest,src,0xBD);} //top bit to bottom bit 796void XEmitter::BSR(int bits, X64Reg dest, const OpArg& src) {WriteBitSearchType(bits,dest,src,0xBD);} // Top bit to bottom bit
825 797
826void XEmitter::TZCNT(int bits, X64Reg dest, OpArg src) 798void XEmitter::TZCNT(int bits, X64Reg dest, const OpArg& src)
827{ 799{
828 CheckFlags(); 800 CheckFlags();
829 if (!Common::GetCPUCaps().bmi1) 801 if (!Common::GetCPUCaps().bmi1)
830 ASSERT_MSG(0, "Trying to use BMI1 on a system that doesn't support it. Bad programmer."); 802 ASSERT_MSG(0, "Trying to use BMI1 on a system that doesn't support it. Bad programmer.");
831 WriteBitSearchType(bits, dest, src, 0xBC, true); 803 WriteBitSearchType(bits, dest, src, 0xBC, true);
832} 804}
833void XEmitter::LZCNT(int bits, X64Reg dest, OpArg src) 805void XEmitter::LZCNT(int bits, X64Reg dest, const OpArg& src)
834{ 806{
835 CheckFlags(); 807 CheckFlags();
836 if (!Common::GetCPUCaps().lzcnt) 808 if (!Common::GetCPUCaps().lzcnt)
@@ -950,7 +922,7 @@ void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
950} 922}
951 923
952//shift can be either imm8 or cl 924//shift can be either imm8 or cl
953void XEmitter::WriteShift(int bits, OpArg dest, OpArg &shift, int ext) 925void XEmitter::WriteShift(int bits, OpArg dest, const OpArg& shift, int ext)
954{ 926{
955 CheckFlags(); 927 CheckFlags();
956 bool writeImm = false; 928 bool writeImm = false;
@@ -991,16 +963,16 @@ void XEmitter::WriteShift(int bits, OpArg dest, OpArg &shift, int ext)
991 963
992// large rotates and shift are slower on intel than amd 964// large rotates and shift are slower on intel than amd
993// intel likes to rotate by 1, and the op is smaller too 965// intel likes to rotate by 1, and the op is smaller too
994void XEmitter::ROL(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 0);} 966void XEmitter::ROL(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 0);}
995void XEmitter::ROR(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 1);} 967void XEmitter::ROR(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 1);}
996void XEmitter::RCL(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 2);} 968void XEmitter::RCL(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 2);}
997void XEmitter::RCR(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 3);} 969void XEmitter::RCR(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 3);}
998void XEmitter::SHL(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 4);} 970void XEmitter::SHL(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 4);}
999void XEmitter::SHR(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 5);} 971void XEmitter::SHR(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 5);}
1000void XEmitter::SAR(int bits, OpArg dest, OpArg shift) {WriteShift(bits, dest, shift, 7);} 972void XEmitter::SAR(int bits, const OpArg& dest, const OpArg& shift) {WriteShift(bits, dest, shift, 7);}
1001 973
1002// index can be either imm8 or register, don't use memory destination because it's slow 974// index can be either imm8 or register, don't use memory destination because it's slow
1003void XEmitter::WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext) 975void XEmitter::WriteBitTest(int bits, const OpArg& dest, const OpArg& index, int ext)
1004{ 976{
1005 CheckFlags(); 977 CheckFlags();
1006 if (dest.IsImm()) 978 if (dest.IsImm())
@@ -1029,13 +1001,13 @@ void XEmitter::WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext)
1029 } 1001 }
1030} 1002}
1031 1003
1032void XEmitter::BT(int bits, OpArg dest, OpArg index) {WriteBitTest(bits, dest, index, 4);} 1004void XEmitter::BT(int bits, const OpArg& dest, const OpArg& index) {WriteBitTest(bits, dest, index, 4);}
1033void XEmitter::BTS(int bits, OpArg dest, OpArg index) {WriteBitTest(bits, dest, index, 5);} 1005void XEmitter::BTS(int bits, const OpArg& dest, const OpArg& index) {WriteBitTest(bits, dest, index, 5);}
1034void XEmitter::BTR(int bits, OpArg dest, OpArg index) {WriteBitTest(bits, dest, index, 6);} 1006void XEmitter::BTR(int bits, const OpArg& dest, const OpArg& index) {WriteBitTest(bits, dest, index, 6);}
1035void XEmitter::BTC(int bits, OpArg dest, OpArg index) {WriteBitTest(bits, dest, index, 7);} 1007void XEmitter::BTC(int bits, const OpArg& dest, const OpArg& index) {WriteBitTest(bits, dest, index, 7);}
1036 1008
1037//shift can be either imm8 or cl 1009//shift can be either imm8 or cl
1038void XEmitter::SHRD(int bits, OpArg dest, OpArg src, OpArg shift) 1010void XEmitter::SHRD(int bits, const OpArg& dest, const OpArg& src, const OpArg& shift)
1039{ 1011{
1040 CheckFlags(); 1012 CheckFlags();
1041 if (dest.IsImm()) 1013 if (dest.IsImm())
@@ -1067,7 +1039,7 @@ void XEmitter::SHRD(int bits, OpArg dest, OpArg src, OpArg shift)
1067 } 1039 }
1068} 1040}
1069 1041
1070void XEmitter::SHLD(int bits, OpArg dest, OpArg src, OpArg shift) 1042void XEmitter::SHLD(int bits, const OpArg& dest, const OpArg& src, const OpArg& shift)
1071{ 1043{
1072 CheckFlags(); 1044 CheckFlags();
1073 if (dest.IsImm()) 1045 if (dest.IsImm())
@@ -1111,7 +1083,7 @@ void OpArg::WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg _operandReg, int bit
1111} 1083}
1112 1084
1113//operand can either be immediate or register 1085//operand can either be immediate or register
1114void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const 1086void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg& operand, int bits) const
1115{ 1087{
1116 X64Reg _operandReg; 1088 X64Reg _operandReg;
1117 if (IsImm()) 1089 if (IsImm())
@@ -1257,7 +1229,7 @@ void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &o
1257 } 1229 }
1258} 1230}
1259 1231
1260void XEmitter::WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2) 1232void XEmitter::WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg& a1, const OpArg& a2)
1261{ 1233{
1262 if (a1.IsImm()) 1234 if (a1.IsImm())
1263 { 1235 {
@@ -1283,24 +1255,24 @@ void XEmitter::WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg
1283 } 1255 }
1284} 1256}
1285 1257
1286void XEmitter::ADD (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmADD, a1, a2);} 1258void XEmitter::ADD (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmADD, a1, a2);}
1287void XEmitter::ADC (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmADC, a1, a2);} 1259void XEmitter::ADC (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmADC, a1, a2);}
1288void XEmitter::SUB (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmSUB, a1, a2);} 1260void XEmitter::SUB (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmSUB, a1, a2);}
1289void XEmitter::SBB (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmSBB, a1, a2);} 1261void XEmitter::SBB (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmSBB, a1, a2);}
1290void XEmitter::AND (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmAND, a1, a2);} 1262void XEmitter::AND (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmAND, a1, a2);}
1291void XEmitter::OR (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmOR , a1, a2);} 1263void XEmitter::OR (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmOR , a1, a2);}
1292void XEmitter::XOR (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmXOR, a1, a2);} 1264void XEmitter::XOR (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmXOR, a1, a2);}
1293void XEmitter::MOV (int bits, const OpArg &a1, const OpArg &a2) 1265void XEmitter::MOV (int bits, const OpArg& a1, const OpArg& a2)
1294{ 1266{
1295 if (a1.IsSimpleReg() && a2.IsSimpleReg() && a1.GetSimpleReg() == a2.GetSimpleReg()) 1267 if (a1.IsSimpleReg() && a2.IsSimpleReg() && a1.GetSimpleReg() == a2.GetSimpleReg())
1296 LOG_ERROR(Common, "Redundant MOV @ %p - bug in JIT?", code); 1268 LOG_ERROR(Common, "Redundant MOV @ %p - bug in JIT?", code);
1297 WriteNormalOp(this, bits, nrmMOV, a1, a2); 1269 WriteNormalOp(this, bits, nrmMOV, a1, a2);
1298} 1270}
1299void XEmitter::TEST(int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmTEST, a1, a2);} 1271void XEmitter::TEST(int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmTEST, a1, a2);}
1300void XEmitter::CMP (int bits, const OpArg &a1, const OpArg &a2) {CheckFlags(); WriteNormalOp(this, bits, nrmCMP, a1, a2);} 1272void XEmitter::CMP (int bits, const OpArg& a1, const OpArg& a2) {CheckFlags(); WriteNormalOp(this, bits, nrmCMP, a1, a2);}
1301void XEmitter::XCHG(int bits, const OpArg &a1, const OpArg &a2) {WriteNormalOp(this, bits, nrmXCHG, a1, a2);} 1273void XEmitter::XCHG(int bits, const OpArg& a1, const OpArg& a2) {WriteNormalOp(this, bits, nrmXCHG, a1, a2);}
1302 1274
1303void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2) 1275void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a1, const OpArg& a2)
1304{ 1276{
1305 CheckFlags(); 1277 CheckFlags();
1306 if (bits == 8) 1278 if (bits == 8)
@@ -1353,7 +1325,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
1353 } 1325 }
1354} 1326}
1355 1327
1356void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a) 1328void XEmitter::IMUL(int bits, X64Reg regOp, const OpArg& a)
1357{ 1329{
1358 CheckFlags(); 1330 CheckFlags();
1359 if (bits == 8) 1331 if (bits == 8)
@@ -1390,7 +1362,7 @@ void XEmitter::WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extr
1390 arg.WriteRest(this, extrabytes); 1362 arg.WriteRest(this, extrabytes);
1391} 1363}
1392 1364
1393void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes) 1365void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes)
1394{ 1366{
1395 WriteAVXOp(opPrefix, op, regOp, INVALID_REG, arg, extrabytes); 1367 WriteAVXOp(opPrefix, op, regOp, INVALID_REG, arg, extrabytes);
1396} 1368}
@@ -1400,25 +1372,25 @@ static int GetVEXmmmmm(u16 op)
1400 // Currently, only 0x38 and 0x3A are used as secondary escape byte. 1372 // Currently, only 0x38 and 0x3A are used as secondary escape byte.
1401 if ((op >> 8) == 0x3A) 1373 if ((op >> 8) == 0x3A)
1402 return 3; 1374 return 3;
1403 else if ((op >> 8) == 0x38) 1375 if ((op >> 8) == 0x38)
1404 return 2; 1376 return 2;
1405 else 1377
1406 return 1; 1378 return 1;
1407} 1379}
1408 1380
1409static int GetVEXpp(u8 opPrefix) 1381static int GetVEXpp(u8 opPrefix)
1410{ 1382{
1411 if (opPrefix == 0x66) 1383 if (opPrefix == 0x66)
1412 return 1; 1384 return 1;
1413 else if (opPrefix == 0xF3) 1385 if (opPrefix == 0xF3)
1414 return 2; 1386 return 2;
1415 else if (opPrefix == 0xF2) 1387 if (opPrefix == 0xF2)
1416 return 3; 1388 return 3;
1417 else 1389
1418 return 0; 1390 return 0;
1419} 1391}
1420 1392
1421void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes) 1393void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes)
1422{ 1394{
1423 if (!Common::GetCPUCaps().avx) 1395 if (!Common::GetCPUCaps().avx)
1424 ASSERT_MSG(0, "Trying to use AVX on a system that doesn't support it. Bad programmer."); 1396 ASSERT_MSG(0, "Trying to use AVX on a system that doesn't support it. Bad programmer.");
@@ -1431,7 +1403,7 @@ void XEmitter::WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpA
1431} 1403}
1432 1404
1433// Like the above, but more general; covers GPR-based VEX operations, like BMI1/2 1405// Like the above, but more general; covers GPR-based VEX operations, like BMI1/2
1434void XEmitter::WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes) 1406void XEmitter::WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes)
1435{ 1407{
1436 if (size != 32 && size != 64) 1408 if (size != 32 && size != 64)
1437 ASSERT_MSG(0, "VEX GPR instructions only support 32-bit and 64-bit modes!"); 1409 ASSERT_MSG(0, "VEX GPR instructions only support 32-bit and 64-bit modes!");
@@ -1442,7 +1414,7 @@ void XEmitter::WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg r
1442 arg.WriteRest(this, extrabytes, regOp1); 1414 arg.WriteRest(this, extrabytes, regOp1);
1443} 1415}
1444 1416
1445void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes) 1417void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes)
1446{ 1418{
1447 CheckFlags(); 1419 CheckFlags();
1448 if (!Common::GetCPUCaps().bmi1) 1420 if (!Common::GetCPUCaps().bmi1)
@@ -1450,7 +1422,7 @@ void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg
1450 WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes); 1422 WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes);
1451} 1423}
1452 1424
1453void XEmitter::WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes) 1425void XEmitter::WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes)
1454{ 1426{
1455 CheckFlags(); 1427 CheckFlags();
1456 if (!Common::GetCPUCaps().bmi2) 1428 if (!Common::GetCPUCaps().bmi2)
@@ -1517,135 +1489,135 @@ void XEmitter::WriteMXCSR(OpArg arg, int ext)
1517 arg.WriteRest(this); 1489 arg.WriteRest(this);
1518} 1490}
1519 1491
1520void XEmitter::STMXCSR(OpArg memloc) {WriteMXCSR(memloc, 3);} 1492void XEmitter::STMXCSR(const OpArg& memloc) {WriteMXCSR(memloc, 3);}
1521void XEmitter::LDMXCSR(OpArg memloc) {WriteMXCSR(memloc, 2);} 1493void XEmitter::LDMXCSR(const OpArg& memloc) {WriteMXCSR(memloc, 2);}
1522 1494
1523void XEmitter::MOVNTDQ(OpArg arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVNTDQ, regOp, arg);} 1495void XEmitter::MOVNTDQ(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVNTDQ, regOp, arg);}
1524void XEmitter::MOVNTPS(OpArg arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVNTP, regOp, arg);} 1496void XEmitter::MOVNTPS(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVNTP, regOp, arg);}
1525void XEmitter::MOVNTPD(OpArg arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVNTP, regOp, arg);} 1497void XEmitter::MOVNTPD(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVNTP, regOp, arg);}
1526 1498
1527void XEmitter::ADDSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseADD, regOp, arg);} 1499void XEmitter::ADDSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseADD, regOp, arg);}
1528void XEmitter::ADDSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseADD, regOp, arg);} 1500void XEmitter::ADDSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseADD, regOp, arg);}
1529void XEmitter::SUBSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseSUB, regOp, arg);} 1501void XEmitter::SUBSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseSUB, regOp, arg);}
1530void XEmitter::SUBSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseSUB, regOp, arg);} 1502void XEmitter::SUBSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseSUB, regOp, arg);}
1531void XEmitter::CMPSS(X64Reg regOp, OpArg arg, u8 compare) {WriteSSEOp(0xF3, sseCMP, regOp, arg, 1); Write8(compare);} 1503void XEmitter::CMPSS(X64Reg regOp, const OpArg& arg, u8 compare) {WriteSSEOp(0xF3, sseCMP, regOp, arg, 1); Write8(compare);}
1532void XEmitter::CMPSD(X64Reg regOp, OpArg arg, u8 compare) {WriteSSEOp(0xF2, sseCMP, regOp, arg, 1); Write8(compare);} 1504void XEmitter::CMPSD(X64Reg regOp, const OpArg& arg, u8 compare) {WriteSSEOp(0xF2, sseCMP, regOp, arg, 1); Write8(compare);}
1533void XEmitter::MULSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseMUL, regOp, arg);} 1505void XEmitter::MULSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseMUL, regOp, arg);}
1534void XEmitter::MULSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseMUL, regOp, arg);} 1506void XEmitter::MULSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseMUL, regOp, arg);}
1535void XEmitter::DIVSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseDIV, regOp, arg);} 1507void XEmitter::DIVSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseDIV, regOp, arg);}
1536void XEmitter::DIVSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseDIV, regOp, arg);} 1508void XEmitter::DIVSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseDIV, regOp, arg);}
1537void XEmitter::MINSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseMIN, regOp, arg);} 1509void XEmitter::MINSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseMIN, regOp, arg);}
1538void XEmitter::MINSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseMIN, regOp, arg);} 1510void XEmitter::MINSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseMIN, regOp, arg);}
1539void XEmitter::MAXSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseMAX, regOp, arg);} 1511void XEmitter::MAXSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseMAX, regOp, arg);}
1540void XEmitter::MAXSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseMAX, regOp, arg);} 1512void XEmitter::MAXSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseMAX, regOp, arg);}
1541void XEmitter::SQRTSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseSQRT, regOp, arg);} 1513void XEmitter::SQRTSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseSQRT, regOp, arg);}
1542void XEmitter::SQRTSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseSQRT, regOp, arg);} 1514void XEmitter::SQRTSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseSQRT, regOp, arg);}
1543void XEmitter::RSQRTSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseRSQRT, regOp, arg);} 1515void XEmitter::RSQRTSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseRSQRT, regOp, arg);}
1544 1516
1545void XEmitter::ADDPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseADD, regOp, arg);} 1517void XEmitter::ADDPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseADD, regOp, arg);}
1546void XEmitter::ADDPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseADD, regOp, arg);} 1518void XEmitter::ADDPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseADD, regOp, arg);}
1547void XEmitter::SUBPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseSUB, regOp, arg);} 1519void XEmitter::SUBPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseSUB, regOp, arg);}
1548void XEmitter::SUBPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseSUB, regOp, arg);} 1520void XEmitter::SUBPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseSUB, regOp, arg);}
1549void XEmitter::CMPPS(X64Reg regOp, OpArg arg, u8 compare) {WriteSSEOp(0x00, sseCMP, regOp, arg, 1); Write8(compare);} 1521void XEmitter::CMPPS(X64Reg regOp, const OpArg& arg, u8 compare) {WriteSSEOp(0x00, sseCMP, regOp, arg, 1); Write8(compare);}
1550void XEmitter::CMPPD(X64Reg regOp, OpArg arg, u8 compare) {WriteSSEOp(0x66, sseCMP, regOp, arg, 1); Write8(compare);} 1522void XEmitter::CMPPD(X64Reg regOp, const OpArg& arg, u8 compare) {WriteSSEOp(0x66, sseCMP, regOp, arg, 1); Write8(compare);}
1551void XEmitter::ANDPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseAND, regOp, arg);} 1523void XEmitter::ANDPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseAND, regOp, arg);}
1552void XEmitter::ANDPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseAND, regOp, arg);} 1524void XEmitter::ANDPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseAND, regOp, arg);}
1553void XEmitter::ANDNPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseANDN, regOp, arg);} 1525void XEmitter::ANDNPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseANDN, regOp, arg);}
1554void XEmitter::ANDNPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseANDN, regOp, arg);} 1526void XEmitter::ANDNPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseANDN, regOp, arg);}
1555void XEmitter::ORPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseOR, regOp, arg);} 1527void XEmitter::ORPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseOR, regOp, arg);}
1556void XEmitter::ORPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseOR, regOp, arg);} 1528void XEmitter::ORPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseOR, regOp, arg);}
1557void XEmitter::XORPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseXOR, regOp, arg);} 1529void XEmitter::XORPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseXOR, regOp, arg);}
1558void XEmitter::XORPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseXOR, regOp, arg);} 1530void XEmitter::XORPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseXOR, regOp, arg);}
1559void XEmitter::MULPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseMUL, regOp, arg);} 1531void XEmitter::MULPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseMUL, regOp, arg);}
1560void XEmitter::MULPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMUL, regOp, arg);} 1532void XEmitter::MULPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMUL, regOp, arg);}
1561void XEmitter::DIVPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseDIV, regOp, arg);} 1533void XEmitter::DIVPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseDIV, regOp, arg);}
1562void XEmitter::DIVPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseDIV, regOp, arg);} 1534void XEmitter::DIVPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseDIV, regOp, arg);}
1563void XEmitter::MINPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseMIN, regOp, arg);} 1535void XEmitter::MINPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseMIN, regOp, arg);}
1564void XEmitter::MINPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMIN, regOp, arg);} 1536void XEmitter::MINPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMIN, regOp, arg);}
1565void XEmitter::MAXPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseMAX, regOp, arg);} 1537void XEmitter::MAXPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseMAX, regOp, arg);}
1566void XEmitter::MAXPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMAX, regOp, arg);} 1538void XEmitter::MAXPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMAX, regOp, arg);}
1567void XEmitter::SQRTPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseSQRT, regOp, arg);} 1539void XEmitter::SQRTPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseSQRT, regOp, arg);}
1568void XEmitter::SQRTPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseSQRT, regOp, arg);} 1540void XEmitter::SQRTPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseSQRT, regOp, arg);}
1569void XEmitter::RCPPS(X64Reg regOp, OpArg arg) { WriteSSEOp(0x00, sseRCP, regOp, arg); } 1541void XEmitter::RCPPS(X64Reg regOp, const OpArg& arg) { WriteSSEOp(0x00, sseRCP, regOp, arg); }
1570void XEmitter::RSQRTPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseRSQRT, regOp, arg);} 1542void XEmitter::RSQRTPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseRSQRT, regOp, arg);}
1571void XEmitter::SHUFPS(X64Reg regOp, OpArg arg, u8 shuffle) {WriteSSEOp(0x00, sseSHUF, regOp, arg,1); Write8(shuffle);} 1543void XEmitter::SHUFPS(X64Reg regOp, const OpArg& arg, u8 shuffle) {WriteSSEOp(0x00, sseSHUF, regOp, arg,1); Write8(shuffle);}
1572void XEmitter::SHUFPD(X64Reg regOp, OpArg arg, u8 shuffle) {WriteSSEOp(0x66, sseSHUF, regOp, arg,1); Write8(shuffle);} 1544void XEmitter::SHUFPD(X64Reg regOp, const OpArg& arg, u8 shuffle) {WriteSSEOp(0x66, sseSHUF, regOp, arg,1); Write8(shuffle);}
1573 1545
1574void XEmitter::HADDPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseHADD, regOp, arg);} 1546void XEmitter::HADDPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseHADD, regOp, arg);}
1575 1547
1576void XEmitter::COMISS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseCOMIS, regOp, arg);} //weird that these should be packed 1548void XEmitter::COMISS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseCOMIS, regOp, arg);} //weird that these should be packed
1577void XEmitter::COMISD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseCOMIS, regOp, arg);} //ordered 1549void XEmitter::COMISD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseCOMIS, regOp, arg);} //ordered
1578void XEmitter::UCOMISS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseUCOMIS, regOp, arg);} //unordered 1550void XEmitter::UCOMISS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseUCOMIS, regOp, arg);} //unordered
1579void XEmitter::UCOMISD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseUCOMIS, regOp, arg);} 1551void XEmitter::UCOMISD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseUCOMIS, regOp, arg);}
1580 1552
1581void XEmitter::MOVAPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseMOVAPfromRM, regOp, arg);} 1553void XEmitter::MOVAPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseMOVAPfromRM, regOp, arg);}
1582void XEmitter::MOVAPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMOVAPfromRM, regOp, arg);} 1554void XEmitter::MOVAPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMOVAPfromRM, regOp, arg);}
1583void XEmitter::MOVAPS(OpArg arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVAPtoRM, regOp, arg);} 1555void XEmitter::MOVAPS(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVAPtoRM, regOp, arg);}
1584void XEmitter::MOVAPD(OpArg arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVAPtoRM, regOp, arg);} 1556void XEmitter::MOVAPD(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVAPtoRM, regOp, arg);}
1585 1557
1586void XEmitter::MOVUPS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, sseMOVUPfromRM, regOp, arg);} 1558void XEmitter::MOVUPS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, sseMOVUPfromRM, regOp, arg);}
1587void XEmitter::MOVUPD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMOVUPfromRM, regOp, arg);} 1559void XEmitter::MOVUPD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMOVUPfromRM, regOp, arg);}
1588void XEmitter::MOVUPS(OpArg arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVUPtoRM, regOp, arg);} 1560void XEmitter::MOVUPS(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x00, sseMOVUPtoRM, regOp, arg);}
1589void XEmitter::MOVUPD(OpArg arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVUPtoRM, regOp, arg);} 1561void XEmitter::MOVUPD(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVUPtoRM, regOp, arg);}
1590 1562
1591void XEmitter::MOVDQA(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, sseMOVDQfromRM, regOp, arg);} 1563void XEmitter::MOVDQA(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, sseMOVDQfromRM, regOp, arg);}
1592void XEmitter::MOVDQA(OpArg arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVDQtoRM, regOp, arg);} 1564void XEmitter::MOVDQA(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0x66, sseMOVDQtoRM, regOp, arg);}
1593void XEmitter::MOVDQU(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseMOVDQfromRM, regOp, arg);} 1565void XEmitter::MOVDQU(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseMOVDQfromRM, regOp, arg);}
1594void XEmitter::MOVDQU(OpArg arg, X64Reg regOp) {WriteSSEOp(0xF3, sseMOVDQtoRM, regOp, arg);} 1566void XEmitter::MOVDQU(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0xF3, sseMOVDQtoRM, regOp, arg);}
1595 1567
1596void XEmitter::MOVSS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, sseMOVUPfromRM, regOp, arg);} 1568void XEmitter::MOVSS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, sseMOVUPfromRM, regOp, arg);}
1597void XEmitter::MOVSD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, sseMOVUPfromRM, regOp, arg);} 1569void XEmitter::MOVSD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, sseMOVUPfromRM, regOp, arg);}
1598void XEmitter::MOVSS(OpArg arg, X64Reg regOp) {WriteSSEOp(0xF3, sseMOVUPtoRM, regOp, arg);} 1570void XEmitter::MOVSS(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0xF3, sseMOVUPtoRM, regOp, arg);}
1599void XEmitter::MOVSD(OpArg arg, X64Reg regOp) {WriteSSEOp(0xF2, sseMOVUPtoRM, regOp, arg);} 1571void XEmitter::MOVSD(const OpArg& arg, X64Reg regOp) {WriteSSEOp(0xF2, sseMOVUPtoRM, regOp, arg);}
1600 1572
1601void XEmitter::MOVLPS(X64Reg regOp, OpArg arg) { WriteSSEOp(0x00, sseMOVLPfromRM, regOp, arg); } 1573void XEmitter::MOVLPS(X64Reg regOp, const OpArg& arg) { WriteSSEOp(0x00, sseMOVLPfromRM, regOp, arg); }
1602void XEmitter::MOVLPD(X64Reg regOp, OpArg arg) { WriteSSEOp(0x66, sseMOVLPfromRM, regOp, arg); } 1574void XEmitter::MOVLPD(X64Reg regOp, const OpArg& arg) { WriteSSEOp(0x66, sseMOVLPfromRM, regOp, arg); }
1603void XEmitter::MOVLPS(OpArg arg, X64Reg regOp) { WriteSSEOp(0x00, sseMOVLPtoRM, regOp, arg); } 1575void XEmitter::MOVLPS(const OpArg& arg, X64Reg regOp) { WriteSSEOp(0x00, sseMOVLPtoRM, regOp, arg); }
1604void XEmitter::MOVLPD(OpArg arg, X64Reg regOp) { WriteSSEOp(0x66, sseMOVLPtoRM, regOp, arg); } 1576void XEmitter::MOVLPD(const OpArg& arg, X64Reg regOp) { WriteSSEOp(0x66, sseMOVLPtoRM, regOp, arg); }
1605 1577
1606void XEmitter::MOVHPS(X64Reg regOp, OpArg arg) { WriteSSEOp(0x00, sseMOVHPfromRM, regOp, arg); } 1578void XEmitter::MOVHPS(X64Reg regOp, const OpArg& arg) { WriteSSEOp(0x00, sseMOVHPfromRM, regOp, arg); }
1607void XEmitter::MOVHPD(X64Reg regOp, OpArg arg) { WriteSSEOp(0x66, sseMOVHPfromRM, regOp, arg); } 1579void XEmitter::MOVHPD(X64Reg regOp, const OpArg& arg) { WriteSSEOp(0x66, sseMOVHPfromRM, regOp, arg); }
1608void XEmitter::MOVHPS(OpArg arg, X64Reg regOp) { WriteSSEOp(0x00, sseMOVHPtoRM, regOp, arg); } 1580void XEmitter::MOVHPS(const OpArg& arg, X64Reg regOp) { WriteSSEOp(0x00, sseMOVHPtoRM, regOp, arg); }
1609void XEmitter::MOVHPD(OpArg arg, X64Reg regOp) { WriteSSEOp(0x66, sseMOVHPtoRM, regOp, arg); } 1581void XEmitter::MOVHPD(const OpArg& arg, X64Reg regOp) { WriteSSEOp(0x66, sseMOVHPtoRM, regOp, arg); }
1610 1582
1611void XEmitter::MOVHLPS(X64Reg regOp1, X64Reg regOp2) {WriteSSEOp(0x00, sseMOVHLPS, regOp1, R(regOp2));} 1583void XEmitter::MOVHLPS(X64Reg regOp1, X64Reg regOp2) {WriteSSEOp(0x00, sseMOVHLPS, regOp1, R(regOp2));}
1612void XEmitter::MOVLHPS(X64Reg regOp1, X64Reg regOp2) {WriteSSEOp(0x00, sseMOVLHPS, regOp1, R(regOp2));} 1584void XEmitter::MOVLHPS(X64Reg regOp1, X64Reg regOp2) {WriteSSEOp(0x00, sseMOVLHPS, regOp1, R(regOp2));}
1613 1585
1614void XEmitter::CVTPS2PD(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, 0x5A, regOp, arg);} 1586void XEmitter::CVTPS2PD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, 0x5A, regOp, arg);}
1615void XEmitter::CVTPD2PS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, 0x5A, regOp, arg);} 1587void XEmitter::CVTPD2PS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, 0x5A, regOp, arg);}
1616 1588
1617void XEmitter::CVTSD2SS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, 0x5A, regOp, arg);} 1589void XEmitter::CVTSD2SS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, 0x5A, regOp, arg);}
1618void XEmitter::CVTSS2SD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0x5A, regOp, arg);} 1590void XEmitter::CVTSS2SD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0x5A, regOp, arg);}
1619void XEmitter::CVTSD2SI(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, 0x2D, regOp, arg);} 1591void XEmitter::CVTSD2SI(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, 0x2D, regOp, arg);}
1620void XEmitter::CVTSS2SI(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0x2D, regOp, arg);} 1592void XEmitter::CVTSS2SI(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0x2D, regOp, arg);}
1621void XEmitter::CVTSI2SD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, 0x2A, regOp, arg);} 1593void XEmitter::CVTSI2SD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, 0x2A, regOp, arg);}
1622void XEmitter::CVTSI2SS(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0x2A, regOp, arg);} 1594void XEmitter::CVTSI2SS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0x2A, regOp, arg);}
1623 1595
1624void XEmitter::CVTDQ2PD(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0xE6, regOp, arg);} 1596void XEmitter::CVTDQ2PD(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0xE6, regOp, arg);}
1625void XEmitter::CVTDQ2PS(X64Reg regOp, OpArg arg) {WriteSSEOp(0x00, 0x5B, regOp, arg);} 1597void XEmitter::CVTDQ2PS(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x00, 0x5B, regOp, arg);}
1626void XEmitter::CVTPD2DQ(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, 0xE6, regOp, arg);} 1598void XEmitter::CVTPD2DQ(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, 0xE6, regOp, arg);}
1627void XEmitter::CVTPS2DQ(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, 0x5B, regOp, arg);} 1599void XEmitter::CVTPS2DQ(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, 0x5B, regOp, arg);}
1628 1600
1629void XEmitter::CVTTSD2SI(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF2, 0x2C, regOp, arg);} 1601void XEmitter::CVTTSD2SI(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF2, 0x2C, regOp, arg);}
1630void XEmitter::CVTTSS2SI(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0x2C, regOp, arg);} 1602void XEmitter::CVTTSS2SI(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0x2C, regOp, arg);}
1631void XEmitter::CVTTPS2DQ(X64Reg regOp, OpArg arg) {WriteSSEOp(0xF3, 0x5B, regOp, arg);} 1603void XEmitter::CVTTPS2DQ(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0xF3, 0x5B, regOp, arg);}
1632void XEmitter::CVTTPD2DQ(X64Reg regOp, OpArg arg) {WriteSSEOp(0x66, 0xE6, regOp, arg);} 1604void XEmitter::CVTTPD2DQ(X64Reg regOp, const OpArg& arg) {WriteSSEOp(0x66, 0xE6, regOp, arg);}
1633 1605
1634void XEmitter::MASKMOVDQU(X64Reg dest, X64Reg src) {WriteSSEOp(0x66, sseMASKMOVDQU, dest, R(src));} 1606void XEmitter::MASKMOVDQU(X64Reg dest, X64Reg src) {WriteSSEOp(0x66, sseMASKMOVDQU, dest, R(src));}
1635 1607
1636void XEmitter::MOVMSKPS(X64Reg dest, OpArg arg) {WriteSSEOp(0x00, 0x50, dest, arg);} 1608void XEmitter::MOVMSKPS(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x00, 0x50, dest, arg);}
1637void XEmitter::MOVMSKPD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x50, dest, arg);} 1609void XEmitter::MOVMSKPD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x50, dest, arg);}
1638 1610
1639void XEmitter::LDDQU(X64Reg dest, OpArg arg) {WriteSSEOp(0xF2, sseLDDQU, dest, arg);} // For integer data only 1611void XEmitter::LDDQU(X64Reg dest, const OpArg& arg) {WriteSSEOp(0xF2, sseLDDQU, dest, arg);} // For integer data only
1640 1612
1641// THESE TWO ARE UNTESTED. 1613// THESE TWO ARE UNTESTED.
1642void XEmitter::UNPCKLPS(X64Reg dest, OpArg arg) {WriteSSEOp(0x00, 0x14, dest, arg);} 1614void XEmitter::UNPCKLPS(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x00, 0x14, dest, arg);}
1643void XEmitter::UNPCKHPS(X64Reg dest, OpArg arg) {WriteSSEOp(0x00, 0x15, dest, arg);} 1615void XEmitter::UNPCKHPS(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x00, 0x15, dest, arg);}
1644 1616
1645void XEmitter::UNPCKLPD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x14, dest, arg);} 1617void XEmitter::UNPCKLPD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x14, dest, arg);}
1646void XEmitter::UNPCKHPD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x15, dest, arg);} 1618void XEmitter::UNPCKHPD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x15, dest, arg);}
1647 1619
1648void XEmitter::MOVDDUP(X64Reg regOp, OpArg arg) 1620void XEmitter::MOVDDUP(X64Reg regOp, const OpArg& arg)
1649{ 1621{
1650 if (Common::GetCPUCaps().sse3) 1622 if (Common::GetCPUCaps().sse3)
1651 { 1623 {
@@ -1663,9 +1635,9 @@ void XEmitter::MOVDDUP(X64Reg regOp, OpArg arg)
1663//There are a few more left 1635//There are a few more left
1664 1636
1665// Also some integer instructions are missing 1637// Also some integer instructions are missing
1666void XEmitter::PACKSSDW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x6B, dest, arg);} 1638void XEmitter::PACKSSDW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x6B, dest, arg);}
1667void XEmitter::PACKSSWB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x63, dest, arg);} 1639void XEmitter::PACKSSWB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x63, dest, arg);}
1668void XEmitter::PACKUSWB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x67, dest, arg);} 1640void XEmitter::PACKUSWB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x67, dest, arg);}
1669 1641
1670void XEmitter::PUNPCKLBW(X64Reg dest, const OpArg &arg) {WriteSSEOp(0x66, 0x60, dest, arg);} 1642void XEmitter::PUNPCKLBW(X64Reg dest, const OpArg &arg) {WriteSSEOp(0x66, 0x60, dest, arg);}
1671void XEmitter::PUNPCKLWD(X64Reg dest, const OpArg &arg) {WriteSSEOp(0x66, 0x61, dest, arg);} 1643void XEmitter::PUNPCKLWD(X64Reg dest, const OpArg &arg) {WriteSSEOp(0x66, 0x61, dest, arg);}
@@ -1690,7 +1662,7 @@ void XEmitter::PSRLQ(X64Reg reg, int shift)
1690 Write8(shift); 1662 Write8(shift);
1691} 1663}
1692 1664
1693void XEmitter::PSRLQ(X64Reg reg, OpArg arg) 1665void XEmitter::PSRLQ(X64Reg reg, const OpArg& arg)
1694{ 1666{
1695 WriteSSEOp(0x66, 0xd3, reg, arg); 1667 WriteSSEOp(0x66, 0xd3, reg, arg);
1696} 1668}
@@ -1735,212 +1707,212 @@ void XEmitter::PSRAD(X64Reg reg, int shift)
1735 Write8(shift); 1707 Write8(shift);
1736} 1708}
1737 1709
1738void XEmitter::WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes) 1710void XEmitter::WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes)
1739{ 1711{
1740 if (!Common::GetCPUCaps().ssse3) 1712 if (!Common::GetCPUCaps().ssse3)
1741 ASSERT_MSG(0, "Trying to use SSSE3 on a system that doesn't support it. Bad programmer."); 1713 ASSERT_MSG(0, "Trying to use SSSE3 on a system that doesn't support it. Bad programmer.");
1742 WriteSSEOp(opPrefix, op, regOp, arg, extrabytes); 1714 WriteSSEOp(opPrefix, op, regOp, arg, extrabytes);
1743} 1715}
1744 1716
1745void XEmitter::WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes) 1717void XEmitter::WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes)
1746{ 1718{
1747 if (!Common::GetCPUCaps().sse4_1) 1719 if (!Common::GetCPUCaps().sse4_1)
1748 ASSERT_MSG(0, "Trying to use SSE4.1 on a system that doesn't support it. Bad programmer."); 1720 ASSERT_MSG(0, "Trying to use SSE4.1 on a system that doesn't support it. Bad programmer.");
1749 WriteSSEOp(opPrefix, op, regOp, arg, extrabytes); 1721 WriteSSEOp(opPrefix, op, regOp, arg, extrabytes);
1750} 1722}
1751 1723
1752void XEmitter::PSHUFB(X64Reg dest, OpArg arg) {WriteSSSE3Op(0x66, 0x3800, dest, arg);} 1724void XEmitter::PSHUFB(X64Reg dest, const OpArg& arg) {WriteSSSE3Op(0x66, 0x3800, dest, arg);}
1753void XEmitter::PTEST(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3817, dest, arg);} 1725void XEmitter::PTEST(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3817, dest, arg);}
1754void XEmitter::PACKUSDW(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x382b, dest, arg);} 1726void XEmitter::PACKUSDW(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x382b, dest, arg);}
1755void XEmitter::DPPS(X64Reg dest, OpArg arg, u8 mask) {WriteSSE41Op(0x66, 0x3A40, dest, arg, 1); Write8(mask);} 1727void XEmitter::DPPS(X64Reg dest, const OpArg& arg, u8 mask) {WriteSSE41Op(0x66, 0x3A40, dest, arg, 1); Write8(mask);}
1756 1728
1757void XEmitter::PMINSB(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3838, dest, arg);} 1729void XEmitter::PMINSB(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3838, dest, arg);}
1758void XEmitter::PMINSD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3839, dest, arg);} 1730void XEmitter::PMINSD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3839, dest, arg);}
1759void XEmitter::PMINUW(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383a, dest, arg);} 1731void XEmitter::PMINUW(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383a, dest, arg);}
1760void XEmitter::PMINUD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383b, dest, arg);} 1732void XEmitter::PMINUD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383b, dest, arg);}
1761void XEmitter::PMAXSB(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383c, dest, arg);} 1733void XEmitter::PMAXSB(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383c, dest, arg);}
1762void XEmitter::PMAXSD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383d, dest, arg);} 1734void XEmitter::PMAXSD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383d, dest, arg);}
1763void XEmitter::PMAXUW(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383e, dest, arg);} 1735void XEmitter::PMAXUW(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383e, dest, arg);}
1764void XEmitter::PMAXUD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x383f, dest, arg);} 1736void XEmitter::PMAXUD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x383f, dest, arg);}
1765 1737
1766void XEmitter::PMOVSXBW(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3820, dest, arg);} 1738void XEmitter::PMOVSXBW(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3820, dest, arg);}
1767void XEmitter::PMOVSXBD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3821, dest, arg);} 1739void XEmitter::PMOVSXBD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3821, dest, arg);}
1768void XEmitter::PMOVSXBQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3822, dest, arg);} 1740void XEmitter::PMOVSXBQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3822, dest, arg);}
1769void XEmitter::PMOVSXWD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3823, dest, arg);} 1741void XEmitter::PMOVSXWD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3823, dest, arg);}
1770void XEmitter::PMOVSXWQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3824, dest, arg);} 1742void XEmitter::PMOVSXWQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3824, dest, arg);}
1771void XEmitter::PMOVSXDQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3825, dest, arg);} 1743void XEmitter::PMOVSXDQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3825, dest, arg);}
1772void XEmitter::PMOVZXBW(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3830, dest, arg);} 1744void XEmitter::PMOVZXBW(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3830, dest, arg);}
1773void XEmitter::PMOVZXBD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3831, dest, arg);} 1745void XEmitter::PMOVZXBD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3831, dest, arg);}
1774void XEmitter::PMOVZXBQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3832, dest, arg);} 1746void XEmitter::PMOVZXBQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3832, dest, arg);}
1775void XEmitter::PMOVZXWD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3833, dest, arg);} 1747void XEmitter::PMOVZXWD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3833, dest, arg);}
1776void XEmitter::PMOVZXWQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3834, dest, arg);} 1748void XEmitter::PMOVZXWQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3834, dest, arg);}
1777void XEmitter::PMOVZXDQ(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3835, dest, arg);} 1749void XEmitter::PMOVZXDQ(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3835, dest, arg);}
1778 1750
1779void XEmitter::PBLENDVB(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3810, dest, arg);} 1751void XEmitter::PBLENDVB(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3810, dest, arg);}
1780void XEmitter::BLENDVPS(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3814, dest, arg);} 1752void XEmitter::BLENDVPS(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3814, dest, arg);}
1781void XEmitter::BLENDVPD(X64Reg dest, OpArg arg) {WriteSSE41Op(0x66, 0x3815, dest, arg);} 1753void XEmitter::BLENDVPD(X64Reg dest, const OpArg& arg) {WriteSSE41Op(0x66, 0x3815, dest, arg);}
1782void XEmitter::BLENDPS(X64Reg dest, const OpArg& arg, u8 blend) { WriteSSE41Op(0x66, 0x3A0C, dest, arg, 1); Write8(blend); } 1754void XEmitter::BLENDPS(X64Reg dest, const OpArg& arg, u8 blend) { WriteSSE41Op(0x66, 0x3A0C, dest, arg, 1); Write8(blend); }
1783void XEmitter::BLENDPD(X64Reg dest, const OpArg& arg, u8 blend) { WriteSSE41Op(0x66, 0x3A0D, dest, arg, 1); Write8(blend); } 1755void XEmitter::BLENDPD(X64Reg dest, const OpArg& arg, u8 blend) { WriteSSE41Op(0x66, 0x3A0D, dest, arg, 1); Write8(blend); }
1784 1756
1785void XEmitter::ROUNDSS(X64Reg dest, OpArg arg, u8 mode) {WriteSSE41Op(0x66, 0x3A0A, dest, arg, 1); Write8(mode);} 1757void XEmitter::ROUNDSS(X64Reg dest, const OpArg& arg, u8 mode) {WriteSSE41Op(0x66, 0x3A0A, dest, arg, 1); Write8(mode);}
1786void XEmitter::ROUNDSD(X64Reg dest, OpArg arg, u8 mode) {WriteSSE41Op(0x66, 0x3A0B, dest, arg, 1); Write8(mode);} 1758void XEmitter::ROUNDSD(X64Reg dest, const OpArg& arg, u8 mode) {WriteSSE41Op(0x66, 0x3A0B, dest, arg, 1); Write8(mode);}
1787void XEmitter::ROUNDPS(X64Reg dest, OpArg arg, u8 mode) {WriteSSE41Op(0x66, 0x3A08, dest, arg, 1); Write8(mode);} 1759void XEmitter::ROUNDPS(X64Reg dest, const OpArg& arg, u8 mode) {WriteSSE41Op(0x66, 0x3A08, dest, arg, 1); Write8(mode);}
1788void XEmitter::ROUNDPD(X64Reg dest, OpArg arg, u8 mode) {WriteSSE41Op(0x66, 0x3A09, dest, arg, 1); Write8(mode);} 1760void XEmitter::ROUNDPD(X64Reg dest, const OpArg& arg, u8 mode) {WriteSSE41Op(0x66, 0x3A09, dest, arg, 1); Write8(mode);}
1789 1761
1790void XEmitter::PAND(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDB, dest, arg);} 1762void XEmitter::PAND(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDB, dest, arg);}
1791void XEmitter::PANDN(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDF, dest, arg);} 1763void XEmitter::PANDN(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDF, dest, arg);}
1792void XEmitter::PXOR(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEF, dest, arg);} 1764void XEmitter::PXOR(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xEF, dest, arg);}
1793void XEmitter::POR(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEB, dest, arg);} 1765void XEmitter::POR(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xEB, dest, arg);}
1794 1766
1795void XEmitter::PADDB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xFC, dest, arg);} 1767void XEmitter::PADDB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xFC, dest, arg);}
1796void XEmitter::PADDW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xFD, dest, arg);} 1768void XEmitter::PADDW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xFD, dest, arg);}
1797void XEmitter::PADDD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xFE, dest, arg);} 1769void XEmitter::PADDD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xFE, dest, arg);}
1798void XEmitter::PADDQ(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xD4, dest, arg);} 1770void XEmitter::PADDQ(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xD4, dest, arg);}
1799 1771
1800void XEmitter::PADDSB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEC, dest, arg);} 1772void XEmitter::PADDSB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xEC, dest, arg);}
1801void XEmitter::PADDSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xED, dest, arg);} 1773void XEmitter::PADDSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xED, dest, arg);}
1802void XEmitter::PADDUSB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDC, dest, arg);} 1774void XEmitter::PADDUSB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDC, dest, arg);}
1803void XEmitter::PADDUSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDD, dest, arg);} 1775void XEmitter::PADDUSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDD, dest, arg);}
1804 1776
1805void XEmitter::PSUBB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF8, dest, arg);} 1777void XEmitter::PSUBB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xF8, dest, arg);}
1806void XEmitter::PSUBW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF9, dest, arg);} 1778void XEmitter::PSUBW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xF9, dest, arg);}
1807void XEmitter::PSUBD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xFA, dest, arg);} 1779void XEmitter::PSUBD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xFA, dest, arg);}
1808void XEmitter::PSUBQ(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xFB, dest, arg);} 1780void XEmitter::PSUBQ(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xFB, dest, arg);}
1809 1781
1810void XEmitter::PSUBSB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xE8, dest, arg);} 1782void XEmitter::PSUBSB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xE8, dest, arg);}
1811void XEmitter::PSUBSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xE9, dest, arg);} 1783void XEmitter::PSUBSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xE9, dest, arg);}
1812void XEmitter::PSUBUSB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xD8, dest, arg);} 1784void XEmitter::PSUBUSB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xD8, dest, arg);}
1813void XEmitter::PSUBUSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xD9, dest, arg);} 1785void XEmitter::PSUBUSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xD9, dest, arg);}
1814 1786
1815void XEmitter::PAVGB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xE0, dest, arg);} 1787void XEmitter::PAVGB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xE0, dest, arg);}
1816void XEmitter::PAVGW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xE3, dest, arg);} 1788void XEmitter::PAVGW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xE3, dest, arg);}
1817 1789
1818void XEmitter::PCMPEQB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x74, dest, arg);} 1790void XEmitter::PCMPEQB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x74, dest, arg);}
1819void XEmitter::PCMPEQW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x75, dest, arg);} 1791void XEmitter::PCMPEQW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x75, dest, arg);}
1820void XEmitter::PCMPEQD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x76, dest, arg);} 1792void XEmitter::PCMPEQD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x76, dest, arg);}
1821 1793
1822void XEmitter::PCMPGTB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x64, dest, arg);} 1794void XEmitter::PCMPGTB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x64, dest, arg);}
1823void XEmitter::PCMPGTW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x65, dest, arg);} 1795void XEmitter::PCMPGTW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x65, dest, arg);}
1824void XEmitter::PCMPGTD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0x66, dest, arg);} 1796void XEmitter::PCMPGTD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0x66, dest, arg);}
1825 1797
1826void XEmitter::PEXTRW(X64Reg dest, OpArg arg, u8 subreg) {WriteSSEOp(0x66, 0xC5, dest, arg, 1); Write8(subreg);} 1798void XEmitter::PEXTRW(X64Reg dest, const OpArg& arg, u8 subreg) {WriteSSEOp(0x66, 0xC5, dest, arg, 1); Write8(subreg);}
1827void XEmitter::PINSRW(X64Reg dest, OpArg arg, u8 subreg) {WriteSSEOp(0x66, 0xC4, dest, arg, 1); Write8(subreg);} 1799void XEmitter::PINSRW(X64Reg dest, const OpArg& arg, u8 subreg) {WriteSSEOp(0x66, 0xC4, dest, arg, 1); Write8(subreg);}
1828 1800
1829void XEmitter::PMADDWD(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF5, dest, arg); } 1801void XEmitter::PMADDWD(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xF5, dest, arg); }
1830void XEmitter::PSADBW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xF6, dest, arg);} 1802void XEmitter::PSADBW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xF6, dest, arg);}
1831 1803
1832void XEmitter::PMAXSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEE, dest, arg); } 1804void XEmitter::PMAXSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xEE, dest, arg); }
1833void XEmitter::PMAXUB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDE, dest, arg); } 1805void XEmitter::PMAXUB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDE, dest, arg); }
1834void XEmitter::PMINSW(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xEA, dest, arg); } 1806void XEmitter::PMINSW(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xEA, dest, arg); }
1835void XEmitter::PMINUB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xDA, dest, arg); } 1807void XEmitter::PMINUB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xDA, dest, arg); }
1836 1808
1837void XEmitter::PMOVMSKB(X64Reg dest, OpArg arg) {WriteSSEOp(0x66, 0xD7, dest, arg); } 1809void XEmitter::PMOVMSKB(X64Reg dest, const OpArg& arg) {WriteSSEOp(0x66, 0xD7, dest, arg); }
1838void XEmitter::PSHUFD(X64Reg regOp, OpArg arg, u8 shuffle) {WriteSSEOp(0x66, 0x70, regOp, arg, 1); Write8(shuffle);} 1810void XEmitter::PSHUFD(X64Reg regOp, const OpArg& arg, u8 shuffle) {WriteSSEOp(0x66, 0x70, regOp, arg, 1); Write8(shuffle);}
1839void XEmitter::PSHUFLW(X64Reg regOp, OpArg arg, u8 shuffle) {WriteSSEOp(0xF2, 0x70, regOp, arg, 1); Write8(shuffle);} 1811void XEmitter::PSHUFLW(X64Reg regOp, const OpArg& arg, u8 shuffle) {WriteSSEOp(0xF2, 0x70, regOp, arg, 1); Write8(shuffle);}
1840void XEmitter::PSHUFHW(X64Reg regOp, OpArg arg, u8 shuffle) {WriteSSEOp(0xF3, 0x70, regOp, arg, 1); Write8(shuffle);} 1812void XEmitter::PSHUFHW(X64Reg regOp, const OpArg& arg, u8 shuffle) {WriteSSEOp(0xF3, 0x70, regOp, arg, 1); Write8(shuffle);}
1841 1813
1842// VEX 1814// VEX
1843void XEmitter::VADDSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseADD, regOp1, regOp2, arg);} 1815void XEmitter::VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0xF2, sseADD, regOp1, regOp2, arg);}
1844void XEmitter::VSUBSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseSUB, regOp1, regOp2, arg);} 1816void XEmitter::VSUBSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0xF2, sseSUB, regOp1, regOp2, arg);}
1845void XEmitter::VMULSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseMUL, regOp1, regOp2, arg);} 1817void XEmitter::VMULSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0xF2, sseMUL, regOp1, regOp2, arg);}
1846void XEmitter::VDIVSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseDIV, regOp1, regOp2, arg);} 1818void XEmitter::VDIVSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0xF2, sseDIV, regOp1, regOp2, arg);}
1847void XEmitter::VADDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseADD, regOp1, regOp2, arg);} 1819void XEmitter::VADDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0x66, sseADD, regOp1, regOp2, arg);}
1848void XEmitter::VSUBPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseSUB, regOp1, regOp2, arg);} 1820void XEmitter::VSUBPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0x66, sseSUB, regOp1, regOp2, arg);}
1849void XEmitter::VMULPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseMUL, regOp1, regOp2, arg);} 1821void XEmitter::VMULPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0x66, sseMUL, regOp1, regOp2, arg);}
1850void XEmitter::VDIVPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0x66, sseDIV, regOp1, regOp2, arg);} 1822void XEmitter::VDIVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0x66, sseDIV, regOp1, regOp2, arg);}
1851void XEmitter::VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(0xF2, sseSQRT, regOp1, regOp2, arg);} 1823void XEmitter::VSQRTSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteAVXOp(0xF2, sseSQRT, regOp1, regOp2, arg);}
1852void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, OpArg arg, u8 shuffle) {WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 1); Write8(shuffle);} 1824void XEmitter::VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle) {WriteAVXOp(0x66, sseSHUF, regOp1, regOp2, arg, 1); Write8(shuffle);}
1853void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg){WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg);} 1825void XEmitter::VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg){WriteAVXOp(0x66, 0x14, regOp1, regOp2, arg);}
1854void XEmitter::VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg){WriteAVXOp(0x66, 0x15, regOp1, regOp2, arg);} 1826void XEmitter::VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg){WriteAVXOp(0x66, 0x15, regOp1, regOp2, arg);}
1855 1827
1856void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x00, sseAND, regOp1, regOp2, arg); } 1828void XEmitter::VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x00, sseAND, regOp1, regOp2, arg); }
1857void XEmitter::VANDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, sseAND, regOp1, regOp2, arg); } 1829void XEmitter::VANDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, sseAND, regOp1, regOp2, arg); }
1858void XEmitter::VANDNPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x00, sseANDN, regOp1, regOp2, arg); } 1830void XEmitter::VANDNPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x00, sseANDN, regOp1, regOp2, arg); }
1859void XEmitter::VANDNPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, sseANDN, regOp1, regOp2, arg); } 1831void XEmitter::VANDNPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, sseANDN, regOp1, regOp2, arg); }
1860void XEmitter::VORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x00, sseOR, regOp1, regOp2, arg); } 1832void XEmitter::VORPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x00, sseOR, regOp1, regOp2, arg); }
1861void XEmitter::VORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, sseOR, regOp1, regOp2, arg); } 1833void XEmitter::VORPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, sseOR, regOp1, regOp2, arg); }
1862void XEmitter::VXORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x00, sseXOR, regOp1, regOp2, arg); } 1834void XEmitter::VXORPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x00, sseXOR, regOp1, regOp2, arg); }
1863void XEmitter::VXORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, sseXOR, regOp1, regOp2, arg); } 1835void XEmitter::VXORPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, sseXOR, regOp1, regOp2, arg); }
1864 1836
1865void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0xDB, regOp1, regOp2, arg); } 1837void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0xDB, regOp1, regOp2, arg); }
1866void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0xDF, regOp1, regOp2, arg); } 1838void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0xDF, regOp1, regOp2, arg); }
1867void XEmitter::VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0xEB, regOp1, regOp2, arg); } 1839void XEmitter::VPOR(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0xEB, regOp1, regOp2, arg); }
1868void XEmitter::VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0xEF, regOp1, regOp2, arg); } 1840void XEmitter::VPXOR(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0xEF, regOp1, regOp2, arg); }
1869 1841
1870void XEmitter::VFMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3898, regOp1, regOp2, arg); } 1842void XEmitter::VFMADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3898, regOp1, regOp2, arg); }
1871void XEmitter::VFMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A8, regOp1, regOp2, arg); } 1843void XEmitter::VFMADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A8, regOp1, regOp2, arg); }
1872void XEmitter::VFMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B8, regOp1, regOp2, arg); } 1844void XEmitter::VFMADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B8, regOp1, regOp2, arg); }
1873void XEmitter::VFMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3898, regOp1, regOp2, arg, 1); } 1845void XEmitter::VFMADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3898, regOp1, regOp2, arg, 1); }
1874void XEmitter::VFMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A8, regOp1, regOp2, arg, 1); } 1846void XEmitter::VFMADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A8, regOp1, regOp2, arg, 1); }
1875void XEmitter::VFMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B8, regOp1, regOp2, arg, 1); } 1847void XEmitter::VFMADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B8, regOp1, regOp2, arg, 1); }
1876void XEmitter::VFMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3899, regOp1, regOp2, arg); } 1848void XEmitter::VFMADD132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3899, regOp1, regOp2, arg); }
1877void XEmitter::VFMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A9, regOp1, regOp2, arg); } 1849void XEmitter::VFMADD213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A9, regOp1, regOp2, arg); }
1878void XEmitter::VFMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B9, regOp1, regOp2, arg); } 1850void XEmitter::VFMADD231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B9, regOp1, regOp2, arg); }
1879void XEmitter::VFMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3899, regOp1, regOp2, arg, 1); } 1851void XEmitter::VFMADD132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3899, regOp1, regOp2, arg, 1); }
1880void XEmitter::VFMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A9, regOp1, regOp2, arg, 1); } 1852void XEmitter::VFMADD213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A9, regOp1, regOp2, arg, 1); }
1881void XEmitter::VFMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B9, regOp1, regOp2, arg, 1); } 1853void XEmitter::VFMADD231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B9, regOp1, regOp2, arg, 1); }
1882void XEmitter::VFMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389A, regOp1, regOp2, arg); } 1854void XEmitter::VFMSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389A, regOp1, regOp2, arg); }
1883void XEmitter::VFMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AA, regOp1, regOp2, arg); } 1855void XEmitter::VFMSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AA, regOp1, regOp2, arg); }
1884void XEmitter::VFMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BA, regOp1, regOp2, arg); } 1856void XEmitter::VFMSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BA, regOp1, regOp2, arg); }
1885void XEmitter::VFMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389A, regOp1, regOp2, arg, 1); } 1857void XEmitter::VFMSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389A, regOp1, regOp2, arg, 1); }
1886void XEmitter::VFMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AA, regOp1, regOp2, arg, 1); } 1858void XEmitter::VFMSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AA, regOp1, regOp2, arg, 1); }
1887void XEmitter::VFMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BA, regOp1, regOp2, arg, 1); } 1859void XEmitter::VFMSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BA, regOp1, regOp2, arg, 1); }
1888void XEmitter::VFMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389B, regOp1, regOp2, arg); } 1860void XEmitter::VFMSUB132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389B, regOp1, regOp2, arg); }
1889void XEmitter::VFMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AB, regOp1, regOp2, arg); } 1861void XEmitter::VFMSUB213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AB, regOp1, regOp2, arg); }
1890void XEmitter::VFMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BB, regOp1, regOp2, arg); } 1862void XEmitter::VFMSUB231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BB, regOp1, regOp2, arg); }
1891void XEmitter::VFMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389B, regOp1, regOp2, arg, 1); } 1863void XEmitter::VFMSUB132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389B, regOp1, regOp2, arg, 1); }
1892void XEmitter::VFMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AB, regOp1, regOp2, arg, 1); } 1864void XEmitter::VFMSUB213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AB, regOp1, regOp2, arg, 1); }
1893void XEmitter::VFMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BB, regOp1, regOp2, arg, 1); } 1865void XEmitter::VFMSUB231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BB, regOp1, regOp2, arg, 1); }
1894void XEmitter::VFNMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389C, regOp1, regOp2, arg); } 1866void XEmitter::VFNMADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389C, regOp1, regOp2, arg); }
1895void XEmitter::VFNMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AC, regOp1, regOp2, arg); } 1867void XEmitter::VFNMADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AC, regOp1, regOp2, arg); }
1896void XEmitter::VFNMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BC, regOp1, regOp2, arg); } 1868void XEmitter::VFNMADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BC, regOp1, regOp2, arg); }
1897void XEmitter::VFNMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389C, regOp1, regOp2, arg, 1); } 1869void XEmitter::VFNMADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389C, regOp1, regOp2, arg, 1); }
1898void XEmitter::VFNMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AC, regOp1, regOp2, arg, 1); } 1870void XEmitter::VFNMADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AC, regOp1, regOp2, arg, 1); }
1899void XEmitter::VFNMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BC, regOp1, regOp2, arg, 1); } 1871void XEmitter::VFNMADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BC, regOp1, regOp2, arg, 1); }
1900void XEmitter::VFNMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389D, regOp1, regOp2, arg); } 1872void XEmitter::VFNMADD132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389D, regOp1, regOp2, arg); }
1901void XEmitter::VFNMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AD, regOp1, regOp2, arg); } 1873void XEmitter::VFNMADD213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AD, regOp1, regOp2, arg); }
1902void XEmitter::VFNMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BD, regOp1, regOp2, arg); } 1874void XEmitter::VFNMADD231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BD, regOp1, regOp2, arg); }
1903void XEmitter::VFNMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389D, regOp1, regOp2, arg, 1); } 1875void XEmitter::VFNMADD132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389D, regOp1, regOp2, arg, 1); }
1904void XEmitter::VFNMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AD, regOp1, regOp2, arg, 1); } 1876void XEmitter::VFNMADD213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AD, regOp1, regOp2, arg, 1); }
1905void XEmitter::VFNMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BD, regOp1, regOp2, arg, 1); } 1877void XEmitter::VFNMADD231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BD, regOp1, regOp2, arg, 1); }
1906void XEmitter::VFNMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389E, regOp1, regOp2, arg); } 1878void XEmitter::VFNMSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389E, regOp1, regOp2, arg); }
1907void XEmitter::VFNMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AE, regOp1, regOp2, arg); } 1879void XEmitter::VFNMSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AE, regOp1, regOp2, arg); }
1908void XEmitter::VFNMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BE, regOp1, regOp2, arg); } 1880void XEmitter::VFNMSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BE, regOp1, regOp2, arg); }
1909void XEmitter::VFNMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389E, regOp1, regOp2, arg, 1); } 1881void XEmitter::VFNMSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389E, regOp1, regOp2, arg, 1); }
1910void XEmitter::VFNMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AE, regOp1, regOp2, arg, 1); } 1882void XEmitter::VFNMSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AE, regOp1, regOp2, arg, 1); }
1911void XEmitter::VFNMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BE, regOp1, regOp2, arg, 1); } 1883void XEmitter::VFNMSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BE, regOp1, regOp2, arg, 1); }
1912void XEmitter::VFNMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389F, regOp1, regOp2, arg); } 1884void XEmitter::VFNMSUB132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389F, regOp1, regOp2, arg); }
1913void XEmitter::VFNMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AF, regOp1, regOp2, arg); } 1885void XEmitter::VFNMSUB213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AF, regOp1, regOp2, arg); }
1914void XEmitter::VFNMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BF, regOp1, regOp2, arg); } 1886void XEmitter::VFNMSUB231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BF, regOp1, regOp2, arg); }
1915void XEmitter::VFNMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x389F, regOp1, regOp2, arg, 1); } 1887void XEmitter::VFNMSUB132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x389F, regOp1, regOp2, arg, 1); }
1916void XEmitter::VFNMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38AF, regOp1, regOp2, arg, 1); } 1888void XEmitter::VFNMSUB213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38AF, regOp1, regOp2, arg, 1); }
1917void XEmitter::VFNMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38BF, regOp1, regOp2, arg, 1); } 1889void XEmitter::VFNMSUB231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38BF, regOp1, regOp2, arg, 1); }
1918void XEmitter::VFMADDSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3896, regOp1, regOp2, arg); } 1890void XEmitter::VFMADDSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3896, regOp1, regOp2, arg); }
1919void XEmitter::VFMADDSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A6, regOp1, regOp2, arg); } 1891void XEmitter::VFMADDSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A6, regOp1, regOp2, arg); }
1920void XEmitter::VFMADDSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B6, regOp1, regOp2, arg); } 1892void XEmitter::VFMADDSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B6, regOp1, regOp2, arg); }
1921void XEmitter::VFMADDSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3896, regOp1, regOp2, arg, 1); } 1893void XEmitter::VFMADDSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3896, regOp1, regOp2, arg, 1); }
1922void XEmitter::VFMADDSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A6, regOp1, regOp2, arg, 1); } 1894void XEmitter::VFMADDSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A6, regOp1, regOp2, arg, 1); }
1923void XEmitter::VFMADDSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B6, regOp1, regOp2, arg, 1); } 1895void XEmitter::VFMADDSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B6, regOp1, regOp2, arg, 1); }
1924void XEmitter::VFMSUBADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3897, regOp1, regOp2, arg); } 1896void XEmitter::VFMSUBADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3897, regOp1, regOp2, arg); }
1925void XEmitter::VFMSUBADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A7, regOp1, regOp2, arg); } 1897void XEmitter::VFMSUBADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A7, regOp1, regOp2, arg); }
1926void XEmitter::VFMSUBADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B7, regOp1, regOp2, arg); } 1898void XEmitter::VFMSUBADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B7, regOp1, regOp2, arg); }
1927void XEmitter::VFMSUBADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x3897, regOp1, regOp2, arg, 1); } 1899void XEmitter::VFMSUBADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x3897, regOp1, regOp2, arg, 1); }
1928void XEmitter::VFMSUBADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38A7, regOp1, regOp2, arg, 1); } 1900void XEmitter::VFMSUBADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38A7, regOp1, regOp2, arg, 1); }
1929void XEmitter::VFMSUBADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg) { WriteAVXOp(0x66, 0x38B7, regOp1, regOp2, arg, 1); } 1901void XEmitter::VFMSUBADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg) { WriteAVXOp(0x66, 0x38B7, regOp1, regOp2, arg, 1); }
1930 1902
1931void XEmitter::SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF3, 0x38F7, regOp1, regOp2, arg);} 1903void XEmitter::SARX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF3, 0x38F7, regOp1, regOp2, arg);}
1932void XEmitter::SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x66, 0x38F7, regOp1, regOp2, arg);} 1904void XEmitter::SHLX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x66, 0x38F7, regOp1, regOp2, arg);}
1933void XEmitter::SHRX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF2, 0x38F7, regOp1, regOp2, arg);} 1905void XEmitter::SHRX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF2, 0x38F7, regOp1, regOp2, arg);}
1934void XEmitter::RORX(int bits, X64Reg regOp, OpArg arg, u8 rotate) {WriteBMI2Op(bits, 0xF2, 0x3AF0, regOp, INVALID_REG, arg, 1); Write8(rotate);} 1906void XEmitter::RORX(int bits, X64Reg regOp, const OpArg& arg, u8 rotate) {WriteBMI2Op(bits, 0xF2, 0x3AF0, regOp, INVALID_REG, arg, 1); Write8(rotate);}
1935void XEmitter::PEXT(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF3, 0x38F5, regOp1, regOp2, arg);} 1907void XEmitter::PEXT(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteBMI2Op(bits, 0xF3, 0x38F5, regOp1, regOp2, arg);}
1936void XEmitter::PDEP(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF2, 0x38F5, regOp1, regOp2, arg);} 1908void XEmitter::PDEP(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteBMI2Op(bits, 0xF2, 0x38F5, regOp1, regOp2, arg);}
1937void XEmitter::MULX(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF2, 0x38F6, regOp2, regOp1, arg);} 1909void XEmitter::MULX(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteBMI2Op(bits, 0xF2, 0x38F6, regOp2, regOp1, arg);}
1938void XEmitter::BZHI(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x00, 0x38F5, regOp1, regOp2, arg);} 1910void XEmitter::BZHI(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x00, 0x38F5, regOp1, regOp2, arg);}
1939void XEmitter::BLSR(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x1, regOp, arg);} 1911void XEmitter::BLSR(int bits, X64Reg regOp, const OpArg& arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x1, regOp, arg);}
1940void XEmitter::BLSMSK(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x2, regOp, arg);} 1912void XEmitter::BLSMSK(int bits, X64Reg regOp, const OpArg& arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x2, regOp, arg);}
1941void XEmitter::BLSI(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x3, regOp, arg);} 1913void XEmitter::BLSI(int bits, X64Reg regOp, const OpArg& arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x3, regOp, arg);}
1942void XEmitter::BEXTR(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2){WriteBMI1Op(bits, 0x00, 0x38F7, regOp1, regOp2, arg);} 1914void XEmitter::BEXTR(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2){WriteBMI1Op(bits, 0x00, 0x38F7, regOp1, regOp2, arg);}
1943void XEmitter::ANDN(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F2, regOp1, regOp2, arg);} 1915void XEmitter::ANDN(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg) {WriteBMI1Op(bits, 0x00, 0x38F2, regOp1, regOp2, arg);}
1944 1916
1945// Prefixes 1917// Prefixes
1946 1918
@@ -1956,7 +1928,7 @@ void XEmitter::FWAIT()
1956} 1928}
1957 1929
1958// TODO: make this more generic 1930// TODO: make this more generic
1959void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg) 1931void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const OpArg& arg)
1960{ 1932{
1961 int mf = 0; 1933 int mf = 0;
1962 ASSERT_MSG(!(bits == 80 && op_80b == floatINVALID), "WriteFloatLoadStore: 80 bits not supported for this instruction"); 1934 ASSERT_MSG(!(bits == 80 && op_80b == floatINVALID), "WriteFloatLoadStore: 80 bits not supported for this instruction");
@@ -1974,9 +1946,9 @@ void XEmitter::WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg a
1974 arg.WriteRest(this, 0, (X64Reg) op); 1946 arg.WriteRest(this, 0, (X64Reg) op);
1975} 1947}
1976 1948
1977void XEmitter::FLD(int bits, OpArg src) {WriteFloatLoadStore(bits, floatLD, floatLD80, src);} 1949void XEmitter::FLD(int bits, const OpArg& src) {WriteFloatLoadStore(bits, floatLD, floatLD80, src);}
1978void XEmitter::FST(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatST, floatINVALID, dest);} 1950void XEmitter::FST(int bits, const OpArg& dest) {WriteFloatLoadStore(bits, floatST, floatINVALID, dest);}
1979void XEmitter::FSTP(int bits, OpArg dest) {WriteFloatLoadStore(bits, floatSTP, floatSTP80, dest);} 1951void XEmitter::FSTP(int bits, const OpArg& dest) {WriteFloatLoadStore(bits, floatSTP, floatSTP80, dest);}
1980void XEmitter::FNSTSW_AX() { Write8(0xDF); Write8(0xE0); } 1952void XEmitter::FNSTSW_AX() { Write8(0xDF); Write8(0xE0); }
1981 1953
1982void XEmitter::RDTSC() { Write8(0x0F); Write8(0x31); } 1954void XEmitter::RDTSC() { Write8(0x0F); Write8(0x31); }
diff --git a/src/common/x64/emitter.h b/src/common/x64/emitter.h
index e9c924126..86f4a1fff 100644
--- a/src/common/x64/emitter.h
+++ b/src/common/x64/emitter.h
@@ -328,8 +328,6 @@ enum SSECompare
328 ORD, 328 ORD,
329}; 329};
330 330
331typedef const u8* JumpTarget;
332
333class XEmitter 331class XEmitter
334{ 332{
335 friend struct OpArg; // for Write8 etc 333 friend struct OpArg; // for Write8 etc
@@ -344,27 +342,27 @@ private:
344 void WriteSimple2Byte(int bits, u8 byte1, u8 byte2, X64Reg reg); 342 void WriteSimple2Byte(int bits, u8 byte1, u8 byte2, X64Reg reg);
345 void WriteMulDivType(int bits, OpArg src, int ext); 343 void WriteMulDivType(int bits, OpArg src, int ext);
346 void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep = false); 344 void WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2, bool rep = false);
347 void WriteShift(int bits, OpArg dest, OpArg &shift, int ext); 345 void WriteShift(int bits, OpArg dest, const OpArg& shift, int ext);
348 void WriteBitTest(int bits, OpArg &dest, OpArg &index, int ext); 346 void WriteBitTest(int bits, const OpArg& dest, const OpArg& index, int ext);
349 void WriteMXCSR(OpArg arg, int ext); 347 void WriteMXCSR(OpArg arg, int ext);
350 void WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0); 348 void WriteSSEOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0);
351 void WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0); 349 void WriteSSSE3Op(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes = 0);
352 void WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0); 350 void WriteSSE41Op(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes = 0);
353 void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, OpArg arg, int extrabytes = 0); 351 void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp, const OpArg& arg, int extrabytes = 0);
354 void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0); 352 void WriteAVXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes = 0);
355 void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0); 353 void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes = 0);
356 void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0); 354 void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes = 0);
357 void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0); 355 void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, const OpArg& arg, int extrabytes = 0);
358 void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg); 356 void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, const OpArg& arg);
359 void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2); 357 void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg& a1, const OpArg& a2);
360 358
361 void ABI_CalculateFrameSize(u32 mask, size_t rsp_alignment, size_t needed_frame_size, size_t* shadowp, size_t* subtractionp, size_t* xmm_offsetp); 359 void ABI_CalculateFrameSize(u32 mask, size_t rsp_alignment, size_t needed_frame_size, size_t* shadowp, size_t* subtractionp, size_t* xmm_offsetp);
362 360
363protected: 361protected:
364 inline void Write8(u8 value) {*code++ = value;} 362 void Write8(u8 value) {*code++ = value;}
365 inline void Write16(u16 value) {*(u16*)code = (value); code += 2;} 363 void Write16(u16 value) {*(u16*)code = (value); code += 2;}
366 inline void Write32(u32 value) {*(u32*)code = (value); code += 4;} 364 void Write32(u32 value) {*(u32*)code = (value); code += 4;}
367 inline void Write64(u64 value) {*(u64*)code = (value); code += 8;} 365 void Write64(u64 value) {*(u64*)code = (value); code += 8;}
368 366
369public: 367public:
370 XEmitter() { code = nullptr; flags_locked = false; } 368 XEmitter() { code = nullptr; flags_locked = false; }
@@ -413,8 +411,8 @@ public:
413 // Stack control 411 // Stack control
414 void PUSH(X64Reg reg); 412 void PUSH(X64Reg reg);
415 void POP(X64Reg reg); 413 void POP(X64Reg reg);
416 void PUSH(int bits, const OpArg &reg); 414 void PUSH(int bits, const OpArg& reg);
417 void POP(int bits, const OpArg &reg); 415 void POP(int bits, const OpArg& reg);
418 void PUSHF(); 416 void PUSHF();
419 void POPF(); 417 void POPF();
420 418
@@ -424,21 +422,19 @@ public:
424 void UD2(); 422 void UD2();
425 FixupBranch J(bool force5bytes = false); 423 FixupBranch J(bool force5bytes = false);
426 424
427 void JMP(const u8 * addr, bool force5Bytes = false); 425 void JMP(const u8* addr, bool force5Bytes = false);
428 void JMP(OpArg arg); 426 void JMPptr(const OpArg& arg);
429 void JMPptr(const OpArg &arg);
430 void JMPself(); //infinite loop! 427 void JMPself(); //infinite loop!
431#ifdef CALL 428#ifdef CALL
432#undef CALL 429#undef CALL
433#endif 430#endif
434 void CALL(const void *fnptr); 431 void CALL(const void* fnptr);
435 void CALLptr(OpArg arg); 432 void CALLptr(OpArg arg);
436 433
437 FixupBranch J_CC(CCFlags conditionCode, bool force5bytes = false); 434 FixupBranch J_CC(CCFlags conditionCode, bool force5bytes = false);
438 //void J_CC(CCFlags conditionCode, JumpTarget target); 435 void J_CC(CCFlags conditionCode, const u8* addr, bool force5Bytes = false);
439 void J_CC(CCFlags conditionCode, const u8 * addr, bool force5Bytes = false);
440 436
441 void SetJumpTarget(const FixupBranch &branch); 437 void SetJumpTarget(const FixupBranch& branch);
442 438
443 void SETcc(CCFlags flag, OpArg dest); 439 void SETcc(CCFlags flag, OpArg dest);
444 // Note: CMOV brings small if any benefit on current cpus. 440 // Note: CMOV brings small if any benefit on current cpus.
@@ -450,8 +446,8 @@ public:
450 void SFENCE(); 446 void SFENCE();
451 447
452 // Bit scan 448 // Bit scan
453 void BSF(int bits, X64Reg dest, OpArg src); //bottom bit to top bit 449 void BSF(int bits, X64Reg dest, const OpArg& src); // Bottom bit to top bit
454 void BSR(int bits, X64Reg dest, OpArg src); //top bit to bottom bit 450 void BSR(int bits, X64Reg dest, const OpArg& src); // Top bit to bottom bit
455 451
456 // Cache control 452 // Cache control
457 enum PrefetchLevel 453 enum PrefetchLevel
@@ -462,67 +458,67 @@ public:
462 PF_T2, //Levels 3+ (aliased to T0 on AMD) 458 PF_T2, //Levels 3+ (aliased to T0 on AMD)
463 }; 459 };
464 void PREFETCH(PrefetchLevel level, OpArg arg); 460 void PREFETCH(PrefetchLevel level, OpArg arg);
465 void MOVNTI(int bits, OpArg dest, X64Reg src); 461 void MOVNTI(int bits, const OpArg& dest, X64Reg src);
466 void MOVNTDQ(OpArg arg, X64Reg regOp); 462 void MOVNTDQ(const OpArg& arg, X64Reg regOp);
467 void MOVNTPS(OpArg arg, X64Reg regOp); 463 void MOVNTPS(const OpArg& arg, X64Reg regOp);
468 void MOVNTPD(OpArg arg, X64Reg regOp); 464 void MOVNTPD(const OpArg& arg, X64Reg regOp);
469 465
470 // Multiplication / division 466 // Multiplication / division
471 void MUL(int bits, OpArg src); //UNSIGNED 467 void MUL(int bits, const OpArg& src); //UNSIGNED
472 void IMUL(int bits, OpArg src); //SIGNED 468 void IMUL(int bits, const OpArg& src); //SIGNED
473 void IMUL(int bits, X64Reg regOp, OpArg src); 469 void IMUL(int bits, X64Reg regOp, const OpArg& src);
474 void IMUL(int bits, X64Reg regOp, OpArg src, OpArg imm); 470 void IMUL(int bits, X64Reg regOp, const OpArg& src, const OpArg& imm);
475 void DIV(int bits, OpArg src); 471 void DIV(int bits, const OpArg& src);
476 void IDIV(int bits, OpArg src); 472 void IDIV(int bits, const OpArg& src);
477 473
478 // Shift 474 // Shift
479 void ROL(int bits, OpArg dest, OpArg shift); 475 void ROL(int bits, const OpArg& dest, const OpArg& shift);
480 void ROR(int bits, OpArg dest, OpArg shift); 476 void ROR(int bits, const OpArg& dest, const OpArg& shift);
481 void RCL(int bits, OpArg dest, OpArg shift); 477 void RCL(int bits, const OpArg& dest, const OpArg& shift);
482 void RCR(int bits, OpArg dest, OpArg shift); 478 void RCR(int bits, const OpArg& dest, const OpArg& shift);
483 void SHL(int bits, OpArg dest, OpArg shift); 479 void SHL(int bits, const OpArg& dest, const OpArg& shift);
484 void SHR(int bits, OpArg dest, OpArg shift); 480 void SHR(int bits, const OpArg& dest, const OpArg& shift);
485 void SAR(int bits, OpArg dest, OpArg shift); 481 void SAR(int bits, const OpArg& dest, const OpArg& shift);
486 482
487 // Bit Test 483 // Bit Test
488 void BT(int bits, OpArg dest, OpArg index); 484 void BT(int bits, const OpArg& dest, const OpArg& index);
489 void BTS(int bits, OpArg dest, OpArg index); 485 void BTS(int bits, const OpArg& dest, const OpArg& index);
490 void BTR(int bits, OpArg dest, OpArg index); 486 void BTR(int bits, const OpArg& dest, const OpArg& index);
491 void BTC(int bits, OpArg dest, OpArg index); 487 void BTC(int bits, const OpArg& dest, const OpArg& index);
492 488
493 // Double-Precision Shift 489 // Double-Precision Shift
494 void SHRD(int bits, OpArg dest, OpArg src, OpArg shift); 490 void SHRD(int bits, const OpArg& dest, const OpArg& src, const OpArg& shift);
495 void SHLD(int bits, OpArg dest, OpArg src, OpArg shift); 491 void SHLD(int bits, const OpArg& dest, const OpArg& src, const OpArg& shift);
496 492
497 // Extend EAX into EDX in various ways 493 // Extend EAX into EDX in various ways
498 void CWD(int bits = 16); 494 void CWD(int bits = 16);
499 inline void CDQ() {CWD(32);} 495 void CDQ() {CWD(32);}
500 inline void CQO() {CWD(64);} 496 void CQO() {CWD(64);}
501 void CBW(int bits = 8); 497 void CBW(int bits = 8);
502 inline void CWDE() {CBW(16);} 498 void CWDE() {CBW(16);}
503 inline void CDQE() {CBW(32);} 499 void CDQE() {CBW(32);}
504 500
505 // Load effective address 501 // Load effective address
506 void LEA(int bits, X64Reg dest, OpArg src); 502 void LEA(int bits, X64Reg dest, OpArg src);
507 503
508 // Integer arithmetic 504 // Integer arithmetic
509 void NEG (int bits, OpArg src); 505 void NEG(int bits, const OpArg& src);
510 void ADD (int bits, const OpArg &a1, const OpArg &a2); 506 void ADD(int bits, const OpArg& a1, const OpArg& a2);
511 void ADC (int bits, const OpArg &a1, const OpArg &a2); 507 void ADC(int bits, const OpArg& a1, const OpArg& a2);
512 void SUB (int bits, const OpArg &a1, const OpArg &a2); 508 void SUB(int bits, const OpArg& a1, const OpArg& a2);
513 void SBB (int bits, const OpArg &a1, const OpArg &a2); 509 void SBB(int bits, const OpArg& a1, const OpArg& a2);
514 void AND (int bits, const OpArg &a1, const OpArg &a2); 510 void AND(int bits, const OpArg& a1, const OpArg& a2);
515 void CMP (int bits, const OpArg &a1, const OpArg &a2); 511 void CMP(int bits, const OpArg& a1, const OpArg& a2);
516 512
517 // Bit operations 513 // Bit operations
518 void NOT (int bits, OpArg src); 514 void NOT (int bits, const OpArg& src);
519 void OR (int bits, const OpArg &a1, const OpArg &a2); 515 void OR(int bits, const OpArg& a1, const OpArg& a2);
520 void XOR (int bits, const OpArg &a1, const OpArg &a2); 516 void XOR(int bits, const OpArg& a1, const OpArg& a2);
521 void MOV (int bits, const OpArg &a1, const OpArg &a2); 517 void MOV(int bits, const OpArg& a1, const OpArg& a2);
522 void TEST(int bits, const OpArg &a1, const OpArg &a2); 518 void TEST(int bits, const OpArg& a1, const OpArg& a2);
523 519
524 // Are these useful at all? Consider removing. 520 // Are these useful at all? Consider removing.
525 void XCHG(int bits, const OpArg &a1, const OpArg &a2); 521 void XCHG(int bits, const OpArg& a1, const OpArg& a2);
526 void XCHG_AHAL(); 522 void XCHG_AHAL();
527 523
528 // Byte swapping (32 and 64-bit only). 524 // Byte swapping (32 and 64-bit only).
@@ -536,13 +532,13 @@ public:
536 void MOVBE(int dbits, const OpArg& dest, const OpArg& src); 532 void MOVBE(int dbits, const OpArg& dest, const OpArg& src);
537 533
538 // Available only on AMD >= Phenom or Intel >= Haswell 534 // Available only on AMD >= Phenom or Intel >= Haswell
539 void LZCNT(int bits, X64Reg dest, OpArg src); 535 void LZCNT(int bits, X64Reg dest, const OpArg& src);
540 // Note: this one is actually part of BMI1 536 // Note: this one is actually part of BMI1
541 void TZCNT(int bits, X64Reg dest, OpArg src); 537 void TZCNT(int bits, X64Reg dest, const OpArg& src);
542 538
543 // WARNING - These two take 11-13 cycles and are VectorPath! (AMD64) 539 // WARNING - These two take 11-13 cycles and are VectorPath! (AMD64)
544 void STMXCSR(OpArg memloc); 540 void STMXCSR(const OpArg& memloc);
545 void LDMXCSR(OpArg memloc); 541 void LDMXCSR(const OpArg& memloc);
546 542
547 // Prefixes 543 // Prefixes
548 void LOCK(); 544 void LOCK();
@@ -569,259 +565,242 @@ public:
569 x87_FPUBusy = 0x8000, 565 x87_FPUBusy = 0x8000,
570 }; 566 };
571 567
572 void FLD(int bits, OpArg src); 568 void FLD(int bits, const OpArg& src);
573 void FST(int bits, OpArg dest); 569 void FST(int bits, const OpArg& dest);
574 void FSTP(int bits, OpArg dest); 570 void FSTP(int bits, const OpArg& dest);
575 void FNSTSW_AX(); 571 void FNSTSW_AX();
576 void FWAIT(); 572 void FWAIT();
577 573
578 // SSE/SSE2: Floating point arithmetic 574 // SSE/SSE2: Floating point arithmetic
579 void ADDSS(X64Reg regOp, OpArg arg); 575 void ADDSS(X64Reg regOp, const OpArg& arg);
580 void ADDSD(X64Reg regOp, OpArg arg); 576 void ADDSD(X64Reg regOp, const OpArg& arg);
581 void SUBSS(X64Reg regOp, OpArg arg); 577 void SUBSS(X64Reg regOp, const OpArg& arg);
582 void SUBSD(X64Reg regOp, OpArg arg); 578 void SUBSD(X64Reg regOp, const OpArg& arg);
583 void MULSS(X64Reg regOp, OpArg arg); 579 void MULSS(X64Reg regOp, const OpArg& arg);
584 void MULSD(X64Reg regOp, OpArg arg); 580 void MULSD(X64Reg regOp, const OpArg& arg);
585 void DIVSS(X64Reg regOp, OpArg arg); 581 void DIVSS(X64Reg regOp, const OpArg& arg);
586 void DIVSD(X64Reg regOp, OpArg arg); 582 void DIVSD(X64Reg regOp, const OpArg& arg);
587 void MINSS(X64Reg regOp, OpArg arg); 583 void MINSS(X64Reg regOp, const OpArg& arg);
588 void MINSD(X64Reg regOp, OpArg arg); 584 void MINSD(X64Reg regOp, const OpArg& arg);
589 void MAXSS(X64Reg regOp, OpArg arg); 585 void MAXSS(X64Reg regOp, const OpArg& arg);
590 void MAXSD(X64Reg regOp, OpArg arg); 586 void MAXSD(X64Reg regOp, const OpArg& arg);
591 void SQRTSS(X64Reg regOp, OpArg arg); 587 void SQRTSS(X64Reg regOp, const OpArg& arg);
592 void SQRTSD(X64Reg regOp, OpArg arg); 588 void SQRTSD(X64Reg regOp, const OpArg& arg);
593 void RSQRTSS(X64Reg regOp, OpArg arg); 589 void RSQRTSS(X64Reg regOp, const OpArg& arg);
594 590
595 // SSE/SSE2: Floating point bitwise (yes) 591 // SSE/SSE2: Floating point bitwise (yes)
596 void CMPSS(X64Reg regOp, OpArg arg, u8 compare); 592 void CMPSS(X64Reg regOp, const OpArg& arg, u8 compare);
597 void CMPSD(X64Reg regOp, OpArg arg, u8 compare); 593 void CMPSD(X64Reg regOp, const OpArg& arg, u8 compare);
598 594
599 inline void CMPEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_EQ); } 595 void CMPEQSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_EQ); }
600 inline void CMPLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LT); } 596 void CMPLTSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_LT); }
601 inline void CMPLESS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_LE); } 597 void CMPLESS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_LE); }
602 inline void CMPUNORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_UNORD); } 598 void CMPUNORDSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_UNORD); }
603 inline void CMPNEQSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NEQ); } 599 void CMPNEQSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_NEQ); }
604 inline void CMPNLTSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_NLT); } 600 void CMPNLTSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_NLT); }
605 inline void CMPORDSS(X64Reg regOp, OpArg arg) { CMPSS(regOp, arg, CMP_ORD); } 601 void CMPORDSS(X64Reg regOp, const OpArg& arg) { CMPSS(regOp, arg, CMP_ORD); }
606 602
607 // SSE/SSE2: Floating point packed arithmetic (x4 for float, x2 for double) 603 // SSE/SSE2: Floating point packed arithmetic (x4 for float, x2 for double)
608 void ADDPS(X64Reg regOp, OpArg arg); 604 void ADDPS(X64Reg regOp, const OpArg& arg);
609 void ADDPD(X64Reg regOp, OpArg arg); 605 void ADDPD(X64Reg regOp, const OpArg& arg);
610 void SUBPS(X64Reg regOp, OpArg arg); 606 void SUBPS(X64Reg regOp, const OpArg& arg);
611 void SUBPD(X64Reg regOp, OpArg arg); 607 void SUBPD(X64Reg regOp, const OpArg& arg);
612 void CMPPS(X64Reg regOp, OpArg arg, u8 compare); 608 void CMPPS(X64Reg regOp, const OpArg& arg, u8 compare);
613 void CMPPD(X64Reg regOp, OpArg arg, u8 compare); 609 void CMPPD(X64Reg regOp, const OpArg& arg, u8 compare);
614 void MULPS(X64Reg regOp, OpArg arg); 610 void MULPS(X64Reg regOp, const OpArg& arg);
615 void MULPD(X64Reg regOp, OpArg arg); 611 void MULPD(X64Reg regOp, const OpArg& arg);
616 void DIVPS(X64Reg regOp, OpArg arg); 612 void DIVPS(X64Reg regOp, const OpArg& arg);
617 void DIVPD(X64Reg regOp, OpArg arg); 613 void DIVPD(X64Reg regOp, const OpArg& arg);
618 void MINPS(X64Reg regOp, OpArg arg); 614 void MINPS(X64Reg regOp, const OpArg& arg);
619 void MINPD(X64Reg regOp, OpArg arg); 615 void MINPD(X64Reg regOp, const OpArg& arg);
620 void MAXPS(X64Reg regOp, OpArg arg); 616 void MAXPS(X64Reg regOp, const OpArg& arg);
621 void MAXPD(X64Reg regOp, OpArg arg); 617 void MAXPD(X64Reg regOp, const OpArg& arg);
622 void SQRTPS(X64Reg regOp, OpArg arg); 618 void SQRTPS(X64Reg regOp, const OpArg& arg);
623 void SQRTPD(X64Reg regOp, OpArg arg); 619 void SQRTPD(X64Reg regOp, const OpArg& arg);
624 void RCPPS(X64Reg regOp, OpArg arg); 620 void RCPPS(X64Reg regOp, const OpArg& arg);
625 void RSQRTPS(X64Reg regOp, OpArg arg); 621 void RSQRTPS(X64Reg regOp, const OpArg& arg);
626 622
627 // SSE/SSE2: Floating point packed bitwise (x4 for float, x2 for double) 623 // SSE/SSE2: Floating point packed bitwise (x4 for float, x2 for double)
628 void ANDPS(X64Reg regOp, OpArg arg); 624 void ANDPS(X64Reg regOp, const OpArg& arg);
629 void ANDPD(X64Reg regOp, OpArg arg); 625 void ANDPD(X64Reg regOp, const OpArg& arg);
630 void ANDNPS(X64Reg regOp, OpArg arg); 626 void ANDNPS(X64Reg regOp, const OpArg& arg);
631 void ANDNPD(X64Reg regOp, OpArg arg); 627 void ANDNPD(X64Reg regOp, const OpArg& arg);
632 void ORPS(X64Reg regOp, OpArg arg); 628 void ORPS(X64Reg regOp, const OpArg& arg);
633 void ORPD(X64Reg regOp, OpArg arg); 629 void ORPD(X64Reg regOp, const OpArg& arg);
634 void XORPS(X64Reg regOp, OpArg arg); 630 void XORPS(X64Reg regOp, const OpArg& arg);
635 void XORPD(X64Reg regOp, OpArg arg); 631 void XORPD(X64Reg regOp, const OpArg& arg);
636 632
637 // SSE/SSE2: Shuffle components. These are tricky - see Intel documentation. 633 // SSE/SSE2: Shuffle components. These are tricky - see Intel documentation.
638 void SHUFPS(X64Reg regOp, OpArg arg, u8 shuffle); 634 void SHUFPS(X64Reg regOp, const OpArg& arg, u8 shuffle);
639 void SHUFPD(X64Reg regOp, OpArg arg, u8 shuffle); 635 void SHUFPD(X64Reg regOp, const OpArg& arg, u8 shuffle);
640 636
641 // SSE/SSE2: Useful alternative to shuffle in some cases. 637 // SSE/SSE2: Useful alternative to shuffle in some cases.
642 void MOVDDUP(X64Reg regOp, OpArg arg); 638 void MOVDDUP(X64Reg regOp, const OpArg& arg);
643
644 // TODO: Actually implement
645#if 0
646 // SSE3: Horizontal operations in SIMD registers. Could be useful for various VFPU things like dot products...
647 void ADDSUBPS(X64Reg dest, OpArg src);
648 void ADDSUBPD(X64Reg dest, OpArg src);
649 void HADDPD(X64Reg dest, OpArg src);
650 void HSUBPS(X64Reg dest, OpArg src);
651 void HSUBPD(X64Reg dest, OpArg src);
652
653 // SSE4: Further horizontal operations - dot products. These are weirdly flexible, the arg contains both a read mask and a write "mask".
654 void DPPD(X64Reg dest, OpArg src, u8 arg);
655
656 // These are probably useful for VFPU emulation.
657 void INSERTPS(X64Reg dest, OpArg src, u8 arg);
658 void EXTRACTPS(OpArg dest, X64Reg src, u8 arg);
659#endif
660 639
661 // SSE3: Horizontal operations in SIMD registers. Very slow! shufps-based code beats it handily on Ivy. 640 // SSE3: Horizontal operations in SIMD registers. Very slow! shufps-based code beats it handily on Ivy.
662 void HADDPS(X64Reg dest, OpArg src); 641 void HADDPS(X64Reg dest, const OpArg& src);
663 642
664 // SSE4: Further horizontal operations - dot products. These are weirdly flexible, the arg contains both a read mask and a write "mask". 643 // SSE4: Further horizontal operations - dot products. These are weirdly flexible, the arg contains both a read mask and a write "mask".
665 void DPPS(X64Reg dest, OpArg src, u8 arg); 644 void DPPS(X64Reg dest, const OpArg& src, u8 arg);
666 645
667 void UNPCKLPS(X64Reg dest, OpArg src); 646 void UNPCKLPS(X64Reg dest, const OpArg& src);
668 void UNPCKHPS(X64Reg dest, OpArg src); 647 void UNPCKHPS(X64Reg dest, const OpArg& src);
669 void UNPCKLPD(X64Reg dest, OpArg src); 648 void UNPCKLPD(X64Reg dest, const OpArg& src);
670 void UNPCKHPD(X64Reg dest, OpArg src); 649 void UNPCKHPD(X64Reg dest, const OpArg& src);
671 650
672 // SSE/SSE2: Compares. 651 // SSE/SSE2: Compares.
673 void COMISS(X64Reg regOp, OpArg arg); 652 void COMISS(X64Reg regOp, const OpArg& arg);
674 void COMISD(X64Reg regOp, OpArg arg); 653 void COMISD(X64Reg regOp, const OpArg& arg);
675 void UCOMISS(X64Reg regOp, OpArg arg); 654 void UCOMISS(X64Reg regOp, const OpArg& arg);
676 void UCOMISD(X64Reg regOp, OpArg arg); 655 void UCOMISD(X64Reg regOp, const OpArg& arg);
677 656
678 // SSE/SSE2: Moves. Use the right data type for your data, in most cases. 657 // SSE/SSE2: Moves. Use the right data type for your data, in most cases.
679 void MOVAPS(X64Reg regOp, OpArg arg); 658 void MOVAPS(X64Reg regOp, const OpArg& arg);
680 void MOVAPD(X64Reg regOp, OpArg arg); 659 void MOVAPD(X64Reg regOp, const OpArg& arg);
681 void MOVAPS(OpArg arg, X64Reg regOp); 660 void MOVAPS(const OpArg& arg, X64Reg regOp);
682 void MOVAPD(OpArg arg, X64Reg regOp); 661 void MOVAPD(const OpArg& arg, X64Reg regOp);
683 662
684 void MOVUPS(X64Reg regOp, OpArg arg); 663 void MOVUPS(X64Reg regOp, const OpArg& arg);
685 void MOVUPD(X64Reg regOp, OpArg arg); 664 void MOVUPD(X64Reg regOp, const OpArg& arg);
686 void MOVUPS(OpArg arg, X64Reg regOp); 665 void MOVUPS(const OpArg& arg, X64Reg regOp);
687 void MOVUPD(OpArg arg, X64Reg regOp); 666 void MOVUPD(const OpArg& arg, X64Reg regOp);
688 667
689 void MOVDQA(X64Reg regOp, OpArg arg); 668 void MOVDQA(X64Reg regOp, const OpArg& arg);
690 void MOVDQA(OpArg arg, X64Reg regOp); 669 void MOVDQA(const OpArg& arg, X64Reg regOp);
691 void MOVDQU(X64Reg regOp, OpArg arg); 670 void MOVDQU(X64Reg regOp, const OpArg& arg);
692 void MOVDQU(OpArg arg, X64Reg regOp); 671 void MOVDQU(const OpArg& arg, X64Reg regOp);
693 672
694 void MOVSS(X64Reg regOp, OpArg arg); 673 void MOVSS(X64Reg regOp, const OpArg& arg);
695 void MOVSD(X64Reg regOp, OpArg arg); 674 void MOVSD(X64Reg regOp, const OpArg& arg);
696 void MOVSS(OpArg arg, X64Reg regOp); 675 void MOVSS(const OpArg& arg, X64Reg regOp);
697 void MOVSD(OpArg arg, X64Reg regOp); 676 void MOVSD(const OpArg& arg, X64Reg regOp);
698 677
699 void MOVLPS(X64Reg regOp, OpArg arg); 678 void MOVLPS(X64Reg regOp, const OpArg& arg);
700 void MOVLPD(X64Reg regOp, OpArg arg); 679 void MOVLPD(X64Reg regOp, const OpArg& arg);
701 void MOVLPS(OpArg arg, X64Reg regOp); 680 void MOVLPS(const OpArg& arg, X64Reg regOp);
702 void MOVLPD(OpArg arg, X64Reg regOp); 681 void MOVLPD(const OpArg& arg, X64Reg regOp);
703 682
704 void MOVHPS(X64Reg regOp, OpArg arg); 683 void MOVHPS(X64Reg regOp, const OpArg& arg);
705 void MOVHPD(X64Reg regOp, OpArg arg); 684 void MOVHPD(X64Reg regOp, const OpArg& arg);
706 void MOVHPS(OpArg arg, X64Reg regOp); 685 void MOVHPS(const OpArg& arg, X64Reg regOp);
707 void MOVHPD(OpArg arg, X64Reg regOp); 686 void MOVHPD(const OpArg& arg, X64Reg regOp);
708 687
709 void MOVHLPS(X64Reg regOp1, X64Reg regOp2); 688 void MOVHLPS(X64Reg regOp1, X64Reg regOp2);
710 void MOVLHPS(X64Reg regOp1, X64Reg regOp2); 689 void MOVLHPS(X64Reg regOp1, X64Reg regOp2);
711 690
712 void MOVD_xmm(X64Reg dest, const OpArg &arg); 691 void MOVD_xmm(X64Reg dest, const OpArg& arg);
713 void MOVQ_xmm(X64Reg dest, OpArg arg); 692 void MOVQ_xmm(X64Reg dest, OpArg arg);
714 void MOVD_xmm(const OpArg &arg, X64Reg src); 693 void MOVD_xmm(const OpArg& arg, X64Reg src);
715 void MOVQ_xmm(OpArg arg, X64Reg src); 694 void MOVQ_xmm(OpArg arg, X64Reg src);
716 695
717 // SSE/SSE2: Generates a mask from the high bits of the components of the packed register in question. 696 // SSE/SSE2: Generates a mask from the high bits of the components of the packed register in question.
718 void MOVMSKPS(X64Reg dest, OpArg arg); 697 void MOVMSKPS(X64Reg dest, const OpArg& arg);
719 void MOVMSKPD(X64Reg dest, OpArg arg); 698 void MOVMSKPD(X64Reg dest, const OpArg& arg);
720 699
721 // SSE2: Selective byte store, mask in src register. EDI/RDI specifies store address. This is a weird one. 700 // SSE2: Selective byte store, mask in src register. EDI/RDI specifies store address. This is a weird one.
722 void MASKMOVDQU(X64Reg dest, X64Reg src); 701 void MASKMOVDQU(X64Reg dest, X64Reg src);
723 void LDDQU(X64Reg dest, OpArg src); 702 void LDDQU(X64Reg dest, const OpArg& src);
724 703
725 // SSE/SSE2: Data type conversions. 704 // SSE/SSE2: Data type conversions.
726 void CVTPS2PD(X64Reg dest, OpArg src); 705 void CVTPS2PD(X64Reg dest, const OpArg& src);
727 void CVTPD2PS(X64Reg dest, OpArg src); 706 void CVTPD2PS(X64Reg dest, const OpArg& src);
728 void CVTSS2SD(X64Reg dest, OpArg src); 707 void CVTSS2SD(X64Reg dest, const OpArg& src);
729 void CVTSI2SS(X64Reg dest, OpArg src); 708 void CVTSI2SS(X64Reg dest, const OpArg& src);
730 void CVTSD2SS(X64Reg dest, OpArg src); 709 void CVTSD2SS(X64Reg dest, const OpArg& src);
731 void CVTSI2SD(X64Reg dest, OpArg src); 710 void CVTSI2SD(X64Reg dest, const OpArg& src);
732 void CVTDQ2PD(X64Reg regOp, OpArg arg); 711 void CVTDQ2PD(X64Reg regOp, const OpArg& arg);
733 void CVTPD2DQ(X64Reg regOp, OpArg arg); 712 void CVTPD2DQ(X64Reg regOp, const OpArg& arg);
734 void CVTDQ2PS(X64Reg regOp, OpArg arg); 713 void CVTDQ2PS(X64Reg regOp, const OpArg& arg);
735 void CVTPS2DQ(X64Reg regOp, OpArg arg); 714 void CVTPS2DQ(X64Reg regOp, const OpArg& arg);
736 715
737 void CVTTPS2DQ(X64Reg regOp, OpArg arg); 716 void CVTTPS2DQ(X64Reg regOp, const OpArg& arg);
738 void CVTTPD2DQ(X64Reg regOp, OpArg arg); 717 void CVTTPD2DQ(X64Reg regOp, const OpArg& arg);
739 718
740 // Destinations are X64 regs (rax, rbx, ...) for these instructions. 719 // Destinations are X64 regs (rax, rbx, ...) for these instructions.
741 void CVTSS2SI(X64Reg xregdest, OpArg src); 720 void CVTSS2SI(X64Reg xregdest, const OpArg& src);
742 void CVTSD2SI(X64Reg xregdest, OpArg src); 721 void CVTSD2SI(X64Reg xregdest, const OpArg& src);
743 void CVTTSS2SI(X64Reg xregdest, OpArg arg); 722 void CVTTSS2SI(X64Reg xregdest, const OpArg& arg);
744 void CVTTSD2SI(X64Reg xregdest, OpArg arg); 723 void CVTTSD2SI(X64Reg xregdest, const OpArg& arg);
745 724
746 // SSE2: Packed integer instructions 725 // SSE2: Packed integer instructions
747 void PACKSSDW(X64Reg dest, OpArg arg); 726 void PACKSSDW(X64Reg dest, const OpArg& arg);
748 void PACKSSWB(X64Reg dest, OpArg arg); 727 void PACKSSWB(X64Reg dest, const OpArg& arg);
749 void PACKUSDW(X64Reg dest, OpArg arg); 728 void PACKUSDW(X64Reg dest, const OpArg& arg);
750 void PACKUSWB(X64Reg dest, OpArg arg); 729 void PACKUSWB(X64Reg dest, const OpArg& arg);
751 730
752 void PUNPCKLBW(X64Reg dest, const OpArg &arg); 731 void PUNPCKLBW(X64Reg dest, const OpArg &arg);
753 void PUNPCKLWD(X64Reg dest, const OpArg &arg); 732 void PUNPCKLWD(X64Reg dest, const OpArg &arg);
754 void PUNPCKLDQ(X64Reg dest, const OpArg &arg); 733 void PUNPCKLDQ(X64Reg dest, const OpArg &arg);
755 void PUNPCKLQDQ(X64Reg dest, const OpArg &arg); 734 void PUNPCKLQDQ(X64Reg dest, const OpArg &arg);
756 735
757 void PTEST(X64Reg dest, OpArg arg); 736 void PTEST(X64Reg dest, const OpArg& arg);
758 void PAND(X64Reg dest, OpArg arg); 737 void PAND(X64Reg dest, const OpArg& arg);
759 void PANDN(X64Reg dest, OpArg arg); 738 void PANDN(X64Reg dest, const OpArg& arg);
760 void PXOR(X64Reg dest, OpArg arg); 739 void PXOR(X64Reg dest, const OpArg& arg);
761 void POR(X64Reg dest, OpArg arg); 740 void POR(X64Reg dest, const OpArg& arg);
762 741
763 void PADDB(X64Reg dest, OpArg arg); 742 void PADDB(X64Reg dest, const OpArg& arg);
764 void PADDW(X64Reg dest, OpArg arg); 743 void PADDW(X64Reg dest, const OpArg& arg);
765 void PADDD(X64Reg dest, OpArg arg); 744 void PADDD(X64Reg dest, const OpArg& arg);
766 void PADDQ(X64Reg dest, OpArg arg); 745 void PADDQ(X64Reg dest, const OpArg& arg);
767 746
768 void PADDSB(X64Reg dest, OpArg arg); 747 void PADDSB(X64Reg dest, const OpArg& arg);
769 void PADDSW(X64Reg dest, OpArg arg); 748 void PADDSW(X64Reg dest, const OpArg& arg);
770 void PADDUSB(X64Reg dest, OpArg arg); 749 void PADDUSB(X64Reg dest, const OpArg& arg);
771 void PADDUSW(X64Reg dest, OpArg arg); 750 void PADDUSW(X64Reg dest, const OpArg& arg);
772 751
773 void PSUBB(X64Reg dest, OpArg arg); 752 void PSUBB(X64Reg dest, const OpArg& arg);
774 void PSUBW(X64Reg dest, OpArg arg); 753 void PSUBW(X64Reg dest, const OpArg& arg);
775 void PSUBD(X64Reg dest, OpArg arg); 754 void PSUBD(X64Reg dest, const OpArg& arg);
776 void PSUBQ(X64Reg dest, OpArg arg); 755 void PSUBQ(X64Reg dest, const OpArg& arg);
777 756
778 void PSUBSB(X64Reg dest, OpArg arg); 757 void PSUBSB(X64Reg dest, const OpArg& arg);
779 void PSUBSW(X64Reg dest, OpArg arg); 758 void PSUBSW(X64Reg dest, const OpArg& arg);
780 void PSUBUSB(X64Reg dest, OpArg arg); 759 void PSUBUSB(X64Reg dest, const OpArg& arg);
781 void PSUBUSW(X64Reg dest, OpArg arg); 760 void PSUBUSW(X64Reg dest, const OpArg& arg);
782 761
783 void PAVGB(X64Reg dest, OpArg arg); 762 void PAVGB(X64Reg dest, const OpArg& arg);
784 void PAVGW(X64Reg dest, OpArg arg); 763 void PAVGW(X64Reg dest, const OpArg& arg);
785 764
786 void PCMPEQB(X64Reg dest, OpArg arg); 765 void PCMPEQB(X64Reg dest, const OpArg& arg);
787 void PCMPEQW(X64Reg dest, OpArg arg); 766 void PCMPEQW(X64Reg dest, const OpArg& arg);
788 void PCMPEQD(X64Reg dest, OpArg arg); 767 void PCMPEQD(X64Reg dest, const OpArg& arg);
789 768
790 void PCMPGTB(X64Reg dest, OpArg arg); 769 void PCMPGTB(X64Reg dest, const OpArg& arg);
791 void PCMPGTW(X64Reg dest, OpArg arg); 770 void PCMPGTW(X64Reg dest, const OpArg& arg);
792 void PCMPGTD(X64Reg dest, OpArg arg); 771 void PCMPGTD(X64Reg dest, const OpArg& arg);
793 772
794 void PEXTRW(X64Reg dest, OpArg arg, u8 subreg); 773 void PEXTRW(X64Reg dest, const OpArg& arg, u8 subreg);
795 void PINSRW(X64Reg dest, OpArg arg, u8 subreg); 774 void PINSRW(X64Reg dest, const OpArg& arg, u8 subreg);
796 775
797 void PMADDWD(X64Reg dest, OpArg arg); 776 void PMADDWD(X64Reg dest, const OpArg& arg);
798 void PSADBW(X64Reg dest, OpArg arg); 777 void PSADBW(X64Reg dest, const OpArg& arg);
799 778
800 void PMAXSW(X64Reg dest, OpArg arg); 779 void PMAXSW(X64Reg dest, const OpArg& arg);
801 void PMAXUB(X64Reg dest, OpArg arg); 780 void PMAXUB(X64Reg dest, const OpArg& arg);
802 void PMINSW(X64Reg dest, OpArg arg); 781 void PMINSW(X64Reg dest, const OpArg& arg);
803 void PMINUB(X64Reg dest, OpArg arg); 782 void PMINUB(X64Reg dest, const OpArg& arg);
804 // SSE4: More MAX/MIN instructions. 783 // SSE4: More MAX/MIN instructions.
805 void PMINSB(X64Reg dest, OpArg arg); 784 void PMINSB(X64Reg dest, const OpArg& arg);
806 void PMINSD(X64Reg dest, OpArg arg); 785 void PMINSD(X64Reg dest, const OpArg& arg);
807 void PMINUW(X64Reg dest, OpArg arg); 786 void PMINUW(X64Reg dest, const OpArg& arg);
808 void PMINUD(X64Reg dest, OpArg arg); 787 void PMINUD(X64Reg dest, const OpArg& arg);
809 void PMAXSB(X64Reg dest, OpArg arg); 788 void PMAXSB(X64Reg dest, const OpArg& arg);
810 void PMAXSD(X64Reg dest, OpArg arg); 789 void PMAXSD(X64Reg dest, const OpArg& arg);
811 void PMAXUW(X64Reg dest, OpArg arg); 790 void PMAXUW(X64Reg dest, const OpArg& arg);
812 void PMAXUD(X64Reg dest, OpArg arg); 791 void PMAXUD(X64Reg dest, const OpArg& arg);
813 792
814 void PMOVMSKB(X64Reg dest, OpArg arg); 793 void PMOVMSKB(X64Reg dest, const OpArg& arg);
815 void PSHUFD(X64Reg dest, OpArg arg, u8 shuffle); 794 void PSHUFD(X64Reg dest, const OpArg& arg, u8 shuffle);
816 void PSHUFB(X64Reg dest, OpArg arg); 795 void PSHUFB(X64Reg dest, const OpArg& arg);
817 796
818 void PSHUFLW(X64Reg dest, OpArg arg, u8 shuffle); 797 void PSHUFLW(X64Reg dest, const OpArg& arg, u8 shuffle);
819 void PSHUFHW(X64Reg dest, OpArg arg, u8 shuffle); 798 void PSHUFHW(X64Reg dest, const OpArg& arg, u8 shuffle);
820 799
821 void PSRLW(X64Reg reg, int shift); 800 void PSRLW(X64Reg reg, int shift);
822 void PSRLD(X64Reg reg, int shift); 801 void PSRLD(X64Reg reg, int shift);
823 void PSRLQ(X64Reg reg, int shift); 802 void PSRLQ(X64Reg reg, int shift);
824 void PSRLQ(X64Reg reg, OpArg arg); 803 void PSRLQ(X64Reg reg, const OpArg& arg);
825 void PSRLDQ(X64Reg reg, int shift); 804 void PSRLDQ(X64Reg reg, int shift);
826 805
827 void PSLLW(X64Reg reg, int shift); 806 void PSLLW(X64Reg reg, int shift);
@@ -833,198 +812,198 @@ public:
833 void PSRAD(X64Reg reg, int shift); 812 void PSRAD(X64Reg reg, int shift);
834 813
835 // SSE4: data type conversions 814 // SSE4: data type conversions
836 void PMOVSXBW(X64Reg dest, OpArg arg); 815 void PMOVSXBW(X64Reg dest, const OpArg& arg);
837 void PMOVSXBD(X64Reg dest, OpArg arg); 816 void PMOVSXBD(X64Reg dest, const OpArg& arg);
838 void PMOVSXBQ(X64Reg dest, OpArg arg); 817 void PMOVSXBQ(X64Reg dest, const OpArg& arg);
839 void PMOVSXWD(X64Reg dest, OpArg arg); 818 void PMOVSXWD(X64Reg dest, const OpArg& arg);
840 void PMOVSXWQ(X64Reg dest, OpArg arg); 819 void PMOVSXWQ(X64Reg dest, const OpArg& arg);
841 void PMOVSXDQ(X64Reg dest, OpArg arg); 820 void PMOVSXDQ(X64Reg dest, const OpArg& arg);
842 void PMOVZXBW(X64Reg dest, OpArg arg); 821 void PMOVZXBW(X64Reg dest, const OpArg& arg);
843 void PMOVZXBD(X64Reg dest, OpArg arg); 822 void PMOVZXBD(X64Reg dest, const OpArg& arg);
844 void PMOVZXBQ(X64Reg dest, OpArg arg); 823 void PMOVZXBQ(X64Reg dest, const OpArg& arg);
845 void PMOVZXWD(X64Reg dest, OpArg arg); 824 void PMOVZXWD(X64Reg dest, const OpArg& arg);
846 void PMOVZXWQ(X64Reg dest, OpArg arg); 825 void PMOVZXWQ(X64Reg dest, const OpArg& arg);
847 void PMOVZXDQ(X64Reg dest, OpArg arg); 826 void PMOVZXDQ(X64Reg dest, const OpArg& arg);
848 827
849 // SSE4: variable blend instructions (xmm0 implicit argument) 828 // SSE4: variable blend instructions (xmm0 implicit argument)
850 void PBLENDVB(X64Reg dest, OpArg arg); 829 void PBLENDVB(X64Reg dest, const OpArg& arg);
851 void BLENDVPS(X64Reg dest, OpArg arg); 830 void BLENDVPS(X64Reg dest, const OpArg& arg);
852 void BLENDVPD(X64Reg dest, OpArg arg); 831 void BLENDVPD(X64Reg dest, const OpArg& arg);
853 void BLENDPS(X64Reg dest, const OpArg& arg, u8 blend); 832 void BLENDPS(X64Reg dest, const OpArg& arg, u8 blend);
854 void BLENDPD(X64Reg dest, const OpArg& arg, u8 blend); 833 void BLENDPD(X64Reg dest, const OpArg& arg, u8 blend);
855 834
856 // SSE4: rounding (see FloatRound for mode or use ROUNDNEARSS, etc. helpers.) 835 // SSE4: rounding (see FloatRound for mode or use ROUNDNEARSS, etc. helpers.)
857 void ROUNDSS(X64Reg dest, OpArg arg, u8 mode); 836 void ROUNDSS(X64Reg dest, const OpArg& arg, u8 mode);
858 void ROUNDSD(X64Reg dest, OpArg arg, u8 mode); 837 void ROUNDSD(X64Reg dest, const OpArg& arg, u8 mode);
859 void ROUNDPS(X64Reg dest, OpArg arg, u8 mode); 838 void ROUNDPS(X64Reg dest, const OpArg& arg, u8 mode);
860 void ROUNDPD(X64Reg dest, OpArg arg, u8 mode); 839 void ROUNDPD(X64Reg dest, const OpArg& arg, u8 mode);
861 840
862 inline void ROUNDNEARSS(X64Reg dest, OpArg arg) { ROUNDSS(dest, arg, FROUND_NEAREST); } 841 void ROUNDNEARSS(X64Reg dest, const OpArg& arg) { ROUNDSS(dest, arg, FROUND_NEAREST); }
863 inline void ROUNDFLOORSS(X64Reg dest, OpArg arg) { ROUNDSS(dest, arg, FROUND_FLOOR); } 842 void ROUNDFLOORSS(X64Reg dest, const OpArg& arg) { ROUNDSS(dest, arg, FROUND_FLOOR); }
864 inline void ROUNDCEILSS(X64Reg dest, OpArg arg) { ROUNDSS(dest, arg, FROUND_CEIL); } 843 void ROUNDCEILSS(X64Reg dest, const OpArg& arg) { ROUNDSS(dest, arg, FROUND_CEIL); }
865 inline void ROUNDZEROSS(X64Reg dest, OpArg arg) { ROUNDSS(dest, arg, FROUND_ZERO); } 844 void ROUNDZEROSS(X64Reg dest, const OpArg& arg) { ROUNDSS(dest, arg, FROUND_ZERO); }
866 845
867 inline void ROUNDNEARSD(X64Reg dest, OpArg arg) { ROUNDSD(dest, arg, FROUND_NEAREST); } 846 void ROUNDNEARSD(X64Reg dest, const OpArg& arg) { ROUNDSD(dest, arg, FROUND_NEAREST); }
868 inline void ROUNDFLOORSD(X64Reg dest, OpArg arg) { ROUNDSD(dest, arg, FROUND_FLOOR); } 847 void ROUNDFLOORSD(X64Reg dest, const OpArg& arg) { ROUNDSD(dest, arg, FROUND_FLOOR); }
869 inline void ROUNDCEILSD(X64Reg dest, OpArg arg) { ROUNDSD(dest, arg, FROUND_CEIL); } 848 void ROUNDCEILSD(X64Reg dest, const OpArg& arg) { ROUNDSD(dest, arg, FROUND_CEIL); }
870 inline void ROUNDZEROSD(X64Reg dest, OpArg arg) { ROUNDSD(dest, arg, FROUND_ZERO); } 849 void ROUNDZEROSD(X64Reg dest, const OpArg& arg) { ROUNDSD(dest, arg, FROUND_ZERO); }
871 850
872 inline void ROUNDNEARPS(X64Reg dest, OpArg arg) { ROUNDPS(dest, arg, FROUND_NEAREST); } 851 void ROUNDNEARPS(X64Reg dest, const OpArg& arg) { ROUNDPS(dest, arg, FROUND_NEAREST); }
873 inline void ROUNDFLOORPS(X64Reg dest, OpArg arg) { ROUNDPS(dest, arg, FROUND_FLOOR); } 852 void ROUNDFLOORPS(X64Reg dest, const OpArg& arg) { ROUNDPS(dest, arg, FROUND_FLOOR); }
874 inline void ROUNDCEILPS(X64Reg dest, OpArg arg) { ROUNDPS(dest, arg, FROUND_CEIL); } 853 void ROUNDCEILPS(X64Reg dest, const OpArg& arg) { ROUNDPS(dest, arg, FROUND_CEIL); }
875 inline void ROUNDZEROPS(X64Reg dest, OpArg arg) { ROUNDPS(dest, arg, FROUND_ZERO); } 854 void ROUNDZEROPS(X64Reg dest, const OpArg& arg) { ROUNDPS(dest, arg, FROUND_ZERO); }
876 855
877 inline void ROUNDNEARPD(X64Reg dest, OpArg arg) { ROUNDPD(dest, arg, FROUND_NEAREST); } 856 void ROUNDNEARPD(X64Reg dest, const OpArg& arg) { ROUNDPD(dest, arg, FROUND_NEAREST); }
878 inline void ROUNDFLOORPD(X64Reg dest, OpArg arg) { ROUNDPD(dest, arg, FROUND_FLOOR); } 857 void ROUNDFLOORPD(X64Reg dest, const OpArg& arg) { ROUNDPD(dest, arg, FROUND_FLOOR); }
879 inline void ROUNDCEILPD(X64Reg dest, OpArg arg) { ROUNDPD(dest, arg, FROUND_CEIL); } 858 void ROUNDCEILPD(X64Reg dest, const OpArg& arg) { ROUNDPD(dest, arg, FROUND_CEIL); }
880 inline void ROUNDZEROPD(X64Reg dest, OpArg arg) { ROUNDPD(dest, arg, FROUND_ZERO); } 859 void ROUNDZEROPD(X64Reg dest, const OpArg& arg) { ROUNDPD(dest, arg, FROUND_ZERO); }
881 860
882 // AVX 861 // AVX
883 void VADDSD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 862 void VADDSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
884 void VSUBSD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 863 void VSUBSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
885 void VMULSD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 864 void VMULSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
886 void VDIVSD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 865 void VDIVSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
887 void VADDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 866 void VADDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
888 void VSUBPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 867 void VSUBPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
889 void VMULPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 868 void VMULPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
890 void VDIVPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 869 void VDIVPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
891 void VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 870 void VSQRTSD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
892 void VSHUFPD(X64Reg regOp1, X64Reg regOp2, OpArg arg, u8 shuffle); 871 void VSHUFPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg, u8 shuffle);
893 void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 872 void VUNPCKLPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
894 void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 873 void VUNPCKHPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
895 874
896 void VANDPS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 875 void VANDPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
897 void VANDPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 876 void VANDPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
898 void VANDNPS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 877 void VANDNPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
899 void VANDNPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 878 void VANDNPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
900 void VORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 879 void VORPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
901 void VORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 880 void VORPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
902 void VXORPS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 881 void VXORPS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
903 void VXORPD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 882 void VXORPD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
904 883
905 void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg); 884 void VPAND(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
906 void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg); 885 void VPANDN(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
907 void VPOR(X64Reg regOp1, X64Reg regOp2, OpArg arg); 886 void VPOR(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
908 void VPXOR(X64Reg regOp1, X64Reg regOp2, OpArg arg); 887 void VPXOR(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
909 888
910 // FMA3 889 // FMA3
911 void VFMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 890 void VFMADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
912 void VFMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 891 void VFMADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
913 void VFMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 892 void VFMADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
914 void VFMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 893 void VFMADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
915 void VFMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 894 void VFMADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
916 void VFMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 895 void VFMADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
917 void VFMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 896 void VFMADD132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
918 void VFMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 897 void VFMADD213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
919 void VFMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 898 void VFMADD231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
920 void VFMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 899 void VFMADD132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
921 void VFMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 900 void VFMADD213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
922 void VFMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 901 void VFMADD231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
923 void VFMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 902 void VFMSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
924 void VFMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 903 void VFMSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
925 void VFMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 904 void VFMSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
926 void VFMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 905 void VFMSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
927 void VFMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 906 void VFMSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
928 void VFMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 907 void VFMSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
929 void VFMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 908 void VFMSUB132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
930 void VFMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 909 void VFMSUB213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
931 void VFMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 910 void VFMSUB231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
932 void VFMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 911 void VFMSUB132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
933 void VFMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 912 void VFMSUB213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
934 void VFMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 913 void VFMSUB231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
935 void VFNMADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 914 void VFNMADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
936 void VFNMADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 915 void VFNMADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
937 void VFNMADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 916 void VFNMADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
938 void VFNMADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 917 void VFNMADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
939 void VFNMADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 918 void VFNMADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
940 void VFNMADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 919 void VFNMADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
941 void VFNMADD132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 920 void VFNMADD132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
942 void VFNMADD213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 921 void VFNMADD213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
943 void VFNMADD231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 922 void VFNMADD231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
944 void VFNMADD132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 923 void VFNMADD132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
945 void VFNMADD213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 924 void VFNMADD213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
946 void VFNMADD231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 925 void VFNMADD231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
947 void VFNMSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 926 void VFNMSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
948 void VFNMSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 927 void VFNMSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
949 void VFNMSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 928 void VFNMSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
950 void VFNMSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 929 void VFNMSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
951 void VFNMSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 930 void VFNMSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
952 void VFNMSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 931 void VFNMSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
953 void VFNMSUB132SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 932 void VFNMSUB132SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
954 void VFNMSUB213SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 933 void VFNMSUB213SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
955 void VFNMSUB231SS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 934 void VFNMSUB231SS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
956 void VFNMSUB132SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 935 void VFNMSUB132SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
957 void VFNMSUB213SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 936 void VFNMSUB213SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
958 void VFNMSUB231SD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 937 void VFNMSUB231SD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
959 void VFMADDSUB132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 938 void VFMADDSUB132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
960 void VFMADDSUB213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 939 void VFMADDSUB213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
961 void VFMADDSUB231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 940 void VFMADDSUB231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
962 void VFMADDSUB132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 941 void VFMADDSUB132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
963 void VFMADDSUB213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 942 void VFMADDSUB213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
964 void VFMADDSUB231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 943 void VFMADDSUB231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
965 void VFMSUBADD132PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 944 void VFMSUBADD132PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
966 void VFMSUBADD213PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 945 void VFMSUBADD213PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
967 void VFMSUBADD231PS(X64Reg regOp1, X64Reg regOp2, OpArg arg); 946 void VFMSUBADD231PS(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
968 void VFMSUBADD132PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 947 void VFMSUBADD132PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
969 void VFMSUBADD213PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 948 void VFMSUBADD213PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
970 void VFMSUBADD231PD(X64Reg regOp1, X64Reg regOp2, OpArg arg); 949 void VFMSUBADD231PD(X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
971 950
972 // VEX GPR instructions 951 // VEX GPR instructions
973 void SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2); 952 void SARX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2);
974 void SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2); 953 void SHLX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2);
975 void SHRX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2); 954 void SHRX(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2);
976 void RORX(int bits, X64Reg regOp, OpArg arg, u8 rotate); 955 void RORX(int bits, X64Reg regOp, const OpArg& arg, u8 rotate);
977 void PEXT(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg); 956 void PEXT(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
978 void PDEP(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg); 957 void PDEP(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
979 void MULX(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg); 958 void MULX(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
980 void BZHI(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2); 959 void BZHI(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2);
981 void BLSR(int bits, X64Reg regOp, OpArg arg); 960 void BLSR(int bits, X64Reg regOp, const OpArg& arg);
982 void BLSMSK(int bits, X64Reg regOp, OpArg arg); 961 void BLSMSK(int bits, X64Reg regOp, const OpArg& arg);
983 void BLSI(int bits, X64Reg regOp, OpArg arg); 962 void BLSI(int bits, X64Reg regOp, const OpArg& arg);
984 void BEXTR(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2); 963 void BEXTR(int bits, X64Reg regOp1, const OpArg& arg, X64Reg regOp2);
985 void ANDN(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg); 964 void ANDN(int bits, X64Reg regOp1, X64Reg regOp2, const OpArg& arg);
986 965
987 void RDTSC(); 966 void RDTSC();
988 967
989 // Utility functions 968 // Utility functions
990 // The difference between this and CALL is that this aligns the stack 969 // The difference between this and CALL is that this aligns the stack
991 // where appropriate. 970 // where appropriate.
992 void ABI_CallFunction(const void *func); 971 void ABI_CallFunction(const void* func);
993 template <typename T> 972 template <typename T>
994 void ABI_CallFunction(T (*func)()) { 973 void ABI_CallFunction(T (*func)()) {
995 ABI_CallFunction((const void *)func); 974 ABI_CallFunction((const void*)func);
996 } 975 }
997 976
998 void ABI_CallFunction(const u8 *func) { 977 void ABI_CallFunction(const u8* func) {
999 ABI_CallFunction((const void *)func); 978 ABI_CallFunction((const void*)func);
1000 } 979 }
1001 void ABI_CallFunctionC16(const void *func, u16 param1); 980 void ABI_CallFunctionC16(const void* func, u16 param1);
1002 void ABI_CallFunctionCC16(const void *func, u32 param1, u16 param2); 981 void ABI_CallFunctionCC16(const void* func, u32 param1, u16 param2);
1003 982
1004 983
1005 // These only support u32 parameters, but that's enough for a lot of uses. 984 // These only support u32 parameters, but that's enough for a lot of uses.
1006 // These will destroy the 1 or 2 first "parameter regs". 985 // These will destroy the 1 or 2 first "parameter regs".
1007 void ABI_CallFunctionC(const void *func, u32 param1); 986 void ABI_CallFunctionC(const void* func, u32 param1);
1008 void ABI_CallFunctionCC(const void *func, u32 param1, u32 param2); 987 void ABI_CallFunctionCC(const void* func, u32 param1, u32 param2);
1009 void ABI_CallFunctionCCC(const void *func, u32 param1, u32 param2, u32 param3); 988 void ABI_CallFunctionCCC(const void* func, u32 param1, u32 param2, u32 param3);
1010 void ABI_CallFunctionCCP(const void *func, u32 param1, u32 param2, void *param3); 989 void ABI_CallFunctionCCP(const void* func, u32 param1, u32 param2, void* param3);
1011 void ABI_CallFunctionCCCP(const void *func, u32 param1, u32 param2, u32 param3, void *param4); 990 void ABI_CallFunctionCCCP(const void* func, u32 param1, u32 param2, u32 param3, void* param4);
1012 void ABI_CallFunctionP(const void *func, void *param1); 991 void ABI_CallFunctionP(const void* func, void* param1);
1013 void ABI_CallFunctionPA(const void *func, void *param1, const Gen::OpArg &arg2); 992 void ABI_CallFunctionPA(const void* func, void* param1, const OpArg& arg2);
1014 void ABI_CallFunctionPAA(const void *func, void *param1, const Gen::OpArg &arg2, const Gen::OpArg &arg3); 993 void ABI_CallFunctionPAA(const void* func, void* param1, const OpArg& arg2, const OpArg& arg3);
1015 void ABI_CallFunctionPPC(const void *func, void *param1, void *param2, u32 param3); 994 void ABI_CallFunctionPPC(const void* func, void* param1, void* param2, u32 param3);
1016 void ABI_CallFunctionAC(const void *func, const Gen::OpArg &arg1, u32 param2); 995 void ABI_CallFunctionAC(const void* func, const OpArg& arg1, u32 param2);
1017 void ABI_CallFunctionACC(const void *func, const Gen::OpArg &arg1, u32 param2, u32 param3); 996 void ABI_CallFunctionACC(const void* func, const OpArg& arg1, u32 param2, u32 param3);
1018 void ABI_CallFunctionA(const void *func, const Gen::OpArg &arg1); 997 void ABI_CallFunctionA(const void* func, const OpArg& arg1);
1019 void ABI_CallFunctionAA(const void *func, const Gen::OpArg &arg1, const Gen::OpArg &arg2); 998 void ABI_CallFunctionAA(const void* func, const OpArg& arg1, const OpArg& arg2);
1020 999
1021 // Pass a register as a parameter. 1000 // Pass a register as a parameter.
1022 void ABI_CallFunctionR(const void *func, X64Reg reg1); 1001 void ABI_CallFunctionR(const void* func, X64Reg reg1);
1023 void ABI_CallFunctionRR(const void *func, X64Reg reg1, X64Reg reg2); 1002 void ABI_CallFunctionRR(const void* func, X64Reg reg1, X64Reg reg2);
1024 1003
1025 template <typename Tr, typename T1> 1004 template <typename Tr, typename T1>
1026 void ABI_CallFunctionC(Tr (*func)(T1), u32 param1) { 1005 void ABI_CallFunctionC(Tr (*func)(T1), u32 param1) {
1027 ABI_CallFunctionC((const void *)func, param1); 1006 ABI_CallFunctionC((const void*)func, param1);
1028 } 1007 }
1029 1008
1030 // A function that doesn't have any control over what it will do to regs, 1009 // A function that doesn't have any control over what it will do to regs,
@@ -1048,9 +1027,9 @@ public:
1048 void ABI_EmitEpilogue(int maxCallParams); 1027 void ABI_EmitEpilogue(int maxCallParams);
1049 1028
1050 #ifdef _M_IX86 1029 #ifdef _M_IX86
1051 inline int ABI_GetNumXMMRegs() { return 8; } 1030 static int ABI_GetNumXMMRegs() { return 8; }
1052 #else 1031 #else
1053 inline int ABI_GetNumXMMRegs() { return 16; } 1032 static int ABI_GetNumXMMRegs() { return 16; }
1054 #endif 1033 #endif
1055}; // class XEmitter 1034}; // class XEmitter
1056 1035
HIC SVNT DRACONES