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authorGravatar archshift2014-09-02 22:40:02 -0700
committerGravatar archshift2014-09-02 22:40:02 -0700
commit4795a64fc8ff59fced28735e627deb7c3b4575ed (patch)
treeb8f6161609efdd649769624b649445923d24935c /src/common/atomic_win32.h
parentMerge pull request #69 from yuriks/cmake-cleanup (diff)
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Removed common/atomic, instead using std::atomic
Diffstat (limited to 'src/common/atomic_win32.h')
-rw-r--r--src/common/atomic_win32.h69
1 files changed, 0 insertions, 69 deletions
diff --git a/src/common/atomic_win32.h b/src/common/atomic_win32.h
deleted file mode 100644
index 0808905f0..000000000
--- a/src/common/atomic_win32.h
+++ /dev/null
@@ -1,69 +0,0 @@
1// Copyright 2013 Dolphin Emulator Project
2// Licensed under GPLv2
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include "common/common.h"
8#include <intrin.h>
9#include <Windows.h>
10
11// Atomic operations are performed in a single step by the CPU. It is
12// impossible for other threads to see the operation "half-done."
13//
14// Some atomic operations can be combined with different types of memory
15// barriers called "Acquire semantics" and "Release semantics", defined below.
16//
17// Acquire semantics: Future memory accesses cannot be relocated to before the
18// operation.
19//
20// Release semantics: Past memory accesses cannot be relocated to after the
21// operation.
22//
23// These barriers affect not only the compiler, but also the CPU.
24//
25// NOTE: Acquire and Release are not differentiated right now. They perform a
26// full memory barrier instead of a "one-way" memory barrier. The newest
27// Windows SDK has Acquire and Release versions of some Interlocked* functions.
28
29namespace Common
30{
31
32inline void AtomicAdd(volatile u32& target, u32 value) {
33 InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
34}
35
36inline void AtomicAnd(volatile u32& target, u32 value) {
37 _InterlockedAnd((volatile LONG*)&target, (LONG)value);
38}
39
40inline void AtomicIncrement(volatile u32& target) {
41 InterlockedIncrement((volatile LONG*)&target);
42}
43
44inline void AtomicDecrement(volatile u32& target) {
45 InterlockedDecrement((volatile LONG*)&target);
46}
47
48inline u32 AtomicLoad(volatile u32& src) {
49 return src; // 32-bit reads are always atomic.
50}
51inline u32 AtomicLoadAcquire(volatile u32& src) {
52 u32 result = src; // 32-bit reads are always atomic.
53 _ReadBarrier(); // Compiler instruction only. x86 loads always have acquire semantics.
54 return result;
55}
56
57inline void AtomicOr(volatile u32& target, u32 value) {
58 _InterlockedOr((volatile LONG*)&target, (LONG)value);
59}
60
61inline void AtomicStore(volatile u32& dest, u32 value) {
62 dest = value; // 32-bit writes are always atomic.
63}
64inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
65 _WriteBarrier(); // Compiler instruction only. x86 stores always have release semantics.
66 dest = value; // 32-bit writes are always atomic.
67}
68
69}