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authorGravatar Subv2018-01-10 00:58:25 -0500
committerGravatar Subv2018-01-10 01:01:55 -0500
commit7ad20154fc9bf1094f78721fed13fac1436bef17 (patch)
tree7c49bbaee40560ffac1a0a5f8a869df23f0dba71 /src/citra_qt/debugger/wait_tree.cpp
parentServices: Allow lm to log single-character messages. (diff)
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Threads: Added enum values for the Switch's 4 cpu cores and implemented svcGetInfo(AllowedCpuIdBitmask)
Diffstat (limited to 'src/citra_qt/debugger/wait_tree.cpp')
-rw-r--r--src/citra_qt/debugger/wait_tree.cpp9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/citra_qt/debugger/wait_tree.cpp b/src/citra_qt/debugger/wait_tree.cpp
index cd03a6554..c066a3e17 100644
--- a/src/citra_qt/debugger/wait_tree.cpp
+++ b/src/citra_qt/debugger/wait_tree.cpp
@@ -205,14 +205,11 @@ std::vector<std::unique_ptr<WaitTreeItem>> WaitTreeThread::GetChildren() const {
205 case ThreadProcessorId::THREADPROCESSORID_DEFAULT: 205 case ThreadProcessorId::THREADPROCESSORID_DEFAULT:
206 processor = tr("default"); 206 processor = tr("default");
207 break; 207 break;
208 case ThreadProcessorId::THREADPROCESSORID_ALL:
209 processor = tr("all");
210 break;
211 case ThreadProcessorId::THREADPROCESSORID_0: 208 case ThreadProcessorId::THREADPROCESSORID_0:
212 processor = tr("AppCore");
213 break;
214 case ThreadProcessorId::THREADPROCESSORID_1: 209 case ThreadProcessorId::THREADPROCESSORID_1:
215 processor = tr("SysCore"); 210 case ThreadProcessorId::THREADPROCESSORID_2:
211 case ThreadProcessorId::THREADPROCESSORID_3:
212 processor = tr("core %1").arg(thread.processor_id);
216 break; 213 break;
217 default: 214 default:
218 processor = tr("Unknown processor %1").arg(thread.processor_id); 215 processor = tr("Unknown processor %1").arg(thread.processor_id);