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| author | 2018-03-16 22:06:24 -0500 | |
|---|---|---|
| committer | 2018-03-16 22:51:06 -0500 | |
| commit | f93d769a1ca127eadfa2edeab03465aeb7552e8d (patch) | |
| tree | 5bf6547fadfc303c49cdab20dfd0613917a6403d | |
| parent | Merge pull request #241 from Subv/gpu_method_call (diff) | |
| download | yuzu-f93d769a1ca127eadfa2edeab03465aeb7552e8d.tar.gz yuzu-f93d769a1ca127eadfa2edeab03465aeb7552e8d.tar.xz yuzu-f93d769a1ca127eadfa2edeab03465aeb7552e8d.zip | |
GPU: Handle the SetShader method call (0xE24) and store the shader config.
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 24 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 18 |
2 files changed, 38 insertions, 4 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 1b963e87e..603a2edaf 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp | |||
| @@ -9,7 +9,7 @@ namespace Tegra { | |||
| 9 | namespace Engines { | 9 | namespace Engines { |
| 10 | 10 | ||
| 11 | const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = { | 11 | const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers = { |
| 12 | {0xE24, {"PrepareShader", 5, &Maxwell3D::PrepareShader}}, | 12 | {0xE24, {"SetShader", 5, &Maxwell3D::SetShader}}, |
| 13 | }; | 13 | }; |
| 14 | 14 | ||
| 15 | Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {} | 15 | Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {} |
| @@ -79,7 +79,27 @@ void Maxwell3D::DrawArrays() { | |||
| 79 | LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring"); | 79 | LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring"); |
| 80 | } | 80 | } |
| 81 | 81 | ||
| 82 | void Maxwell3D::PrepareShader(const std::vector<u32>& parameters) {} | 82 | void Maxwell3D::SetShader(const std::vector<u32>& parameters) { |
| 83 | /** | ||
| 84 | * Parameters description: | ||
| 85 | * [0] = Shader Program. | ||
| 86 | * [1] = Unknown. | ||
| 87 | * [2] = Offset to the start of the shader, after the 0x30 bytes header. | ||
| 88 | * [3] = Shader Type. | ||
| 89 | * [4] = Shader End Address >> 8. | ||
| 90 | */ | ||
| 91 | auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]); | ||
| 92 | // TODO(Subv): This address is probably an offset from the CODE_ADDRESS register. | ||
| 93 | GPUVAddr begin_address = parameters[2]; | ||
| 94 | auto shader_type = static_cast<Regs::ShaderType>(parameters[3]); | ||
| 95 | GPUVAddr end_address = parameters[4] << 8; | ||
| 96 | |||
| 97 | auto& shader = state.shaders[static_cast<size_t>(shader_program)]; | ||
| 98 | shader.program = shader_program; | ||
| 99 | shader.type = shader_type; | ||
| 100 | shader.begin_address = begin_address; | ||
| 101 | shader.end_address = end_address; | ||
| 102 | } | ||
| 83 | 103 | ||
| 84 | } // namespace Engines | 104 | } // namespace Engines |
| 85 | } // namespace Tegra | 105 | } // namespace Tegra |
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 8870ef119..3708b31ee 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | 4 | ||
| 5 | #pragma once | 5 | #pragma once |
| 6 | 6 | ||
| 7 | #include <array> | ||
| 7 | #include <unordered_map> | 8 | #include <unordered_map> |
| 8 | #include <vector> | 9 | #include <vector> |
| 9 | #include "common/bit_field.h" | 10 | #include "common/bit_field.h" |
| @@ -104,7 +105,7 @@ public: | |||
| 104 | u32 gpr_alloc; | 105 | u32 gpr_alloc; |
| 105 | ShaderType type; | 106 | ShaderType type; |
| 106 | INSERT_PADDING_WORDS(9); | 107 | INSERT_PADDING_WORDS(9); |
| 107 | } shader_config[6]; | 108 | } shader_config[MaxShaderProgram]; |
| 108 | 109 | ||
| 109 | INSERT_PADDING_WORDS(0x5D0); | 110 | INSERT_PADDING_WORDS(0x5D0); |
| 110 | 111 | ||
| @@ -120,6 +121,19 @@ public: | |||
| 120 | 121 | ||
| 121 | static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size"); | 122 | static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size"); |
| 122 | 123 | ||
| 124 | struct State { | ||
| 125 | struct ShaderInfo { | ||
| 126 | Regs::ShaderType type; | ||
| 127 | Regs::ShaderProgram program; | ||
| 128 | GPUVAddr begin_address; | ||
| 129 | GPUVAddr end_address; | ||
| 130 | }; | ||
| 131 | |||
| 132 | std::array<ShaderInfo, Regs::MaxShaderProgram> shaders; | ||
| 133 | }; | ||
| 134 | |||
| 135 | State state; | ||
| 136 | |||
| 123 | private: | 137 | private: |
| 124 | MemoryManager& memory_manager; | 138 | MemoryManager& memory_manager; |
| 125 | 139 | ||
| @@ -130,7 +144,7 @@ private: | |||
| 130 | void DrawArrays(); | 144 | void DrawArrays(); |
| 131 | 145 | ||
| 132 | /// Method call handlers | 146 | /// Method call handlers |
| 133 | void PrepareShader(const std::vector<u32>& parameters); | 147 | void SetShader(const std::vector<u32>& parameters); |
| 134 | 148 | ||
| 135 | struct MethodInfo { | 149 | struct MethodInfo { |
| 136 | const char* name; | 150 | const char* name; |