diff options
| author | 2019-04-08 12:07:56 -0400 | |
|---|---|---|
| committer | 2019-04-08 12:07:56 -0400 | |
| commit | ef8be408d321f4f15f0731c46118834bb757be1a (patch) | |
| tree | 75c3e7efd01bb84086b905d8b033b9c82a1371da | |
| parent | Move ConstBufferAccessor to Maxwell3d, correct mistakes and clang format. (diff) | |
| download | yuzu-ef8be408d321f4f15f0731c46118834bb757be1a.tar.gz yuzu-ef8be408d321f4f15f0731c46118834bb757be1a.tar.xz yuzu-ef8be408d321f4f15f0731c46118834bb757be1a.zip | |
Adapt Bindless to work with AOFFI
| -rw-r--r-- | src/video_core/shader/decode/texture.cpp | 25 |
1 files changed, 18 insertions, 7 deletions
diff --git a/src/video_core/shader/decode/texture.cpp b/src/video_core/shader/decode/texture.cpp index dd5310c36..fa65ac9a9 100644 --- a/src/video_core/shader/decode/texture.cpp +++ b/src/video_core/shader/decode/texture.cpp | |||
| @@ -67,11 +67,12 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 67 | 67 | ||
| 68 | const TextureType texture_type{instr.tex_b.texture_type}; | 68 | const TextureType texture_type{instr.tex_b.texture_type}; |
| 69 | const bool is_array = instr.tex_b.array != 0; | 69 | const bool is_array = instr.tex_b.array != 0; |
| 70 | const bool is_aoffi = instr.tex.UsesMiscMode(TextureMiscMode::AOFFI); | ||
| 70 | const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC); | 71 | const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC); |
| 71 | const auto process_mode = instr.tex_b.GetTextureProcessMode(); | 72 | const auto process_mode = instr.tex_b.GetTextureProcessMode(); |
| 72 | WriteTexInstructionFloat( | 73 | WriteTexInstructionFloat(bb, instr, |
| 73 | bb, instr, | 74 | GetTexCode(instr, texture_type, process_mode, depth_compare, |
| 74 | GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, {instr.gpr20})); | 75 | is_array, is_aoffi, {instr.gpr20})); |
| 75 | break; | 76 | break; |
| 76 | } | 77 | } |
| 77 | case OpCode::Id::TEXS: { | 78 | case OpCode::Id::TEXS: { |
| @@ -384,7 +385,9 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr, | |||
| 384 | 385 | ||
| 385 | Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, | 386 | Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, |
| 386 | TextureProcessMode process_mode, std::vector<Node> coords, | 387 | TextureProcessMode process_mode, std::vector<Node> coords, |
| 387 | Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, std::optional<Tegra::Shader::Register> bindless_reg) { | 388 | Node array, Node depth_compare, u32 bias_offset, |
| 389 | std::vector<Node> aoffi, | ||
| 390 | std::optional<Tegra::Shader::Register> bindless_reg) { | ||
| 388 | const bool is_array = array; | 391 | const bool is_array = array; |
| 389 | const bool is_shadow = depth_compare; | 392 | const bool is_shadow = depth_compare; |
| 390 | const bool is_bindless = bindless_reg.has_value(); | 393 | const bool is_bindless = bindless_reg.has_value(); |
| @@ -451,7 +454,14 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, | |||
| 451 | const bool lod_bias_enabled{ | 454 | const bool lod_bias_enabled{ |
| 452 | (process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)}; | 455 | (process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)}; |
| 453 | 456 | ||
| 457 | const bool is_bindless = bindless_reg.has_value(); | ||
| 458 | |||
| 454 | u64 parameter_register = instr.gpr20.Value(); | 459 | u64 parameter_register = instr.gpr20.Value(); |
| 460 | if (is_bindless) { | ||
| 461 | ++parameter_register; | ||
| 462 | } | ||
| 463 | |||
| 464 | const u32 bias_lod_offset = (is_bindless ? 1 : 0); | ||
| 455 | if (lod_bias_enabled) { | 465 | if (lod_bias_enabled) { |
| 456 | ++parameter_register; | 466 | ++parameter_register; |
| 457 | } | 467 | } |
| @@ -478,7 +488,6 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, | |||
| 478 | if (is_aoffi) { | 488 | if (is_aoffi) { |
| 479 | aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, false); | 489 | aoffi = GetAoffiCoordinates(GetRegister(parameter_register++), coord_count, false); |
| 480 | } | 490 | } |
| 481 | const u32 bindless_offset = (is_bindless ? 1 : 0); | ||
| 482 | 491 | ||
| 483 | Node dc{}; | 492 | Node dc{}; |
| 484 | if (depth_compare) { | 493 | if (depth_compare) { |
| @@ -487,7 +496,8 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, | |||
| 487 | dc = GetRegister(parameter_register++); | 496 | dc = GetRegister(parameter_register++); |
| 488 | } | 497 | } |
| 489 | 498 | ||
| 490 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi, bindless_reg); | 499 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_lod_offset, |
| 500 | aoffi, bindless_reg); | ||
| 491 | } | 501 | } |
| 492 | 502 | ||
| 493 | Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type, | 503 | Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type, |
| @@ -523,7 +533,8 @@ Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type, | |||
| 523 | dc = GetRegister(depth_register); | 533 | dc = GetRegister(depth_register); |
| 524 | } | 534 | } |
| 525 | 535 | ||
| 526 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset, {}); | 536 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, bias_offset, {}, |
| 537 | {}); | ||
| 527 | } | 538 | } |
| 528 | 539 | ||
| 529 | Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare, | 540 | Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare, |