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| author | 2018-12-20 23:59:01 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:50 -0300 | |
| commit | ea358bd4bf70b6b93b4022ede7a8bcd111f10f9e (patch) | |
| tree | adac0a6f611770f77d6d8dd147e340b5b7d482ce | |
| parent | shader_decode: Implement FMUL32_IMM (diff) | |
| download | yuzu-ea358bd4bf70b6b93b4022ede7a8bcd111f10f9e.tar.gz yuzu-ea358bd4bf70b6b93b4022ede7a8bcd111f10f9e.tar.xz yuzu-ea358bd4bf70b6b93b4022ede7a8bcd111f10f9e.zip | |
shader_decode: Implement FADD32I
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_immediate.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_immediate.cpp b/src/video_core/shader/decode/arithmetic_immediate.cpp index 0e4cbccab..996b2537a 100644 --- a/src/video_core/shader/decode/arithmetic_immediate.cpp +++ b/src/video_core/shader/decode/arithmetic_immediate.cpp | |||
| @@ -31,6 +31,18 @@ u32 ShaderIR::DecodeArithmeticImmediate(BasicBlock& bb, u32 pc) { | |||
| 31 | SetRegister(bb, instr.gpr0, value); | 31 | SetRegister(bb, instr.gpr0, value); |
| 32 | break; | 32 | break; |
| 33 | } | 33 | } |
| 34 | case OpCode::Id::FADD32I: { | ||
| 35 | UNIMPLEMENTED_IF_MSG(instr.op_32.generates_cc, | ||
| 36 | "Condition codes generation in FADD32I is not implemented"); | ||
| 37 | const Node op_a = GetOperandAbsNegFloat(GetRegister(instr.gpr8), instr.fadd32i.abs_a, | ||
| 38 | instr.fadd32i.negate_a); | ||
| 39 | const Node op_b = GetOperandAbsNegFloat(GetImmediate32(instr), instr.fadd32i.abs_b, | ||
| 40 | instr.fadd32i.negate_b); | ||
| 41 | |||
| 42 | const Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b); | ||
| 43 | SetRegister(bb, instr.gpr0, value); | ||
| 44 | break; | ||
| 45 | } | ||
| 34 | default: | 46 | default: |
| 35 | UNIMPLEMENTED_MSG("Unhandled arithmetic immediate instruction: {}", | 47 | UNIMPLEMENTED_MSG("Unhandled arithmetic immediate instruction: {}", |
| 36 | opcode->get().GetName()); | 48 | opcode->get().GetName()); |