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| author | 2020-01-27 01:14:25 -0300 | |
|---|---|---|
| committer | 2020-01-27 01:15:44 -0300 | |
| commit | e3fc3459c817398fdc9a878c2e554e4580b1d863 (patch) | |
| tree | 60f589d1c76bb589b9d171ae6e4ac2395288ed36 | |
| parent | Merge pull request #3343 from FearlessTobi/ui-tab (diff) | |
| download | yuzu-e3fc3459c817398fdc9a878c2e554e4580b1d863.tar.gz yuzu-e3fc3459c817398fdc9a878c2e554e4580b1d863.tar.xz yuzu-e3fc3459c817398fdc9a878c2e554e4580b1d863.zip | |
shader/arithmetic: Implement FCMP
Compares the third operand with zero, then selects between the first and
second.
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 7 | ||||
| -rw-r--r-- | src/video_core/shader/decode/arithmetic.cpp | 11 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 6f98bd827..6376b579b 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -1096,6 +1096,11 @@ union Instruction { | |||
| 1096 | } fset; | 1096 | } fset; |
| 1097 | 1097 | ||
| 1098 | union { | 1098 | union { |
| 1099 | BitField<47, 1, u64> ftz; | ||
| 1100 | BitField<48, 4, PredCondition> cond; | ||
| 1101 | } fcmp; | ||
| 1102 | |||
| 1103 | union { | ||
| 1099 | BitField<49, 1, u64> bf; | 1104 | BitField<49, 1, u64> bf; |
| 1100 | BitField<35, 3, PredCondition> cond; | 1105 | BitField<35, 3, PredCondition> cond; |
| 1101 | BitField<50, 1, u64> ftz; | 1106 | BitField<50, 1, u64> ftz; |
| @@ -1771,6 +1776,7 @@ public: | |||
| 1771 | ICMP_R, | 1776 | ICMP_R, |
| 1772 | ICMP_CR, | 1777 | ICMP_CR, |
| 1773 | ICMP_IMM, | 1778 | ICMP_IMM, |
| 1779 | FCMP_R, | ||
| 1774 | MUFU, // Multi-Function Operator | 1780 | MUFU, // Multi-Function Operator |
| 1775 | RRO_C, // Range Reduction Operator | 1781 | RRO_C, // Range Reduction Operator |
| 1776 | RRO_R, | 1782 | RRO_R, |
| @@ -2074,6 +2080,7 @@ private: | |||
| 2074 | INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"), | 2080 | INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"), |
| 2075 | INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"), | 2081 | INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"), |
| 2076 | INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), | 2082 | INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"), |
| 2083 | INST("010110111010----", Id::FCMP_R, Type::Arithmetic, "FCMP_R"), | ||
| 2077 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), | 2084 | INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), |
| 2078 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), | 2085 | INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), |
| 2079 | INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), | 2086 | INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), |
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp index fcedd2af6..90240c765 100644 --- a/src/video_core/shader/decode/arithmetic.cpp +++ b/src/video_core/shader/decode/arithmetic.cpp | |||
| @@ -21,7 +21,7 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { | |||
| 21 | 21 | ||
| 22 | Node op_a = GetRegister(instr.gpr8); | 22 | Node op_a = GetRegister(instr.gpr8); |
| 23 | 23 | ||
| 24 | Node op_b = [&]() -> Node { | 24 | Node op_b = [&] { |
| 25 | if (instr.is_b_imm) { | 25 | if (instr.is_b_imm) { |
| 26 | return GetImmediate19(instr); | 26 | return GetImmediate19(instr); |
| 27 | } else if (instr.is_b_gpr) { | 27 | } else if (instr.is_b_gpr) { |
| @@ -141,6 +141,15 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { | |||
| 141 | SetRegister(bb, instr.gpr0, value); | 141 | SetRegister(bb, instr.gpr0, value); |
| 142 | break; | 142 | break; |
| 143 | } | 143 | } |
| 144 | case OpCode::Id::FCMP_R: { | ||
| 145 | UNIMPLEMENTED_IF(instr.fcmp.ftz == 0); | ||
| 146 | Node op_c = GetRegister(instr.gpr39); | ||
| 147 | Node comp = GetPredicateComparisonFloat(instr.fcmp.cond, std::move(op_c), Immediate(0.0f)); | ||
| 148 | SetRegister( | ||
| 149 | bb, instr.gpr0, | ||
| 150 | Operation(OperationCode::Select, std::move(comp), std::move(op_a), std::move(op_b))); | ||
| 151 | break; | ||
| 152 | } | ||
| 144 | case OpCode::Id::RRO_C: | 153 | case OpCode::Id::RRO_C: |
| 145 | case OpCode::Id::RRO_R: | 154 | case OpCode::Id::RRO_R: |
| 146 | case OpCode::Id::RRO_IMM: { | 155 | case OpCode::Id::RRO_IMM: { |