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authorGravatar Subv2018-07-02 11:21:23 -0500
committerGravatar Subv2018-07-02 11:21:23 -0500
commitcc73bad293cadb2323a821fa32bcd03c9d359e3e (patch)
treef5bf0dc3522f7f6fb688ac85e68409731769d0f2
parentMerge pull request #602 from Subv/mufu_subop (diff)
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GPU: Added register definitions for the vertex buffer base element.
-rw-r--r--src/video_core/engines/maxwell_3d.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 180be4ff4..58db81222 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -455,7 +455,11 @@ public:
455 u32 enable[NumRenderTargets]; 455 u32 enable[NumRenderTargets];
456 } blend; 456 } blend;
457 457
458 INSERT_PADDING_WORDS(0x77); 458 INSERT_PADDING_WORDS(0x2D);
459
460 u32 vb_element_base;
461
462 INSERT_PADDING_WORDS(0x49);
459 463
460 struct { 464 struct {
461 u32 tsc_address_high; 465 u32 tsc_address_high;
@@ -745,6 +749,7 @@ ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
745ASSERT_REG_POSITION(rt_control, 0x487); 749ASSERT_REG_POSITION(rt_control, 0x487);
746ASSERT_REG_POSITION(independent_blend_enable, 0x4B9); 750ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
747ASSERT_REG_POSITION(blend, 0x4CF); 751ASSERT_REG_POSITION(blend, 0x4CF);
752ASSERT_REG_POSITION(vb_element_base, 0x50D);
748ASSERT_REG_POSITION(tsc, 0x557); 753ASSERT_REG_POSITION(tsc, 0x557);
749ASSERT_REG_POSITION(tic, 0x55D); 754ASSERT_REG_POSITION(tic, 0x55D);
750ASSERT_REG_POSITION(code_address, 0x582); 755ASSERT_REG_POSITION(code_address, 0x582);