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authorGravatar jam1garner2021-11-21 21:18:56 -0500
committerGravatar jam1garner2021-11-21 21:18:56 -0500
commitc8a67a725de6481c891d5bfe1b83fcb6340c88a3 (patch)
tree9211464997cc2f241a56fd88b810f8bd599c9a73
parentarm: dynarmic: Implement icache op handling for 'ic ivau' instruction (diff)
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arm: dynarmic: Implement icache op handling for 'ic iallu' instruction
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 587fffb34..8fe83413c 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -98,6 +98,9 @@ public:
98 return; 98 return;
99 99
100 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: 100 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
101 parent.ClearInstructionCache();
102 return;
103
101 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: 104 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
102 default: 105 default:
103 LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation"); 106 LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");