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authorGravatar Lioncash2018-10-20 15:58:06 -0400
committerGravatar Lioncash2018-10-20 15:58:09 -0400
commitc1e5525fc622e5bf5c40acceba4a07529051fab3 (patch)
treed77362f0fceace3a09776b7d828c1c4ca56fd58b
parentmaxwell_dma: Make variables const where applicable within HandleCopy() (diff)
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engines/maxwell_*: Use nested namespace specifiers where applicable
These three source files are the only ones within the engines directory that don't use nested namespaces. We may as well change these over to keep things consistent.
-rw-r--r--src/video_core/engines/maxwell_3d.cpp6
-rw-r--r--src/video_core/engines/maxwell_compute.cpp6
-rw-r--r--src/video_core/engines/maxwell_dma.cpp6
3 files changed, 6 insertions, 12 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 8afd26fe9..bca014a4a 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -13,8 +13,7 @@
13#include "video_core/renderer_base.h" 13#include "video_core/renderer_base.h"
14#include "video_core/textures/texture.h" 14#include "video_core/textures/texture.h"
15 15
16namespace Tegra { 16namespace Tegra::Engines {
17namespace Engines {
18 17
19/// First register id that is actually a Macro call. 18/// First register id that is actually a Macro call.
20constexpr u32 MacroRegistersStart = 0xE00; 19constexpr u32 MacroRegistersStart = 0xE00;
@@ -408,5 +407,4 @@ void Maxwell3D::ProcessClearBuffers() {
408 rasterizer.Clear(); 407 rasterizer.Clear();
409} 408}
410 409
411} // namespace Engines 410} // namespace Tegra::Engines
412} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index 59e28b22d..8b5f08351 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -6,8 +6,7 @@
6#include "core/core.h" 6#include "core/core.h"
7#include "video_core/engines/maxwell_compute.h" 7#include "video_core/engines/maxwell_compute.h"
8 8
9namespace Tegra { 9namespace Tegra::Engines {
10namespace Engines {
11 10
12void MaxwellCompute::WriteReg(u32 method, u32 value) { 11void MaxwellCompute::WriteReg(u32 method, u32 value) {
13 ASSERT_MSG(method < Regs::NUM_REGS, 12 ASSERT_MSG(method < Regs::NUM_REGS,
@@ -26,5 +25,4 @@ void MaxwellCompute::WriteReg(u32 method, u32 value) {
26 } 25 }
27} 26}
28 27
29} // namespace Engines 28} // namespace Tegra::Engines
30} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp
index 9469bce59..b8a78cf82 100644
--- a/src/video_core/engines/maxwell_dma.cpp
+++ b/src/video_core/engines/maxwell_dma.cpp
@@ -7,8 +7,7 @@
7#include "video_core/rasterizer_interface.h" 7#include "video_core/rasterizer_interface.h"
8#include "video_core/textures/decoders.h" 8#include "video_core/textures/decoders.h"
9 9
10namespace Tegra { 10namespace Tegra::Engines {
11namespace Engines {
12 11
13MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager) 12MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
14 : memory_manager(memory_manager), rasterizer{rasterizer} {} 13 : memory_manager(memory_manager), rasterizer{rasterizer} {}
@@ -119,5 +118,4 @@ void MaxwellDMA::HandleCopy() {
119 } 118 }
120} 119}
121 120
122} // namespace Engines 121} // namespace Tegra::Engines
123} // namespace Tegra