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authorGravatar bunnei2018-06-08 23:25:22 -0400
committerGravatar bunnei2018-06-08 23:25:22 -0400
commitbbc4f369edeab6c21a13fce6146b443445a62c48 (patch)
treeac8613849062fe64ed2e8ddd02dbedf5e381ecaa
parentgl_shader_decompiler: Add missing asserts for saturate_a instructions. (diff)
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gl_shader_decompiler: Implement IADD instruction.
-rw-r--r--src/video_core/engines/shader_bytecode.h16
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp32
2 files changed, 37 insertions, 11 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index bf254ef33..dc3dd8a80 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -264,7 +264,7 @@ union Instruction {
264 BitField<39, 5, u64> shift_amount; 264 BitField<39, 5, u64> shift_amount;
265 BitField<48, 1, u64> negate_b; 265 BitField<48, 1, u64> negate_b;
266 BitField<49, 1, u64> negate_a; 266 BitField<49, 1, u64> negate_a;
267 } iscadd; 267 } alu_integer;
268 268
269 union { 269 union {
270 BitField<20, 8, u64> shift_position; 270 BitField<20, 8, u64> shift_position;
@@ -434,6 +434,9 @@ public:
434 FMUL_R, 434 FMUL_R,
435 FMUL_IMM, 435 FMUL_IMM,
436 FMUL32_IMM, 436 FMUL32_IMM,
437 IADD_C,
438 IADD_R,
439 IADD_IMM,
437 ISCADD_C, // Scale and Add 440 ISCADD_C, // Scale and Add
438 ISCADD_R, 441 ISCADD_R,
439 ISCADD_IMM, 442 ISCADD_IMM,
@@ -489,10 +492,10 @@ public:
489 enum class Type { 492 enum class Type {
490 Trivial, 493 Trivial,
491 Arithmetic, 494 Arithmetic,
495 ArithmeticInteger,
492 Bfe, 496 Bfe,
493 Logic, 497 Logic,
494 Shift, 498 Shift,
495 ScaledAdd,
496 Ffma, 499 Ffma,
497 Flow, 500 Flow,
498 Memory, 501 Memory,
@@ -617,9 +620,12 @@ private:
617 INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"), 620 INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
618 INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"), 621 INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
619 INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"), 622 INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
620 INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"), 623 INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"),
621 INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"), 624 INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"),
622 INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"), 625 INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"),
626 INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
627 INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
628 INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),
623 INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), 629 INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
624 INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), 630 INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
625 INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), 631 INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 3abdd7fdb..4e248d328 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -992,13 +992,13 @@ private:
992 break; 992 break;
993 } 993 }
994 994
995 case OpCode::Type::ScaledAdd: { 995 case OpCode::Type::ArithmeticInteger: {
996 std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); 996 std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
997 997
998 if (instr.iscadd.negate_a) 998 if (instr.alu_integer.negate_a)
999 op_a = '-' + op_a; 999 op_a = '-' + op_a;
1000 1000
1001 std::string op_b = instr.iscadd.negate_b ? "-" : ""; 1001 std::string op_b = instr.alu_integer.negate_b ? "-" : "";
1002 1002
1003 if (instr.is_b_imm) { 1003 if (instr.is_b_imm) {
1004 op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')'; 1004 op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
@@ -1011,10 +1011,30 @@ private:
1011 } 1011 }
1012 } 1012 }
1013 1013
1014 std::string shift = std::to_string(instr.iscadd.shift_amount.Value()); 1014 switch (opcode->GetId()) {
1015 case OpCode::Id::IADD_C:
1016 case OpCode::Id::IADD_R:
1017 case OpCode::Id::IADD_IMM: {
1018 ASSERT_MSG(!instr.saturate_a, "Unimplemented");
1019 regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1);
1020 break;
1021 }
1022 case OpCode::Id::ISCADD_C:
1023 case OpCode::Id::ISCADD_R:
1024 case OpCode::Id::ISCADD_IMM: {
1025 std::string shift = std::to_string(instr.alu_integer.shift_amount.Value());
1026
1027 regs.SetRegisterToInteger(instr.gpr0, true, 0,
1028 "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
1029 break;
1030 }
1031 default: {
1032 NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticInteger instruction: {}",
1033 opcode->GetName());
1034 UNREACHABLE();
1035 }
1036 }
1015 1037
1016 regs.SetRegisterToInteger(instr.gpr0, true, 0,
1017 "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
1018 break; 1038 break;
1019 } 1039 }
1020 case OpCode::Type::Ffma: { 1040 case OpCode::Type::Ffma: {