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| author | 2018-04-09 22:09:23 -0400 | |
|---|---|---|
| committer | 2018-04-14 16:01:40 -0400 | |
| commit | 5a47832221fb03a50af2583ec311114871ea1dd1 (patch) | |
| tree | 117326890470f9a63768334dfb218d3523eaecdb | |
| parent | gl_shader_decompiler: Add shader stage hint. (diff) | |
| download | yuzu-5a47832221fb03a50af2583ec311114871ea1dd1.tar.gz yuzu-5a47832221fb03a50af2583ec311114871ea1dd1.tar.xz yuzu-5a47832221fb03a50af2583ec311114871ea1dd1.zip | |
shader_bytecode: Add SubOp decoding.
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 6660742cc..477d01f94 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -265,6 +265,15 @@ enum class Pred : u64 { | |||
| 265 | NeverExecute = 0xf, | 265 | NeverExecute = 0xf, |
| 266 | }; | 266 | }; |
| 267 | 267 | ||
| 268 | enum class SubOp : u64 { | ||
| 269 | Cos = 0x0, | ||
| 270 | Sin = 0x1, | ||
| 271 | Ex2 = 0x2, | ||
| 272 | Lg2 = 0x3, | ||
| 273 | Rcp = 0x4, | ||
| 274 | Rsq = 0x5, | ||
| 275 | }; | ||
| 276 | |||
| 268 | #pragma pack(1) | 277 | #pragma pack(1) |
| 269 | union Instruction { | 278 | union Instruction { |
| 270 | Instruction& operator=(const Instruction& instr) { | 279 | Instruction& operator=(const Instruction& instr) { |
| @@ -276,6 +285,7 @@ union Instruction { | |||
| 276 | BitField<0, 8, Register> gpr1; | 285 | BitField<0, 8, Register> gpr1; |
| 277 | BitField<8, 8, Register> gpr2; | 286 | BitField<8, 8, Register> gpr2; |
| 278 | BitField<16, 4, Pred> pred; | 287 | BitField<16, 4, Pred> pred; |
| 288 | BitField<20, 7, SubOp> sub_op; | ||
| 279 | BitField<39, 8, Register> gpr3; | 289 | BitField<39, 8, Register> gpr3; |
| 280 | BitField<45, 1, u64> nb; | 290 | BitField<45, 1, u64> nb; |
| 281 | BitField<46, 1, u64> aa; | 291 | BitField<46, 1, u64> aa; |