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authorGravatar Jannik Vogel2016-05-11 13:39:28 +0200
committerGravatar Jannik Vogel2016-06-07 00:06:28 +0200
commit57855a1701474c65b8dd95d0c312d02fae8fe1a6 (patch)
treeb56fa3b4381e767aec2cba572e656e51110cd92e
parentOpenGL: Avoid undefined behaviour for UNIFORM_BLOCK_DATA_SIZE (diff)
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Pica: Add fog state
-rw-r--r--src/video_core/command_processor.cpp14
-rw-r--r--src/video_core/pica.h53
-rw-r--r--src/video_core/pica_state.h16
3 files changed, 69 insertions, 14 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 19e03adf4..689859049 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -423,6 +423,20 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
423 break; 423 break;
424 } 424 }
425 425
426 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[0], 0xe8):
427 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[1], 0xe9):
428 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[2], 0xea):
429 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[3], 0xeb):
430 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[4], 0xec):
431 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[5], 0xed):
432 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[6], 0xee):
433 case PICA_REG_INDEX_WORKAROUND(fog_lut_data[7], 0xef):
434 {
435 g_state.fog.lut[regs.fog_lut_offset % 128].raw = value;
436 regs.fog_lut_offset.Assign(regs.fog_lut_offset + 1);
437 break;
438 }
439
426 default: 440 default:
427 break; 441 break;
428 } 442 }
diff --git a/src/video_core/pica.h b/src/video_core/pica.h
index 544ea037f..09702d46a 100644
--- a/src/video_core/pica.h
+++ b/src/video_core/pica.h
@@ -401,22 +401,47 @@ struct Regs {
401 TevStageConfig tev_stage3; 401 TevStageConfig tev_stage3;
402 INSERT_PADDING_WORDS(0x3); 402 INSERT_PADDING_WORDS(0x3);
403 403
404 enum class FogMode : u32 {
405 None = 0,
406 Fog = 5,
407 Gas = 7,
408 };
409
404 union { 410 union {
405 // Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in 411 BitField<0, 3, FogMode> fog_mode;
406 // these masks are set 412 BitField<16, 1, u32> fog_flip;
407 BitField< 8, 4, u32> update_mask_rgb;
408 BitField<12, 4, u32> update_mask_a;
409 413
410 bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const { 414 union {
411 return (stage_index < 4) && (update_mask_rgb & (1 << stage_index)); 415 // Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
412 } 416 // these masks are set
417 BitField< 8, 4, u32> update_mask_rgb;
418 BitField<12, 4, u32> update_mask_a;
413 419
414 bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const { 420 bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
415 return (stage_index < 4) && (update_mask_a & (1 << stage_index)); 421 return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
416 } 422 }
417 } tev_combiner_buffer_input; 423
424 bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
425 return (stage_index < 4) && (update_mask_a & (1 << stage_index));
426 }
427 } tev_combiner_buffer_input;
428 };
429
430 union {
431 u32 raw;
432 BitField< 0, 8, u32> r;
433 BitField< 8, 8, u32> g;
434 BitField<16, 8, u32> b;
435 } fog_color;
436
437 INSERT_PADDING_WORDS(0x4);
438
439 BitField<0, 16, u32> fog_lut_offset;
440
441 INSERT_PADDING_WORDS(0x1);
442
443 u32 fog_lut_data[8];
418 444
419 INSERT_PADDING_WORDS(0xf);
420 TevStageConfig tev_stage4; 445 TevStageConfig tev_stage4;
421 INSERT_PADDING_WORDS(0x3); 446 INSERT_PADDING_WORDS(0x3);
422 TevStageConfig tev_stage5; 447 TevStageConfig tev_stage5;
@@ -1318,6 +1343,10 @@ ASSERT_REG_POSITION(tev_stage1, 0xc8);
1318ASSERT_REG_POSITION(tev_stage2, 0xd0); 1343ASSERT_REG_POSITION(tev_stage2, 0xd0);
1319ASSERT_REG_POSITION(tev_stage3, 0xd8); 1344ASSERT_REG_POSITION(tev_stage3, 0xd8);
1320ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0); 1345ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
1346ASSERT_REG_POSITION(fog_mode, 0xe0);
1347ASSERT_REG_POSITION(fog_color, 0xe1);
1348ASSERT_REG_POSITION(fog_lut_offset, 0xe6);
1349ASSERT_REG_POSITION(fog_lut_data, 0xe8);
1321ASSERT_REG_POSITION(tev_stage4, 0xf0); 1350ASSERT_REG_POSITION(tev_stage4, 0xf0);
1322ASSERT_REG_POSITION(tev_stage5, 0xf8); 1351ASSERT_REG_POSITION(tev_stage5, 0xf8);
1323ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd); 1352ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
diff --git a/src/video_core/pica_state.h b/src/video_core/pica_state.h
index 495174c25..01f4285a8 100644
--- a/src/video_core/pica_state.h
+++ b/src/video_core/pica_state.h
@@ -33,10 +33,10 @@ struct State {
33 u32 raw; 33 u32 raw;
34 34
35 // LUT value, encoded as 12-bit fixed point, with 12 fraction bits 35 // LUT value, encoded as 12-bit fixed point, with 12 fraction bits
36 BitField< 0, 12, u32> value; 36 BitField< 0, 12, u32> value; // 0.0.12 fixed point
37 37
38 // Used by HW for efficient interpolation, Citra does not use these 38 // Used by HW for efficient interpolation, Citra does not use these
39 BitField<12, 12, u32> difference; 39 BitField<12, 12, s32> difference; // 1.0.11 fixed point
40 40
41 float ToFloat() { 41 float ToFloat() {
42 return static_cast<float>(value) / 4095.f; 42 return static_cast<float>(value) / 4095.f;
@@ -46,6 +46,18 @@ struct State {
46 std::array<std::array<LutEntry, 256>, 24> luts; 46 std::array<std::array<LutEntry, 256>, 24> luts;
47 } lighting; 47 } lighting;
48 48
49 struct {
50 union LutEntry {
51 // Used for raw access
52 u32 raw;
53
54 BitField< 0, 13, s32> difference; // 1.1.11 fixed point
55 BitField<13, 11, u32> value; // 0.0.11 fixed point
56 };
57
58 std::array<LutEntry, 128> lut;
59 } fog;
60
49 /// Current Pica command list 61 /// Current Pica command list
50 struct { 62 struct {
51 const u32* head_ptr; 63 const u32* head_ptr;