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| author | 2018-06-09 00:01:17 -0400 | |
|---|---|---|
| committer | 2018-06-09 00:01:17 -0400 | |
| commit | 5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb (patch) | |
| tree | b491f11a8e2ddb023c66b709c2f19c8b38de2c97 | |
| parent | Merge pull request #505 from janisozaur/ccache-travis (diff) | |
| download | yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.gz yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.tar.xz yuzu-5440b9c634555c174a9eaf7fd6d308c4ab2cb3bb.zip | |
gl_shader_decompiler: Implement SHR instruction.
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 4 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 13 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 32800392b..a9ea550dc 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -260,6 +260,10 @@ union Instruction { | |||
| 260 | } alu; | 260 | } alu; |
| 261 | 261 | ||
| 262 | union { | 262 | union { |
| 263 | BitField<48, 1, u64> is_signed; | ||
| 264 | } shift; | ||
| 265 | |||
| 266 | union { | ||
| 263 | BitField<39, 5, u64> shift_amount; | 267 | BitField<39, 5, u64> shift_amount; |
| 264 | BitField<48, 1, u64> negate_b; | 268 | BitField<48, 1, u64> negate_b; |
| 265 | BitField<49, 1, u64> negate_a; | 269 | BitField<49, 1, u64> negate_a; |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 94c6bc4b2..fde19cb6b 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -973,6 +973,19 @@ private: | |||
| 973 | } | 973 | } |
| 974 | 974 | ||
| 975 | switch (opcode->GetId()) { | 975 | switch (opcode->GetId()) { |
| 976 | case OpCode::Id::SHR_C: | ||
| 977 | case OpCode::Id::SHR_R: | ||
| 978 | case OpCode::Id::SHR_IMM: { | ||
| 979 | if (!instr.shift.is_signed) { | ||
| 980 | // Logical shift right | ||
| 981 | op_a = "uint(" + op_a + ')'; | ||
| 982 | } | ||
| 983 | |||
| 984 | // Cast to int is superfluous for arithmetic shift, it's only for a logical shift | ||
| 985 | regs.SetRegisterToInteger(instr.gpr0, true, 0, "int(" + op_a + " >> " + op_b + ')', | ||
| 986 | 1, 1); | ||
| 987 | break; | ||
| 988 | } | ||
| 976 | case OpCode::Id::SHL_C: | 989 | case OpCode::Id::SHL_C: |
| 977 | case OpCode::Id::SHL_R: | 990 | case OpCode::Id::SHL_R: |
| 978 | case OpCode::Id::SHL_IMM: | 991 | case OpCode::Id::SHL_IMM: |