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authorGravatar Lioncash2014-12-17 09:36:23 -0500
committerGravatar Lioncash2014-12-17 09:36:25 -0500
commit5289a496a75bd7abe4d18bfc586cb1cfac84fc48 (patch)
tree5b9d0b65118f1398375e3f6cffb0e9a57b0bcb5f
parentMerge pull request #289 from lioncash/smops (diff)
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armemu: Fix SADD16
The lo and hi parts of the result were being constructed as a result of hi and lo halfword intermixing from the rm and rn regs. However the lo part of the result should be constructed only from the lo halfwords of rm and rn, and the hi part of the result should only be constructed from the hi halfwords of rm and rn.
-rw-r--r--src/core/arm/interpreter/armemu.cpp17
1 files changed, 9 insertions, 8 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 5752d116f..dbfb9d858 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -5811,14 +5811,15 @@ L_stm_s_takeabort:
5811 state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10); 5811 state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10);
5812 return 1; 5812 return 1;
5813 } else if ((instr & 0xFF0) == 0xf10) { //sadd16 5813 } else if ((instr & 0xFF0) == 0xf10) { //sadd16
5814 u8 tar = BITS(12, 15); 5814 const u8 rd_idx = BITS(12, 15);
5815 u8 src1 = BITS(16, 19); 5815 const u8 rm_idx = BITS(0, 3);
5816 u8 src2 = BITS(0, 3); 5816 const u8 rn_idx = BITS(16, 19);
5817 s16 a1 = (state->Reg[src1] & 0xFFFF); 5817 const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
5818 s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF); 5818 const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
5819 s16 b1 = (state->Reg[src2] & 0xFFFF); 5819 const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF);
5820 s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF); 5820 const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF);
5821 state->Reg[tar] = ((a1 + a2) & 0xFFFF) | (((b1 + b2) & 0xFFFF) << 0x10); 5821
5822 state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16);
5822 return 1; 5823 return 1;
5823 } else if ((instr & 0xFF0) == 0xf50) { //ssax 5824 } else if ((instr & 0xFF0) == 0xf50) { //ssax
5824 u8 tar = BITS(12, 15); 5825 u8 tar = BITS(12, 15);