summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorGravatar bunnei2015-09-07 15:59:24 -0400
committerGravatar bunnei2015-09-07 15:59:24 -0400
commit47221ab1e62d7bca6a0e430401afb1e0b32cdce7 (patch)
treea2427dc7c5ba6c94fd8ac5562c0fa27e13c862df
parentMerge pull request #1052 from yuriks/vertex-disasm (diff)
parentShader JIT: Use SCALE constant from emitter (diff)
downloadyuzu-47221ab1e62d7bca6a0e430401afb1e0b32cdce7.tar.gz
yuzu-47221ab1e62d7bca6a0e430401afb1e0b32cdce7.tar.xz
yuzu-47221ab1e62d7bca6a0e430401afb1e0b32cdce7.zip
Merge pull request #1121 from aroulin/shader-minor-fixes
Shader: Use constants and proper type casts
-rw-r--r--src/video_core/shader/shader.h12
-rw-r--r--src/video_core/shader/shader_jit_x64.cpp26
2 files changed, 22 insertions, 16 deletions
diff --git a/src/video_core/shader/shader.h b/src/video_core/shader/shader.h
index bac51ddd8..1c6fa592c 100644
--- a/src/video_core/shader/shader.h
+++ b/src/video_core/shader/shader.h
@@ -289,13 +289,13 @@ struct UnitState {
289 289
290 DebugData<Debug> debug; 290 DebugData<Debug> debug;
291 291
292 static int InputOffset(const SourceRegister& reg) { 292 static size_t InputOffset(const SourceRegister& reg) {
293 switch (reg.GetRegisterType()) { 293 switch (reg.GetRegisterType()) {
294 case RegisterType::Input: 294 case RegisterType::Input:
295 return (int)offsetof(UnitState::Registers, input) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 295 return offsetof(UnitState::Registers, input) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
296 296
297 case RegisterType::Temporary: 297 case RegisterType::Temporary:
298 return (int)offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 298 return offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
299 299
300 default: 300 default:
301 UNREACHABLE(); 301 UNREACHABLE();
@@ -303,13 +303,13 @@ struct UnitState {
303 } 303 }
304 } 304 }
305 305
306 static int OutputOffset(const DestRegister& reg) { 306 static size_t OutputOffset(const DestRegister& reg) {
307 switch (reg.GetRegisterType()) { 307 switch (reg.GetRegisterType()) {
308 case RegisterType::Output: 308 case RegisterType::Output:
309 return (int)offsetof(UnitState::Registers, output) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 309 return offsetof(UnitState::Registers, output) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
310 310
311 case RegisterType::Temporary: 311 case RegisterType::Temporary:
312 return (int)offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 312 return offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
313 313
314 default: 314 default:
315 UNREACHABLE(); 315 UNREACHABLE();
diff --git a/src/video_core/shader/shader_jit_x64.cpp b/src/video_core/shader/shader_jit_x64.cpp
index b9a0b19e3..0c02976ac 100644
--- a/src/video_core/shader/shader_jit_x64.cpp
+++ b/src/video_core/shader/shader_jit_x64.cpp
@@ -144,7 +144,7 @@ static const u8 NO_DEST_REG_MASK = 0xf;
144 */ 144 */
145void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, X64Reg dest) { 145void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, X64Reg dest) {
146 X64Reg src_ptr; 146 X64Reg src_ptr;
147 int src_offset; 147 size_t src_offset;
148 148
149 if (src_reg.GetRegisterType() == RegisterType::FloatUniform) { 149 if (src_reg.GetRegisterType() == RegisterType::FloatUniform) {
150 src_ptr = UNIFORMS; 150 src_ptr = UNIFORMS;
@@ -154,6 +154,9 @@ void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, Source
154 src_offset = UnitState<false>::InputOffset(src_reg); 154 src_offset = UnitState<false>::InputOffset(src_reg);
155 } 155 }
156 156
157 int src_offset_disp = (int)src_offset;
158 ASSERT_MSG(src_offset == src_offset_disp, "Source register offset too large for int type");
159
157 unsigned operand_desc_id; 160 unsigned operand_desc_id;
158 if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD || 161 if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD ||
159 instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) { 162 instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) {
@@ -163,7 +166,7 @@ void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, Source
163 operand_desc_id = instr.mad.operand_desc_id; 166 operand_desc_id = instr.mad.operand_desc_id;
164 167
165 // Load the source 168 // Load the source
166 MOVAPS(dest, MDisp(src_ptr, src_offset)); 169 MOVAPS(dest, MDisp(src_ptr, src_offset_disp));
167 } else { 170 } else {
168 operand_desc_id = instr.common.operand_desc_id; 171 operand_desc_id = instr.common.operand_desc_id;
169 172
@@ -173,13 +176,13 @@ void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, Source
173 if (src_num == offset_src && instr.common.address_register_index != 0) { 176 if (src_num == offset_src && instr.common.address_register_index != 0) {
174 switch (instr.common.address_register_index) { 177 switch (instr.common.address_register_index) {
175 case 1: // address offset 1 178 case 1: // address offset 1
176 MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_0, 1, src_offset)); 179 MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_0, SCALE_1, src_offset_disp));
177 break; 180 break;
178 case 2: // address offset 2 181 case 2: // address offset 2
179 MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_1, 1, src_offset)); 182 MOVAPS(dest, MComplex(src_ptr, ADDROFFS_REG_1, SCALE_1, src_offset_disp));
180 break; 183 break;
181 case 3: // adddress offet 3 184 case 3: // address offset 3
182 MOVAPS(dest, MComplex(src_ptr, LOOPCOUNT_REG, 1, src_offset)); 185 MOVAPS(dest, MComplex(src_ptr, LOOPCOUNT_REG, SCALE_1, src_offset_disp));
183 break; 186 break;
184 default: 187 default:
185 UNREACHABLE(); 188 UNREACHABLE();
@@ -187,7 +190,7 @@ void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, Source
187 } 190 }
188 } else { 191 } else {
189 // Load the source 192 // Load the source
190 MOVAPS(dest, MDisp(src_ptr, src_offset)); 193 MOVAPS(dest, MDisp(src_ptr, src_offset_disp));
191 } 194 }
192 } 195 }
193 196
@@ -224,14 +227,17 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
224 227
225 SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] }; 228 SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] };
226 229
230 int dest_offset_disp = (int)UnitState<false>::OutputOffset(dest);
231 ASSERT_MSG(dest_offset_disp == UnitState<false>::OutputOffset(dest), "Destinaton offset too large for int type");
232
227 // If all components are enabled, write the result to the destination register 233 // If all components are enabled, write the result to the destination register
228 if (swiz.dest_mask == NO_DEST_REG_MASK) { 234 if (swiz.dest_mask == NO_DEST_REG_MASK) {
229 // Store dest back to memory 235 // Store dest back to memory
230 MOVAPS(MDisp(REGISTERS, UnitState<false>::OutputOffset(dest)), src); 236 MOVAPS(MDisp(REGISTERS, dest_offset_disp), src);
231 237
232 } else { 238 } else {
233 // Not all components are enabled, so mask the result when storing to the destination register... 239 // Not all components are enabled, so mask the result when storing to the destination register...
234 MOVAPS(SCRATCH, MDisp(REGISTERS, UnitState<false>::OutputOffset(dest))); 240 MOVAPS(SCRATCH, MDisp(REGISTERS, dest_offset_disp));
235 241
236 if (Common::GetCPUCaps().sse4_1) { 242 if (Common::GetCPUCaps().sse4_1) {
237 u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1); 243 u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1);
@@ -250,7 +256,7 @@ void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) {
250 } 256 }
251 257
252 // Store dest back to memory 258 // Store dest back to memory
253 MOVAPS(MDisp(REGISTERS, UnitState<false>::OutputOffset(dest)), SCRATCH); 259 MOVAPS(MDisp(REGISTERS, dest_offset_disp), SCRATCH);
254 } 260 }
255} 261}
256 262