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| author | 2018-06-05 23:46:23 -0400 | |
|---|---|---|
| committer | 2018-06-06 18:09:06 -0400 | |
| commit | 4669f15f8be26ddf3c1cc02d8aac78656c41d361 (patch) | |
| tree | 3e6968e43a2377a0bfd8bb45f3ea8141f9bd0568 | |
| parent | gl_shader_gen: Add uniform handling for indirect const buffer access. (diff) | |
| download | yuzu-4669f15f8be26ddf3c1cc02d8aac78656c41d361.tar.gz yuzu-4669f15f8be26ddf3c1cc02d8aac78656c41d361.tar.xz yuzu-4669f15f8be26ddf3c1cc02d8aac78656c41d361.zip | |
gl_shader_decompiler: Implement LD_C instruction.
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 16 | ||||
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 27 |
2 files changed, 43 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 7a74771ce..af18c2d81 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -175,6 +175,15 @@ enum class FloatRoundingOp : u64 { | |||
| 175 | Trunc = 3, | 175 | Trunc = 3, |
| 176 | }; | 176 | }; |
| 177 | 177 | ||
| 178 | enum class UniformType : u64 { | ||
| 179 | UnsignedByte = 0, | ||
| 180 | SignedByte = 1, | ||
| 181 | UnsignedShort = 2, | ||
| 182 | SignedShort = 3, | ||
| 183 | Single = 4, | ||
| 184 | Double = 5, | ||
| 185 | }; | ||
| 186 | |||
| 178 | union Instruction { | 187 | union Instruction { |
| 179 | Instruction& operator=(const Instruction& instr) { | 188 | Instruction& operator=(const Instruction& instr) { |
| 180 | value = instr.value; | 189 | value = instr.value; |
| @@ -253,6 +262,11 @@ union Instruction { | |||
| 253 | } ffma; | 262 | } ffma; |
| 254 | 263 | ||
| 255 | union { | 264 | union { |
| 265 | BitField<48, 3, UniformType> type; | ||
| 266 | BitField<44, 2, u64> unknown; | ||
| 267 | } ld_c; | ||
| 268 | |||
| 269 | union { | ||
| 256 | BitField<0, 3, u64> pred0; | 270 | BitField<0, 3, u64> pred0; |
| 257 | BitField<3, 3, u64> pred3; | 271 | BitField<3, 3, u64> pred3; |
| 258 | BitField<7, 1, u64> abs_a; | 272 | BitField<7, 1, u64> abs_a; |
| @@ -378,6 +392,7 @@ public: | |||
| 378 | KIL, | 392 | KIL, |
| 379 | BRA, | 393 | BRA, |
| 380 | LD_A, | 394 | LD_A, |
| 395 | LD_C, | ||
| 381 | ST_A, | 396 | ST_A, |
| 382 | TEX, | 397 | TEX, |
| 383 | TEXQ, // Texture Query | 398 | TEXQ, // Texture Query |
| @@ -552,6 +567,7 @@ private: | |||
| 552 | INST("111000110011----", Id::KIL, Type::Flow, "KIL"), | 567 | INST("111000110011----", Id::KIL, Type::Flow, "KIL"), |
| 553 | INST("111000100100----", Id::BRA, Type::Flow, "BRA"), | 568 | INST("111000100100----", Id::BRA, Type::Flow, "BRA"), |
| 554 | INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"), | 569 | INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"), |
| 570 | INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"), | ||
| 555 | INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"), | 571 | INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"), |
| 556 | INST("1100000000111---", Id::TEX, Type::Memory, "TEX"), | 572 | INST("1100000000111---", Id::TEX, Type::Memory, "TEX"), |
| 557 | INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"), | 573 | INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"), |
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 44c8bf4d4..a703b9151 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -1090,6 +1090,33 @@ private: | |||
| 1090 | attribute); | 1090 | attribute); |
| 1091 | break; | 1091 | break; |
| 1092 | } | 1092 | } |
| 1093 | case OpCode::Id::LD_C: { | ||
| 1094 | ASSERT_MSG(instr.ld_c.unknown == 0, "Unimplemented"); | ||
| 1095 | |||
| 1096 | std::string op_a = | ||
| 1097 | regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 0, instr.gpr8, | ||
| 1098 | GLSLRegister::Type::Float); | ||
| 1099 | std::string op_b = | ||
| 1100 | regs.GetUniformIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, instr.gpr8, | ||
| 1101 | GLSLRegister::Type::Float); | ||
| 1102 | |||
| 1103 | switch (instr.ld_c.type.Value()) { | ||
| 1104 | case Tegra::Shader::UniformType::Single: | ||
| 1105 | regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1); | ||
| 1106 | break; | ||
| 1107 | |||
| 1108 | case Tegra::Shader::UniformType::Double: | ||
| 1109 | regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1); | ||
| 1110 | regs.SetRegisterToFloat(instr.gpr0.Value() + 1, 0, op_b, 1, 1); | ||
| 1111 | break; | ||
| 1112 | |||
| 1113 | default: | ||
| 1114 | NGLOG_CRITICAL(HW_GPU, "Unhandled type: {}", | ||
| 1115 | static_cast<unsigned>(instr.ld_c.type.Value())); | ||
| 1116 | UNREACHABLE(); | ||
| 1117 | } | ||
| 1118 | break; | ||
| 1119 | } | ||
| 1093 | case OpCode::Id::ST_A: { | 1120 | case OpCode::Id::ST_A: { |
| 1094 | ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested"); | 1121 | ASSERT_MSG(instr.attribute.fmt20.size == 0, "untested"); |
| 1095 | regs.SetOutputAttributeToRegister(attribute, instr.attribute.fmt20.element, | 1122 | regs.SetOutputAttributeToRegister(attribute, instr.attribute.fmt20.element, |